SILVACO 073125 Webinar 800x100
WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4182
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4182
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)

Designing Next Generation Memory Interfaces: Modeling, Analysis, and Tips

Designing Next Generation Memory Interfaces: Modeling, Analysis, and Tips
by Mike Gianfagna on 03-04-2020 at 10:00 am

IBIS AMI vs. Transient

At DesignCon 2020, there was a presentation by Micron, Socionext and Cadence that discussed design challenges and strategies for using the new low-power DDR specification (LPDDR5). As is the case with many presentations at DesignCon, ecosystem collaboration was emphasized. Justin Butterfield (senior engineer at Micron)… Read More


Reliability Challenges in Advanced Packages and Boards

Reliability Challenges in Advanced Packages and Boards
by Herb Reiter on 03-02-2020 at 10:00 am

CTE Stress ANSYS SemiWiki

Today’s Market Requirements
Complex electronic devices and (sub)systems work for us in important applications, such as aircrafts, trains, trucks, passenger vehicles as well as building infrastructure, manufacturing equipment, medical systems and more. Very high reliability (the ability of a product to meet all requirements… Read More


An Important Step in Tackling the Debug Monster

An Important Step in Tackling the Debug Monster
by Daniel Nenni on 02-28-2020 at 6:00 am

AMIQ EDA Compare Report SemiWiki

If you’ve spent any time at all in the semiconductor industry, you’ve heard the statement that verification consumes two-thirds or more of the total resources on a chip project. The estimates range up to 80%, in which case verification is taking four times the effort of the design process. The exact ratio is subject to debate, but… Read More


Navigating Memory Choices for Your Next Low-Power Design

Navigating Memory Choices for Your Next Low-Power Design
by Mike Gianfagna on 02-27-2020 at 10:00 am

Memory options

Choosing a memory architecture can be a daunting task. There are many options to choose from, each with their own power, performance, area and cost profile. The right choice can make a new design competitive and popular in the market. The wrong choice can doom the whole project to failure.

Vadhiraj Sankaranarayanan, senior technical… Read More


Mentor Helps Mythic Implement Analog Approach to AI

Mentor Helps Mythic Implement Analog Approach to AI
by Tom Simon on 02-27-2020 at 6:00 am

Mythic AMS Verification Challenges

The entire field of Artificial Intelligence (AI) has resulted from what is called “first principles thinking”, where problems are re-examined using a complete reassessment of the underlying issues and potential solutions. It is a testament to how effective this can be that AI is being used for a rapidly expanding number of applications… Read More


Thermal Issues and Solutions for 3D ICs: Latest Updates and Future Prospect

Thermal Issues and Solutions for 3D ICs: Latest Updates and Future Prospect
by Mike Gianfagna on 02-26-2020 at 10:00 am

2D vs. 3D heat maps

At DesignCon 2020, ANSYS held a series of sponsored presentations. I was able to attend a couple of them.  These were excellent events with the material delivered by talented and high-energy speakers. The DesignCon technical program has many dimensions beyond the conference tracks. One of the presentations dealt with 3D ICs.… Read More


Hybrid Verification for Deep Sequential Convergence

Hybrid Verification for Deep Sequential Convergence
by Bernard Murphy on 02-26-2020 at 6:00 am

Hybrid Verification Synopsys

I’m always curious to learn what might be new in clock domain crossing (CDC) verification, having dabbled in this area in my past. It’s an arcane but important field, the sort of thing that if missed can put you out of business, but otherwise only a limited number of people want to think about it to any depth.

 

The core issue is something… Read More


Build Custom SoC Assembly Platforms

Build Custom SoC Assembly Platforms
by Bernard Murphy on 02-25-2020 at 6:00 am

STAR RTL design builder

I’ve talked with Defacto on and off for several years – Chouki Aktouf (CEO) and Bastien Gratreaux (Marketing). I was in a similar line of business back in Atrenta. Now I’m just enjoying myself, I’ve written a few blogs for them. I’ll confess I wondered why they wouldn’t struggle with the same problems we’d had. Script-driven RTL editing,… Read More


Edge Computing – The Critical Middle Ground

Edge Computing – The Critical Middle Ground
by Mike Gianfagna on 02-21-2020 at 10:00 am

Computing hierarchy

Ron Lowman, product marketing manager at Synopsys, recently posted an interesting technical bulletin on the Synopsys website entitled How AI in Edge Computing Drives 5G and the IoT. There’s been a lot of discussion recently about the emerging processing hierarchy of edge devices (think cell phone or self-driving car), cloud… Read More


Webinar on Concurrent Electro-Thermal Analysis for PowerMOS Devices to Improve Performance and Reliability

Webinar on Concurrent Electro-Thermal Analysis for PowerMOS Devices to Improve Performance and Reliability
by Tom Simon on 02-20-2020 at 10:00 am

PTM-ET Sidecut view

PowerMOS devices play a major role in a variety of power converter and control circuits. Some examples of their applications include PMICs, or boost and buck converters. Often these are used in mobile and IoT devices to convert battery voltages to circuit operating voltages.

Due to their size and internal complexity PowerMOS … Read More