Constrained random methods in simulation are universally popular, still can the method be improved? Paul Cunningham (Senior VP/GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas. As always, feedback welcome.… Read More
Tensilica Processor Cores Enable Sensor Fusion For Robust Perception
While sensor-based control and activation systems have been around for several decades, the development and integration of sensors into control systems have significantly evolved over time. Early sensor-based control systems utilized basic sensing elements like switches, potentiometers and pressure sensors and were … Read More
Deep Learning for Fault Localization. Innovation in Verification
A new look at fault localization and repair in debug using learning based on deep semantic features. Paul Cunningham (Senior VP/GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas. As always, feedback welcome.
The
… Read MoreUS giant swoops for British chipmaker months after Chinese sale blocked on national security grounds
According to UK based The Telegraph Pulsic is a chip maker and Cadence is a swooping US giant. I guess you have to stretch the truth to get those precious clicks these days. Even so this is a strategic acquisition for Cadence.
Pulsic is a 20+ year old EDA software company that offers chip planning and implementation software for custom… Read More
Opinions on Generative AI at CadenceLIVE
According to some AI dreamers, we’re almost there. We’ll no longer need hardware or software design experts—just someone to input basic requirements from which fully realized system technologies will drop out the other end. Expert opinions in the industry are enthusiastic but less hyperbolic. Bob O’Donnell, president, founder… Read More
Takeaways from CadenceLIVE 2023
Given popular fascination it seems impossible these days to talk about anything other than AI. At CadenceLIVE, it was refreshing to be reminded that the foundational methods on which designs of any type remain and will always be dominated in all aspects of engineering by deep, precise, and scalable math, physics, computer science… Read More
Anirudh Keynote at Cadence Live
Anirudh is an engaging speaker with a passion for technology. Acknowledging the sign of the times, he sees significant value-add in AI but reminded us that it is a still supporting actor in system design and other applications where star roles will continue to be played by computational software that’s founded in hard science, … Read More
Petri Nets Validating DRAM Protocols. Innovation in Verification
A Petri nets blog scored highest in engagement last year. This month we review application of the technique to validating an expanding range of JEDEC memory standards. Paul Cunningham (Senior VP/GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue… Read More
More Software-Based Testing, Less Errata
In verification there is an ever-popular question, “When can we stop verifying?” The intent behind the question is “when will we have found all the important bugs?” but the reality is that you stop verifying when you run out of time. Any unresolved bugs appear in errata lists delivered with the product (some running to 100 or more … Read More
What’s New with Cadence Virtuoso?
It was back in 1991 that Cadence first announced the Virtuoso product name, and here we are 32 years later and the product is alive and doing quite well. Steven Lewis from Cadence gave me an update on something new that they call Virtuoso Studio, and it’s all about custom IC design for the real world. In those 32 years we’ve… Read More