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As the oldest and largest EDA conference, the Design Automation Conference (DAC) brings the best minds together to present, discuss, showcase and debate the latest and greatest advances in EDA. It accomplishes this in the form of technical papers, talks, company booths, product pavilions and panel discussions.
A key aspect … Read More
As we established last year, we will use the January issue of this blog to look back at the papers we reviewed last year. We lost Jim Hogan and the benefit of his insight early last year, but we gained a new and also well-known expert in Raúl Camposano (another friend of Jim). Paul (GM, Verification at Cadence), Raúl (Silicon Catalyst,… Read More
At the recent Design Automation Conference, Cadence presented their methodology for incorporating performance degradation measures due to device aging into a static timing analysis flow. [1] (The work was a collaborative project with Samsung Electronics.) This article reviews the highlights of their presentation.
Background… Read More
Combining simulation and symbolic methods is an attractive way to excite rare branches in block-level verification, but is this method really scalable? Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO) and I continue our series on research ideas. As always,… Read More
The incredible growth that the semiconductor industry has enjoyed over the last several decades is attributed to Moore’s Law. While no one argues that point, there is also industry wide acknowledgment that Moore’s Law started slowing down around the 7nm process node. While die-size reductions still scale, performance jumps… Read More
Paul, Raúl and I are having fun with our Innovation in Verification series, and you seem to be also, judging by the hit rates we’re getting. We track these carefully to judge what you find most interesting and what seems to fall more under the category of “Meh”. Paul and others also get informal feedback in client meetings but it would… Read More
Learning-Based Power Modeling. Innovation in Verification
Is it possible to automatically generate abstract power models for complex IP which can both run fast and preserve high estimation accuracy? Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO) and… Read More
Earbuds are one of the fastest growing market segments, which is creating the need for audio DSPs with higher performance and a smaller energy footprint. More than just being wireless speakers – earbuds, and wearables for that matter, have become a sophisticated extension of the user interface of phones and laptops, etc.… Read More
Multicore systems working with shared memory must support a well-defined model for consistency of thread accesses to that memory. There are multiple possible consistency models. Can a design team run memory consistency checks at RTL? Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur,… Read More
This is another level-up story, a direction I am finding increasingly appealing. This is when a critical supplier in the electronics value chain moves beyond islands of design automation to provide an integrated solution for the front-to-back design for capabilities now essential for automotive and industrial automation … Read More
Podcast EP16: Hyperscale Computing & Changes in the Datacenter
Podcast EP90: A Tour of Cadence’s Cloud Solutions with Mahesh Turaga
Podcast EP105: Cadence STA Strategy and Capabilities, Today and Tomorrow with Brandon Bautz
Podcast EP112: How Cadence is Revolutionizing Full-Chip Signoff with Certus
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