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Who will Win in the Chiplet War?

Who will Win in the Chiplet War?
by Daniel Nenni on 01-16-2023 at 6:00 am

Chiplet APEC

The first Chiplet specific conference is coming up which is a milestone in itself. As we know the only thing new about chiplets is the name but when there is a dedicated conference to such a specific thing you know it has officially “arrived”. There is even a cool new tagline: Chiplets make huge chips happen!

“The First Annual Chiplet… Read More


The Era of Chiplets and Heterogeneous Integration: Challenges and Emerging Solutions to Support 2.5D and 3D Advanced Packaging

The Era of Chiplets and Heterogeneous Integration: Challenges and Emerging Solutions to Support 2.5D and 3D Advanced Packaging
by Kalar Rajendiran on 12-27-2022 at 6:00 am

High End Performance Packaging Spectrum

From the multi-chip-modules (MCM) of yester years to today’s System-in-Package (SiP) implementations, things have progressed a lot in terms of package technology. The chiplet movement is not only a big beneficiary of today’s advanced package technologies but drives further advances in this technology area. While a chiplets-based… Read More


Chiplets UCIe Require Verification

Chiplets UCIe Require Verification
by Daniel Nenni on 12-20-2022 at 6:00 am

UCIe VIP Truechip

Chiplets have been trending on SemiWiki for the past two years and I think that will continue into the distant future. As a potential way to unclog Moore’s Law, you can bet the semiconductor ecosystem will prove once again to be a chiplet force of nature driving semiconductor company roadmaps to smaller and better things.

To be clear,… Read More


Synopsys Crosses $5 Billion Milestone!

Synopsys Crosses $5 Billion Milestone!
by Daniel Nenni on 12-14-2022 at 6:00 am

Synopsys NASDAQ SemiWiki

“We intend to grow revenue 14% to 15%, continue to drive notable ops margin expansion and aim for approximately 16% non-GAAP earnings per share growth.”

Synopsys, Inc. (NASDAQ:SNPS) Q4 2022 Earnings Call Transcript

Synopsys is the EDA bellwether since they report early and are the #1 EDA and #1 IP company.  In addition to crossing… Read More


Architectural Planning of 3D IC

Architectural Planning of 3D IC
by Daniel Payne on 11-15-2022 at 10:00 am

3D IC min

Before chiplets arrived, it seemed like designing an electronic system was a bit simpler, as a system on chip (SoC) methodology was well understood, and each SoC was mounted inside a package, then the packages for each component were interconnected on a printed circuit board (PCB). The emerging trend to design a 3D IC using chiplets… Read More


TSMC Expands the OIP Ecosystem!

TSMC Expands the OIP Ecosystem!
by Daniel Nenni on 10-28-2022 at 6:00 am

TSMC OIP 2022 Roadmap

This was the 12th TSMC OIP and it did not disappoint. The attendance was back to pre pandemic levels, there was interesting news and great presentations. We will cover the presentations in more depth after the virtual event which is on November 10th. You can register HERE.

As I mentioned in my previous post, the Jim Keller Keynote … Read More


Moore’s Law is Dead – Long-live the Chiplet!

Moore’s Law is Dead – Long-live the Chiplet!
by Paul McWilliams on 09-30-2022 at 8:00 am

Moores Law Slows

Dr. Gordon Moore was the Director of Research and Development at Fairchild when he wrote the paper, “Cramming More Components onto Integrated Circuits” that was published in the April 19, 1965 issue of Electronics.  Following this publication, Dr. Carver Mead of Caltech declared Dr. Moore’s predictions as “Moore’s… Read More


UCIe Specification Streamlines Multi-Die System Design with Chiplets

UCIe Specification Streamlines Multi-Die System Design with Chiplets
by Dave Bursky on 09-26-2022 at 10:00 am

protocol stack 1

Over the last few years, the design of application-specific ICs as well as high-performance CPUs and other complex ICs has hit a proverbial wall. This wall is built from several issues: first, chip sizes have grown so large that they can fill the entire mask reticle and that could limit future growth. Second, the large chip size impacts… Read More


Ansys’ Emergence as a Tier 1 EDA Player— and What That Means for 3D-IC

Ansys’ Emergence as a Tier 1 EDA Player— and What That Means for 3D-IC
by Daniel Nenni on 09-20-2022 at 10:00 am

Ansys chip package board

Over its 40+ year history, electronic design automation (EDA) has seen many companies rise, fall, and merge. In the beginning, in the 1980s, the industry was dominated by what came to be known as the big three — Daisy Systems, Mentor Graphics, and Valid Logic (the infamous “DMV”). The Big 3 has morphed over the years, eventually settling… Read More


Five Key Workflows For 3D IC Packaging Success

Five Key Workflows For 3D IC Packaging Success
by Kalar Rajendiran on 08-31-2022 at 6:00 am

3D IC design workflows

An earlier blog started with the topic of delivering 3D IC innovations faster. The blog covered the following foundational enablers for successful heterogeneous 3D IC implementation.

  • System Co-Optimization (STCO) approach
  • Transition from design-based to systems-based optimization
  • Expanding the supply chain and tool
Read More