You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please,
join our community today!
WP_Term Object
(
[term_id] => 15
[name] => Cadence
[slug] => cadence
[term_group] => 0
[term_taxonomy_id] => 15
[taxonomy] => category
[description] =>
[parent] => 157
[count] => 598
[filter] => raw
[cat_ID] => 15
[category_count] => 598
[category_description] =>
[cat_name] => Cadence
[category_nicename] => cadence
[category_parent] => 157
[is_post] =>
)
WP_Term Object
(
[term_id] => 15
[name] => Cadence
[slug] => cadence
[term_group] => 0
[term_taxonomy_id] => 15
[taxonomy] => category
[description] =>
[parent] => 157
[count] => 598
[filter] => raw
[cat_ID] => 15
[category_count] => 598
[category_description] =>
[cat_name] => Cadence
[category_nicename] => cadence
[category_parent] => 157
[is_post] =>
)
One of the Designer Track at this year’s DAC focused on the popular topic of automotive electronics. The title was particularly on-point, The Modern Automobile: A Safety and Security “Hot Zone”. The session was chaired by Debdeep Mukhopadhyay, a Professor at the Indian Institute of Technology in Kharagpur.
This special, invited… Read More
DAC was full of great panels, research papers and chip design stories this year, the same as other years. Being a virtual show, there were some differences of course. I’ve heard attendance was way up, allowing a lot more folks to experience the technical program. This is likely to be true for a virtual event. I’m sure we’ll see more… Read More
Presenters took a trip down memory lane at DAC this year by having a panel discussion on HLS (High Level Synthesis) spanning from 1974 to 2020, and that time period aligns with when I first graduated from the University of Minnesota in 1978, starting chip design at Intel, then later transitioning into EDA companies by 1986. Marilyn… Read More
Semiconductor technology advances have a way of rewriting the rule book. As process geometries shrink, subtle effects graduate to mainstream problems. Performance curves can become inverted. And no matter what else occurs, low power demands are constantly reducing voltage and design margins along with it. Sometimes these… Read More
After we detect a bug, can we use AI to locate the fault, or at least get close? Paul Cunningham (GM of Verification at Cadence), Jim Hogan and I continue our series on novel research ideas, through a paper in software verification we find equally relevant to hardware. Feel free to comment.
The Innovation
This month’s pick is… Read More
A few months ago, I wrote about the announcement of a new digital full flow from Cadence. In that piece, I focused on the machine learning (ML) aspects of the new tool. I had covered a discussion with Cadence’s Paul Cunningham a week before that explored ML in Cadence products, so it was timely to dive into a real-world example of the … Read More
Cadence vManager™ Verification Management provides what the company describes as metric-driven signoff. Anyone who has been through the tapeout process for a complex SoC knows the perils of verification sign-off. How much of the chip has been verified? What’s left to do? Will all be ready when the tapeout deadline arrives? … Read More
Can we predict where bugs are most likely to be found, to better direct testing? Paul Cunningham (GM of Verification at Cadence), Jim Hogan and I continue our series on novel research ideas, again through a paper in software verification we find equally relevant to hardware. Feel free to comment if you agree or disagree.
The Innovation… Read More
Mutation testing is an intriguing idea, but is it useful? Paul Cunningham (GM of Verification at Cadence), Jim Hogan and I continue our series on novel research ideas, here looking at a paper examining the pros and cons of this topic. Feel free to comment if you agree or disagree.
The Innovation
This month’s pick is Which Software … Read More
Based on what I’m seeing, I believe Cadence is looking at the world a bit differently these days. I first reported about their approach to machine learning for EDA in March, and then there was their white paper about Intelligent System Design in April. It’s now May, and Cadence is shaking things up again with a new white paper entitled… Read More