Visual Debug for Formal Verification

Visual Debug for Formal Verification
by Steve Hoover on 04-20-2022 at 6:00 am

ThisIsFormal

Success with Open-Source Formal Verification

The dream of 100% confidence is compelling for silicon engineers. We all want that big red button to push that magically finds all of our bugs for us. Verification, after all, accounts for roughly two-thirds of logic design effort. Without that button, we have to create reference models,… Read More


A Free RISC-V CPU Core Builder – Democratizing CPUs

A Free RISC-V CPU Core Builder – Democratizing CPUs
by Steve Hoover on 06-27-2021 at 6:00 am

warp v.org

There are now over a hundred RISC-V CPU cores listed on riscv.org‘s RISC-V Exchange! Amazing. If you need a RISC-V CPU core, you’ll likely be able to find one that suits your needs… if you evaluate a hundred CPU cores to find it.

Or, now, you can configure exactly the core you need, and have it built in seconds, for free! WARP-V Read More