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3D and 2.5D (silicon interposer) designs create new challenges for EDA. Not all of them are in the most obvious areas. Mentor has an interesting presentation on what is required for verification and testing of these types of designs. Obviously it is somewhat Mentor-centric but in laying out the challenges it is pretty much agnostic.… Read More
“Before we acquire great power we must acquire wisdom to use it well”
Ralph Waldo Emerson
Making good architectural decisions for controlling power consumption and ensuring power integrity requires a good analysis of the current requirements and how they vary. Low power designs, and today there really aren’t… Read More
Apple’s iPhone did well in Q4 according to Neilsen who polled recent buyers of smartphones. Of people who had purchased a smartphone in the previous 3 months (roughly Q4) 44.5% chose an iPhone (up from 25.1% in October, roughly Q3). But Android retained the lead with a 46.9% share, down from 61.6% in October. How many phones… Read More
For the next few days Atrenta is running a series of 30 minute live webinars to discuss the new solutions and approaches that are required to improve the way SoC designs are created and modified.
The webinars are at the following times:
Chips, packages and circuit boards (systems, hence CPS) used to be three separate domains with their own tools that barely interacted at all. If you were lucky, reassigning a pin on a package wouldn’t have to be done manually in all 3 places. But now, from a signal integrity, noise, power point of view these three domains must… Read More
Note that there are several DAC deadlines coming up in the next couple of weeks.
The deadline for user track submissions is January 17th (next Tuesday). Submission requires an extended abstract. See here for details.
The deadline for DAC workshops is January 19th (next Thursday). A proposal is required. See here for details.
The… Read More
One of the fun things when a company gets big but is still private, like Atrenta, is that you start to get invited to events like the Needham Growth Conference that took place earlier this week in New York. When I ran Compass Design Automation, which at the time was about $55M in revenue, I remember going to a couple of these events. At … Read More
EDAC (EDA consortium) market statistics service announced the data for Q3 of 2011. Revenue increased 18.1% (versus 2010) to $1543.9 million. Sequentially (versus Q2) revenue increase 7.4%. Annualized, that puts EDA at over $6B for, I belive, the first time ever. Wally Rhines, who is EDAC chair (and CEO of Mentor) commented that… Read More
As chips have become larger, one of the more challenging steps is full-chip signoff. Lots of other steps in the design process can work on just a part of the problem, but by definition full-chip signoff has to work on the full chip. But it is not just that chips have got larger, the number of corners that need to be validated has also exploded.… Read More
One of the most significant announcements at the consumer electronics show (CES) this week was Intel’s Medfield, an Atom-based smartphone SoC. The SoC itself is unremarkable, perhaps a little better than ARM Cortex-based SoCs in some areas, worse in others. The reason it is significant is that Motorola (soon to be Google,… Read More
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Elon Musk Given CHIPS Act & AI Oversight – Mulls Relocation of Taiwanese Fabs