Author: Don Dingee

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Testing Ethernet with virtual co-modeling

Testing Ethernet with virtual co-modeling
by Don Dingee on 08-24-2015 at 12:00 pm
Categories: EDA, Siemens EDA

Ethernet is suddenly a hot topic in SoC design again. The biggest news may be this: it’s not just the cloud and enterprise networks. Those are still important applications. The cloud is driving hard for more ports at 25G server and 100G switch speeds according to a recent Dell’Oro Group report. Enterprise networks are driving for… Read More

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CEVA achieves first certified Bluetooth 4.2 IP

CEVA achieves first certified Bluetooth 4.2 IP
by Don Dingee on 08-18-2015 at 8:05 am
Categories: Ceva, IoT, IP

SoC designers working on chips for the IoT and wearables now have access to cutting-edge certified Bluetooth Smart technology from CEVA. At Bluetooth ASIA in Shanghai, CEVA announced the RivieraWaves Bluetooth Smart 4.2 IP Platform has achieved full certification by the Bluetooth SIG to the Bluetooth 4.2 specification using… Read More

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Aldec updates two EDA product lines

Aldec updates two EDA product lines
by Don Dingee on 08-12-2015 at 4:00 pm
Categories: Aldec, EDA

Continuous, incremental improvement based on customer feedback and insight from researchers is a pillar of the Aldec EDA strategy. Within the last two weeks, two of the Aldec product lines – Riviera-PRO, and ALINT-PRO-CDC – have seen new version releases. Here’s a quick look at some of the highlights of both.

Riviera-PRO 2015.06… Read More

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More FPGA-based prototype myths quashed

More FPGA-based prototype myths quashed
by Don Dingee on 08-03-2015 at 12:00 pm
Categories: EDA, FPGA, Synopsys

Speaking of having the right tools, FPGA-based prototyping has become as much if not more about the synthesis software than it is about the FPGA hardware. This is a follow-up to my post earlier this month on FPGA-based prototyping, but with a different perspective from another vendor. Instead of thinking about what else can be done… Read More

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Taking prototyping beyond prototypes

Taking prototyping beyond prototypes
by Don Dingee on 07-22-2015 at 12:00 pm
Categories: EDA, FPGA, S2C EDA

Everyone has heard the expression, “Half the job is having the right tool.” In the case of FPGA-based prototyping, however, the right tool for the job is only the beginning. What teams really need to think through is what exactly should be done with an FPGA-based prototyping tool?

The obvious answer is prototyping an SoC, pre-silicon.… Read More

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Xilinx in an ARM-fueled post-Altera world

Xilinx in an ARM-fueled post-Altera world
by Don Dingee on 06-29-2015 at 5:30 pm
Categories: Arm, FPGA, Xilinx

When the news broke about the on, off, and on-again Intel-Altera merger a few weeks ago, I checked off another box on my Six Degrees of Kevin Bacon scorecard. That plus a $5 bill gets me a Happy Meal at McDonalds, but in a post-Altera world, it might be worth more.

On January 16, 2008, I’m sitting in a meeting with some Intel strategic marketing… Read More

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DDR stands for Don’t Do (Just) RTL

DDR stands for Don’t Do (Just) RTL
by Don Dingee on 06-16-2015 at 9:00 pm
Categories: EDA, Synopsys

In optimizing SoC design for performance, there is so much focus on how fast a CPU core is, or a GPU core, or peripherals, or even the efficiency of the chip-level interconnect. Most designers also understand selecting high performance memory at a cost sweet spot, and optimizing physical layout to clock it as fast as possible within… Read More

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5 Things Chipmakers Are Missing on the IoT

5 Things Chipmakers Are Missing on the IoT
by Don Dingee on 06-07-2015 at 7:00 pm
Categories: General, IoT

When the RISC movement surfaced in 1982, researchers analyzed UNIX to discover what instructions multi-user code was actually using, and then designed an instruction set and execution pipeline to do that better. Fewer instructions meant fewer transistors, which led to less power consumption – although in the original… Read More

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Aldec packs 6 UltraScale parts on HES-7

Aldec packs 6 UltraScale parts on HES-7
by Don Dingee on 06-01-2015 at 12:00 pm
Categories: Aldec, EDA, FPGA

A few months ago, when the Xilinx UltraScale VU440 FPGA began shipping, one of the immediate claims was a quad-FPGA-based prototyping board touted as “Godzilla’s Butcher on Steroids”. That was a refreshing and creative PR approach, frankly. I’m always careful with less creative terms like “world’s biggest” or “world’s fastest”,… Read More

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Virtual HIL and the 100M LOC car

Virtual HIL and the 100M LOC car
by Don Dingee on 05-28-2015 at 7:00 pm
Categories: Automotive, EDA, Synopsys

Aerospace and defense applications have traditionally leveraged hardware-in-the-loop (HIL) testing to overcome several issues. A big one is how expensive the physical system is. Even breaking down the system into subsystems for test can still be too expensive when fielding more than a couple test stations. Modeling elements… Read More