Back in February when we shared the Sonics philosophy on the ICE-Grain Power Architecture for hardware-based SoC power management, I speculated we’d know more by DAC 2016. Sonics is hitting the road with a new live seminar coming to Silicon Valley this month and Austin during DAC – and the news is big.… Read More
Author: Don Dingee
One FPGA synthesis flow for different IP types
Both Altera and Xilinx are innovative companies with robust ecosystems, right? It would be a terrible shame if you located the perfect FPGA IP block for a design, but couldn’t use it because it was in the “wrong” format for your preferred FPGA. What if there were a way around that?
There is a compelling argument to use each FPGA vendor’s… Read More
Body-biasing for ARM big or LITTLE in GF 22FDX
GLOBALFOUNDRIES has been evangelizing their 22FDX FD-SOI process for a few months; readers may have seen Tom Simon’s write-up of their preview at ARM TechCon. Dr. Joerg Winkler recently gave an updated webinar presentation of their approach in an implementation of ARM Cortex-A17 core.
By now, you’ve probably heard that 22FDX… Read More
BLDC motor control kit targets power savings
We tend to focus on connectivity and sensors for the IoT, however there is a third element to what I call the “Edge Device Triad” that is just as important: actuators. Making things move with microcontrollers (MCUs) is a science in and of itself. For small size and low weight combined with decent mechanical power, designers are opting… Read More
Cadence loads up on MACs for vision with CNNs
For vision DSP IP running convolutional neural networks (CNNs), a big driver of performance is increasing the bits processed per cycle with parallel MACs. Tom Simon did a great job in recent posts of introducing CNNs at a high level, so I’ll look at what is architecturally behind Cadence’s latest announcement: the Tensilica Vision… Read More
Webinar alert – VHDL guru says its time to move up
Many years ago when I worked for Ed Staiano at Motorola, I learned never to use the word “comfortable” in a career context. I’m comfortable being with family and friends. This new high-back chair I sit in at my new faux-cocobolo desk (slightly distressed chalk-painted wood and industrial piping, awesome) is comfortable,… Read More
Tcl scripts and managing messages in ASIC & FPGA debug
Our previous Blue Pearl post looked at the breadth of contextual visualization capability in the GUI to speed up debug. Two other important aspects of the ASIC & FPGA pre-synthesis workflow are automating analysis with scripts and managing the stream of messages produced. Let’s look at these aspects… Read More
Fast Track to a reconfigurable ASIC design
Licensing IP can be a pain, especially when the vendor’s business model has front-loaded costs to get started. Without an easy way to evaluate IP, justifying a purchase may be tough. With more mid-volume starts coming for the IoT, wearables, automotive, and other application segments, it’s a growing concern. Flex… Read More
Enterprise Design Management Engineered for SoCs
In my initial look at ClioSoft’s design management system created from the ground up for the semiconductor industry, I made the opening case for managing and reusing IP across an ASIC design organization. Let’s for a moment say we agree on the need for an enterprise software package to do design management… Read More
Cross-viewing improves ASIC & FPGA debug efficiency
We introduced the philosophy behind the Blue Pearl Software suite of tools for front-end analysis of ASIC & FPGA designs in a recent post. As we said in that discussion, effective automation helps find and remedy issues as each re-synthesis potentially turns up new defects. Why do Blue Pearl users say their tool suite is easier… Read More
More Headwinds – CHIPS Act Chop? – Chip Equip Re-Shore? Orders Canceled & Fab Delay