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Introduction
Circuit designers work at the transistor level and strive to get the ultimate in performance, layout density or low power by creating crafty circuit topologies in both schematics and layout. Along with this quest comes the daunting task of verifying that all of your rules and best practices about reliability have… Read More
Inroduction
In the early days we made paper plots of an IC layout then measured the width and length of interconnect segments with a ruler to add up all of the squares, then multiplied by the resistance per square. It was tedious, error prone and took way too much time, but we were rewarded with accurate parasitic values for our SPICE… Read More
Intro
Earlier this month I drove to Mentor Graphics in Wilsonville, Oregon and spoke with Michael Buehler-Garcia, Director of Marketing and Nancy Nguyen, TME, both part of the Calibre Design to Silicon Division. I’m a big fan of correct-by-construction thinking in EDA tools and what they had to say immediately caught my… Read More
Intro
On Friday I talked with Srinath Anantharaman by phone to gain some perspective on Hardware Configuration Management (HCM) versus Software Configuration Management (SCM), especially as it applies to the IC design flows in use today. In the 1990’s we both worked at Viewlogic in Fremont, CA and in 1997 Srinath founded… Read More
Last week I met with Joseph Davis, Ph.D. at Mentor Graphics in Wilsonville, Oregon to learn about a new product designed for full-custom IC layout designers to improve productivity.
The traditional flow for full-custom IC layout designers has been nearly unchanged for decades:
For IC designers creating full-custom or AMS designs there are plenty of challenges to getting designs done right on the first spin of silicon. Let me give you a sneak peek into what’s being discussed at the EDA Tech Forum in Santa Clara, CA on March 10th that will be of special interest to you:
3D TSV (Through Silicon Vias) are… Read More
When I worked at Intel as a circuit design engineer I could talk directly with the technology development engineers to understand how to really push my DRAM designs and get the smallest possible memory cell layout that would still yield well, provide fast access time, and long refresh cycles.
(United States Patent 6661699. Inventor:… Read More
Cadence at DesignCon 2011
I met with Rahul Deokar, Product Manager this morning to review 9 slides that tell the story of Giga-gates and GigaHz systems design at Cadence. Their updated P&R system now completes jobs 2X faster for 28nm designs.
Silicon Realization Trends and Challenges:
Silicon Realization – end to end digital… Read More
I just read the press release from TowerJazz and Tanner EDA about how an AMS designer can use schematic symbols and layout generators in Tanner EDA tools for the TowerJazz 0.18um node. This is made possible because of the growing iPDK (Interoperable Process Design Kits) movement.
In the old days each foundry would have to staff up… Read More
Last week I talked with two experts at Mentor about the challenges of getting IC designs into the 32nm/28nm node on the Common Platform (IBM, GLOBALFOUNDRIES and Samsung). Global Foundries issued a press release talking about how the four major EDA companies have worked together to qualify EDA tools for this node.
Sudhakar Jilla,… Read More
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