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After lunch on Monday I met with John Heinlin, Ph.D. – VP Marketing of Physical IP Division
Back in the day I knew the founders of Artisan (VLSI Libraries) when we worked together at Silicon Compilers (Mark Templeton, John Malecki, Scott Becker).
Q: Do you favor any EDA tools for creating your IP?
A: No, we don’t really endorse a specific… Read More
Lunch time Monday at DAC and I learned about what’s new at the IPL Alliance in 2011.
IPL Sponsors: Magma, Mentor Graphics, Springsoft, Accelicon, Ciranova, Synopsys, TSMC, TowerJazz, Jedat, Tanner EDA
Two major projects:
1) iPDKS
2) Analog Constraints… Read More
At DAC I spent time in the Magma FineSIM demo suite on Monday morning.
Greg Curtis – Product Director, Custom Design Business Unit
– Talus for Digital Design
– FineSim does: SPICE, FastSPICE, Characterization
– Flows Demoed at DAC: High Performance Core, SOC, ASIC/ASSP, AMS, Memory
– What’s New in FineSim?o… Read More
I met with Bala Vishwanath, CMO at Nimbic on Monday morning. They had just announced a $6.9M round of venture capital which is something that you rarely hear about in EDA these days, especially during a slow economic recovery.
Intro
Physware – served the package and board markets, co-design challenges (can add IC noise sources).… Read More
Introduction
Monday morning at DAC I attended the breakfast presentation from Magma, ARM and GLOBALFOUNDRIES. The 28nm node is ready for business using Magma tools and ARM libraries.
During breakfast I met Karim Arabi, Ph.D. from QualComm. He’s a senior director of engineering in San Diego and wanted to learn more about… Read More
San Diego Arrival
It’s another picture perfect day in San Diego as I arrived and checked into the Hyatt. The view from the 40th floor looked magnificent, with the Convention Center just a few minutes away in the distance:
Registration
Check in at DAC is quite automated and it took only a minute to receive my official badge with… Read More
Introduction
Cadence and ClioSoft made a webinar recently and I’ll summarize what I learned from it.
What’s New from Cadence in Virtuoso 6.1.5
Introduction
3D field solvers produce the most accurate netlists of RC values of your IC layout that can then be used in SPICE circuit simulators however most of these solvers produce a flat netlist which tends to simulate rather slowly. Thankfully several years ago the first hierarchical SPICE tools were offered by Nassda (HSIM… Read More
Reading the title you guessed it right, Mentor Graphics has three new board members today from the slate offered by billionaire activist Carl Icahn:
Introduction
Today Cadence announced at the Embedded Systems Conference something of interest to systems designers.
What’s New?
The Rapid Prototyping Platform and Virtual System Platform are what’s new, and they intend to enable and automate concurrent hardware and software development. I can remember Mentor… Read More
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Relaxation-Aware Programming in ReRAM: Evaluating and Optimizing Write Termination