Ken Kundert while at Cadence developed: Spectre, Spectre RF, Verilog-A and Verilog-AMS. About 6 years ago he and Henry Chang left Cadence and created a consulting company called The Designers Guide.
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Author: Daniel Payne
Why X-Fab uses 3D Resistance Extraction and Analysis
At DAC in 2011 I visited an EDA company called Silicon Frontline Technology because they offered some 3D field solver tools used to create the highest accuracy netlists that can then be simulated with a SPICE circuit simulator to predict timing, power and IR drop. A recent press release with X-FAB and Silicon Frontline looked interesting… Read More
Using "Apps" to Take Formal Analysis Mainstream
On my last graphics chip design at Intel the project manager asked me, “So, will this new chip work when silicon comes back?”
My response was, “Yes, however only the parts that we have been able to simulate.”
Today designers of semiconductor IP and SoC have more approaches than just simulation to ensure… Read More
Design & Verification of Platform-Based, Multi-Core SoCs
Consumer electronics is a new driver in our global semiconductor economy as we enjoy using Smart Phones, Tablets and Ultra Books. The challenge of designing and then verifying the electronic systems to meet the market windows is a daunting one. Instead of starting with a blank sheet for a new product, most electronic design companies… Read More
How Is Your IC Design Flow Glued Together?
Most IC designers I talk to really enjoy the creative process of developing a new SoC design, debugging it, then watching it go into production. They don’t really like spending time learning how to make their EDA tools work together in an optimal IC design flow where they may have a dozen tools each with dozens of options. Fortunately… Read More
Manage Your Cadence Virtuoso Libraries, PDKs & Design IPs (Webinar)
Users of Cadence Virtuoso tools for IC layout and schematics can make their design flow easier by using Design Data Management tools from ClioSoft. Keeping track of versions across schematics, layout, IP libraries and PDKs can be daunting. Come and learn more about this at a Webinar hosted by ClioSoft next Tuesday.… Read More
Analog Panel Discussion at DesignCon
DesignCon is coming up and the panel discussions look very interesting this year. The one panel session that I recommend most is called, “Analog and Mixed-Signal Design and Verification” which is moderated by Brian Bailey, one of my former Mentor Graphics buddies and fellow Oregonian.… Read More
EDA Tool Flow at MoSys Plus Design Data Management
I’ve read about MoSys over the years and had the chance this week to interview Nani Subraminian, Engineering Manager about the types of EDA tools that they use and how design data management has been deployed to keep the design process organized. My background includes both DRAM and SRAM design, so I’ve been curious… Read More
What is a Hierarchical SPICE Circuit Simulator?
Hierarchy is used in IC designs at many abstraction levels to help describe a design in a compact format:
- Mask Data
- IC Layout
- Schematic Netlists
- Gate level netlists
- RTL netlists
But the question and focus for this blog is, “What is a hierarchical SPICE Circuit Simulator?”… Read More
Low-power IC design in Switzerland
My wife and I have traveled to Switzerland on vacation and marveled at the natural beauty of the mountains, efficient train system, tasty chocolate, and wonderful foods. I only wished that our American dollar bought more in Swiss currency than it did. Recently I discovered a high-tech IC design company called Microdul that designs… Read More
Intel’s Path to Technological Leadership: Transforming Foundry Services and Embracing AI