Users of Cadence Virtuoso tools for IC layout and schematics can make their design flow easier by using Design Data Management tools from ClioSoft. Keeping track of versions across schematics, layout, IP libraries and PDKs can be daunting. Come and learn more about this at a Webinar hosted by ClioSoft next Tuesday.… Read More
Author: Daniel Payne
Analog Panel Discussion at DesignCon
DesignCon is coming up and the panel discussions look very interesting this year. The one panel session that I recommend most is called, “Analog and Mixed-Signal Design and Verification” which is moderated by Brian Bailey, one of my former Mentor Graphics buddies and fellow Oregonian.… Read More
EDA Tool Flow at MoSys Plus Design Data Management
I’ve read about MoSys over the years and had the chance this week to interview Nani Subraminian, Engineering Manager about the types of EDA tools that they use and how design data management has been deployed to keep the design process organized. My background includes both DRAM and SRAM design, so I’ve been curious… Read More
What is a Hierarchical SPICE Circuit Simulator?
Hierarchy is used in IC designs at many abstraction levels to help describe a design in a compact format:
- Mask Data
- IC Layout
- Schematic Netlists
- Gate level netlists
- RTL netlists
But the question and focus for this blog is, “What is a hierarchical SPICE Circuit Simulator?”… Read More
Low-power IC design in Switzerland
My wife and I have traveled to Switzerland on vacation and marveled at the natural beauty of the mountains, efficient train system, tasty chocolate, and wonderful foods. I only wished that our American dollar bought more in Swiss currency than it did. Recently I discovered a high-tech IC design company called Microdul that designs… Read More
Kindle Touch – My Experience
Mostly I blog about EDA software however the end objective of IC design is to produce an electronic system like the Kindle Touch, a popular e-book reader from Amazon introduced in late 2011.
Tear Down
This particular model has the following components (Source: Tech Republic):
What Dolpin Technology Uses for SPICE Circuit Simulation of IP
Mo Tamjidi founded two Semiconductor IP companies Virage Logic and Dolphin Technology. After reading a press release about how Dolphin Technology is using FineSIM SPICE from Magma I decided to contact him and learn more about why they are now using that circuit simulator in the design of their memory, standard cells, and IO cells.… Read More
EDA Vendors Providing Secure Remote Support for an IC Design Flow
In my last corporate EDA job I had customers in Korea that were evaluating a new circuit simulator and getting strange results. When I asked, “Could you send me your test case?” the reply was always, “No, we cannot let any of our IC design data leave the building because of security concerns.”… Read More
View from the top: Joe Sawicki
Joe Sawicki is the VP and General Manager at Mentor Graphics for the Design-to-Silicon Division where the Calibre product line is developed. We met today in Wilsonville, Oregon to review the challenges in IC design, processing and manufacturing.… Read More
Clock Design for SOCs with Lower Power and Better Specs
Dan Ganousis posted in our SemiWiki forums about a newer technique to lower the power consumed by GHz clocks on SOC designs and asked if I was interested to learn more, so we met today via WebEx. Dan is with a company called Cyclos Semiconductor, co-founded in 2006 by Marios Papaefthymiou, President and Alexander Ishii, VP of Engineering.… Read More
Unlocking the cloud: A new era for post-tapeout flow for semiconductor manufacturing