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Three people from Ciranova met with me at DAC this year: Eric Filseth (CEO), David Millman (Marketing) and Lindor Hendrickson (CTO). They gave me an update on how the Helix tools are being used to automate the layout of custom IC designs at 28nm and smaller nodes.… Read More
Lunch on Tuesday at DAC was sponsored by the IPL Alliance and thankfully this year they skipped the attempt at humor and focused on interoperable PDKs. Presenting companies include: Synopsys, Dongbu HiTek, TowerJazz, X-FAB and Si2. Having both OpenPDK and iPDK on the same platform does sound like a peaceful co-existence to me,… Read More
IC place and route is a big challenge so we see many EDA companies creating tools. On Tuesday at DAC I met with Dave Noble of Pulsic to get an update.
Notes
Dave Noble, VP Operations (EDA since 2003), Sperry Univac since 1974
– had been an EDA distributor for Pulsic as well
More leads qualified on Monday than all days of last year … Read More
3D has been a growing buzz word in IC design and packaging for several years now, so it’s refreshing to actually find an EDA vendor that has developed tools to help analyze something like 3D thermal and mechanical stress at DAC. … Read More
I use social media 7 days a week and while at DAC I received a message from Herve Guegan on my LinkedIn account where he basically said, “Hey, go check out Asygn at DAC, they do analog macro models.”… Read More
One year ago I met with Hany Elhak of Synopsys to get an update on what was new with HSPICE in 2011, so this year at DAC Hany met me at the Synopsys booth for a quick update.
HSPICE has something called Precision Parallel so with 16 cores your IC circuit simulations will have about 10 x speed up compared to a single core.… Read More
Tuesday morning at DAC I attended the Synopsys-hosted breakfast to hear from foundries and ARM about the challenges of designing and delivering silicon at the 32nm/28nm and 20nm nodes.
… Read More
Firas Mohamed, President and CEO (Ph.D.) of Infiniscale met with me on Monday at DAC to provide an overview of what EDA software they offer to IC designers at the transistor-level.
Vision – analog flow that Monte Carlo simulation is required, which is thousands of circuit simulations, however the higher the sigma the more… Read More
Last Monday I met with Nobuto Ono, VP Business development at Jedat (Japan EDA Technologies) while attending the DAC conference.
The company started in Tokyo and is Ex Seiko Instruments, in 2004.
Main product – layout editor for IC (SX 9000). New system is ALpha SX in 2002. 2007 listed on JASDAQ market. Like Virtuoso tools,… Read More
There are only a handful of billion transistor IC designs in existence today, so when an EDA company touts 1 trillion transistor IC layout editing then I take notice. This year at DAC I met with Katherine Hayes and Karen Mangum of Micro Magic to get an update on their IC layout tools.… Read More
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[title] => SemiWiki Main Forum ( Ask the Experts! )
[description] => Post your questions to the experts here!
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Unlocking the cloud: A new era for post-tapeout flow for semiconductor manufacturing