Fast Monte Carlo from Infiniscale at DAC

Fast Monte Carlo from Infiniscale at DAC
by Daniel Payne on 06-14-2012 at 10:56 am

Firas Mohamed, President and CEO (Ph.D.) of Infiniscale met with me on Monday at DAC to provide an overview of what EDA software they offer to IC designers at the transistor-level.


Vision – analog flow that Monte Carlo simulation is required, which is thousands of circuit simulations, however the higher the sigma the more… Read More


IC Layout Tools from Japan at DAC

IC Layout Tools from Japan at DAC
by Daniel Payne on 06-14-2012 at 10:29 am

Last Monday I met with Nobuto Ono, VP Business development at Jedat (Japan EDA Technologies) while attending the DAC conference.

The company started in Tokyo and is Ex Seiko Instruments, in 2004.

Main product – layout editor for IC (SX 9000). New system is ALpha SX in 2002. 2007 listed on JASDAQ market. Like Virtuoso tools,… Read More


One Billion Transistor IC Layout Editing

One Billion Transistor IC Layout Editing
by Daniel Payne on 06-11-2012 at 6:33 pm

There are only a handful of billion transistor IC designs in existence today, so when an EDA company touts 1 trillion transistor IC layout editing then I take notice. This year at DAC I met with Katherine Hayes and Karen Mangum of Micro Magic to get an update on their IC layout tools.… Read More


From SPICE Netlist back to Schematics at DAC

From SPICE Netlist back to Schematics at DAC
by Daniel Payne on 06-11-2012 at 5:22 pm

I first heard about SPICE Vision Pro when working at Mentor Graphics where we needed a way to visualize SPICE netlists and debug SPICE simulation results node by node on a design where we didn’t have the original schematics. Last Monday I met the engineers from Concept Engineering in their booth at DAC to get an update, Gerhard… Read More


A DAC Update from Mentor Graphics on IC Layout and Circuit Simulation Tools

A DAC Update from Mentor Graphics on IC Layout and Circuit Simulation Tools
by Daniel Payne on 06-11-2012 at 4:07 pm

Linda Fosler, Tom Daspit and Mitch from Mentor Graphics met with me last Monday at DAC to provide an update on IC layout and circuit simulation tools. My notes follow:

Overview – Pyxis for Schematic and Layout, IC Station is re-branded as Pyxis. (Pyxis schematic is still Falcon, Ample language is still used.)… Read More


Schematic, IC Layout, Clock and Timing Closure from ICScape

Schematic, IC Layout, Clock and Timing Closure from ICScape
by Daniel Payne on 06-08-2012 at 11:10 am

Before this DAC I had never even heard of ICScape, so on Monday and Wednesday I visited their booth to find out their story.

Steve Yang, Ph.D. (Co-founder and President), Ravi Ravikumar (Marketing)

ICScape was founded in 2005 in Santa Clara by Steve Yang (Circuit Design engineer for microprocessor, Synopsys) and Jason Xing (Sun… Read More


Fast Monte Carlo and Analog Fast SPICE

Fast Monte Carlo and Analog Fast SPICE
by Daniel Payne on 06-08-2012 at 10:25 am

Britto Vincent of ProPlus Design Solutions met with me at DAC on Monday morning to talk about Design For Yield (DFY) and Analog Fast SPICE.

In 2011 ProPlus announced DFY tools where the technology came from IBM, it provides fast Monte Carlo results up to 3 sigma, then added NanoSpice for faster simulation results. Similar in approach… Read More


Collaboration at 28nm, 20nm and 14nm

Collaboration at 28nm, 20nm and 14nm
by Daniel Payne on 06-06-2012 at 11:23 am


Wednesday morning I attended a panel discussion with: ARM, IBM, Cadence, GLOBALFOUNDRIES and Samsung.

The panelists all sang the same song of collaboration between EDA, IP and Foundry to enable 28nm, 20nm and even 14nm.… Read More