The rapid evolution of semiconductor design has elevated chiplets from a niche concept to a foundational strategy for next-generation computing. At the upcoming Chiplet Summit – February 17–19, 2026 Santa Clara Convention Center. Silicon Catalyst will play a central role in shaping this conversation, highlighting… Read More
Author: Daniel Nenni
Silicon Catalyst at the Chiplet Summit: Advancing the Chiplet Economy
Semidynamics Unveils 3nm AI Inference Silicon and Full-Stack Systems
Semidynamics has taken a significant step forward in the race to build next-generation AI infrastructure with the unveiling of its 3nm AI inference silicon and a vertically integrated, full-stack systems strategy. Announced in February 2026, the development marks the company’s evolution from an advanced architecture specialist… Read More
Accellera Strengthens Industry Collaboration and Standards Leadership at DVCon U.S. 2026
At DVCon U.S. 2026, Accellera Systems Initiative reinforces its central role in shaping the future of electronic design and verification through a focused program of workshops, tutorials, and community engagement. As system complexity continues to rise across AI, automotive, HPC, and communications markets, the need for… Read More
Ceva Wi-Fi 6 and Bluetooth IPs Power Renesas’ First Combo MCUs for IoT and Connected Home
The rapid expansion of IoT, smart home, and industrial automation markets is reshaping how connectivity is designed into embedded systems. Developers increasingly require highly integrated wireless solutions that deliver strong performance, ultra-low power consumption, and design flexibility, while also shortening… Read More
Chiplets Reach an Architectural Turning Point at Chiplet Summit 2026
The semiconductor industry’s transition toward chiplet-based architectures is entering a decisive new phase. What began as a promising alternative to SoC design is now confronting real-world demands around system integration, validation, and long-term scalability. At Chiplet Summit 2026, taking place February 17–19 … Read More
Gate-All-Around (GAA) Technology for Sustainable AI
The transition from FinFET to Gate-All-Around (GAA) transistor technology represents a pivotal moment in the evolution of logic devices, driven by both physical scaling limits and the rapidly growing computational demands of artificial intelligence. As semiconductor technology approaches the sub-3 nm regime, traditional… Read More
TSMC & GCU Semiconductor Training Program: Preparing Tomorrow’s Workforce
The expansion of semiconductor manufacturing in the United States, particularly with TSMC’s multi-fab campus in Phoenix, Arizona, has created a significant need for skilled technical workers. To meet this demand, TSMC has partnered with educational institutions, including Grand Canyon University (GCU), to launch… Read More
CEO Interview with Dr. Raj Gautam Dutta of Silicon Assurance
Dr. Raj Gautam Dutta is the Co-Founder and Chief Executive Officer of Silicon Assurance, where he defines the company’s strategic direction and leads its technology and product vision. He is responsible for driving the development of differentiated hardware security solutions, executing growth and partnership strategies,… Read More
Quadric’s Recent Momentum & Funding Success
Quadric®, Inc., headquartered in Burlingame, California, is accelerating its position as a leading provider of programmable AI inference processor intellectual property (IP) and development tools for on-device AI workloads. The company announced an oversubscribed $30 million Series C funding round, bringing total capital… Read More
2026 Outlook with Abhijeet Chakraborty VP, R&D Engineering at Synopsys
Tell us a little bit about yourself and your company.
My name’s Abhijeet Chakraborty and I’m Vice President of Engineering at Synopsys. I led the development of Synopsys Design Compiler-NXT, the industry’s leading synthesis product, and now oversee the company’s multi-die and 3DIC product portfolio. Throughout my career,… Read More
Silicon Insurance: Why eFPGA is Cheaper Than a Respin — and Why It Matters in the Intel 18A Era