Silicon Catalyst: Searching for the Next Great Start-up

Silicon Catalyst: Searching for the Next Great Start-up
by Daniel Nenni on 01-04-2026 at 2:00 pm

SiC 400 Jan2026Deadline Static

Silicon Catalyst has emerged as a distinctive force in the global start-up ecosystem, positioning itself not merely as an accelerator, but as a launchpad for deep-technology innovation. Focused primarily on semiconductor and hardware-based start-ups, Silicon Catalyst addresses a long-standing gap in the venture landscape:… Read More


CEO Interview with Artem Golubev of testRigor

CEO Interview with Artem Golubev of testRigor
by Daniel Nenni on 01-04-2026 at 12:00 pm

Testrigor Artem

Artem Golubev is the founder and CEO of testRigor, a company revolutionizing software test automation through AI-powered plain English testing. With a mission to eliminate the massive maintenance overhead that plagues traditional testing tools while simultaneously improving test coverage, testRigor has enabled hundreds… Read More


Revolutionizing Hardware Design Debugging with Time Travel Technology

Revolutionizing Hardware Design Debugging with Time Travel Technology
by Daniel Nenni on 01-02-2026 at 6:00 am

DVCon Europe 2025 Undo.io

In the semiconductor industry High-Level Synthesis (HLS) and SystemC have become essential tools, allowing engineers to model complex hardware designs using familiar C/C++ constructs. Yet, despite the widespread adoption of these languages, the debugging workflows in hardware development lag far behind those in software… Read More


Addressing Silent Data Corruption (SDC) with In-System Embedded Deterministic Testing

Addressing Silent Data Corruption (SDC) with In-System Embedded Deterministic Testing
by Daniel Nenni on 01-01-2026 at 10:00 am

Siemens Broadcom TSMC OIP2025 SemiWiki

Silent Data Corruption (SDC) represents a critical challenge in modern semiconductor design, particularly in high-performance computing environments like AI data centers. As highlighted in a collaborative presentation by Broadcom Inc. and Siemens EDA at the 2025 TSMC OIP event, SDC occurs when hardware defects cause erroneous… Read More


TSMC’s 6th ESG AWARD Receives over 5,800 Proposals, Igniting Sustainability Passion

TSMC’s 6th ESG AWARD Receives over 5,800 Proposals, Igniting Sustainability Passion
by Daniel Nenni on 01-01-2026 at 6:00 am

TSMC ESG Award Ceremony 2025

Taiwan Semiconductor Manufacturing Company has once again demonstrated its leadership in corporate sustainability with the successful conclusion of its 6th ESG AWARD, which attracted more than 5,800 proposals from employees across the organization. The overwhelming response reflects not only TSMC’s strong internal engagement… Read More


Tiling Support in SiFive’s AI/ML Software Stack for RISC-V Vector-Matrix Extension

Tiling Support in SiFive’s AI/ML Software Stack for RISC-V Vector-Matrix Extension
by Daniel Nenni on 12-31-2025 at 10:00 am

SiFive AI ML RISC V Summit 2025

At the 2025 RISC-V Summit North America, Min Hsu, Staff Compiler Engineer at SiFive, presented on enhancing tiling support within SiFive’s AI/ML software stack for the RISC-V Vector-Matrix Extension (VME). This extension aims to boost matrix multiplication efficiency, a cornerstone of AI workloads. SiFive’s… Read More


TSMC based 3D Chips: Socionext Achieves Two Successful Tape-Outs in Just Seven Months!

TSMC based 3D Chips: Socionext Achieves Two Successful Tape-Outs in Just Seven Months!
by Daniel Nenni on 12-31-2025 at 6:00 am

Synopsys Socionext 3d IC

Socionext’s recent run of rapid 3D-IC tape-outs is a noteworthy milestone for the industry with two successful tape-outs in just seven months for complex, multi-die designs aimed at AI and HPC workloads. That pace of iteration highlights how advanced packaging, richer EDA toolchains, and closer foundry-ecosystem collaboration… Read More


RISC-V Extensions for AI: Enhancing Performance in Machine Learning

RISC-V Extensions for AI: Enhancing Performance in Machine Learning
by Daniel Nenni on 12-30-2025 at 10:00 am

SiFive Risc V Summit 2025

In a presentation at the RISC-V Summit North America 2025, John Simpson, Senior Principal Architect at SiFive, delved into the evolving landscape of RISC-V extensions tailored for artificial intelligence and machine learning. RISC-V’s open architecture has fueled its adoption in AI/ML markets by allowing customization… Read More


CISCO ASIC Success with Synopsys SLM IPs

CISCO ASIC Success with Synopsys SLM IPs
by Daniel Nenni on 12-29-2025 at 10:00 am

cisco silicon one networking 839x473

Cisco’s relentless push toward higher-performance networking silicon has placed extraordinary demands on its ASIC design methodology. As transistor densities continue to rise across advanced SoCs, traditional design-time guardbands are no longer sufficient to ensure long-term reliability, consistent performance,

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RISC-V: Powering the Era of Intelligent General Computing

RISC-V: Powering the Era of Intelligent General Computing
by Daniel Nenni on 12-29-2025 at 8:00 am

Andes RISC V Summit 2025 Charlie Su

Charlie Su, President and CTO of Andes Technology, delivered a compelling keynote at the 2025 RISC-V Summit North America, asserting that RISC-V is primed to drive the burgeoning field of Intelligent General Computing. This emerging paradigm integrates AI and machine learning into everyday computing devices, from AI-enabled… Read More