When I first saw that Rob Knoth (Product Director at Cadence) had proposed this topic as a subject for a blog, my reaction was “well, how accurate can that be?” I’ve been around the power business for a while, so I should know better. It’s interesting that I jumped straight to that one metric for QoR; I suspect many others will do the same.… Read More
Author: Bernard Murphy
Simulating ADAS
Simulation is a broad technique spanning certainly digital logic and circuit simulation but also methods beyond these which are particularly relevant to ADAS design. In fact, much of the design of full ADAS systems begins and ends with these types of modeling. This is in part due to the need fully validate integrity and reliability… Read More
Quantifying Formal Coverage
Verification coverage is a tricky concept. Ideally a definition would measure against how many paths were tested of every possible path through the complete state graph, but that goal is unimaginably out of reach for any typical design. Instead we fall back on proxies for completeness, like hitting every line in the code. This … Read More
Webinar – Next Generation DDRM Needs, Solutions
I’m a believer in product life-cycle management (PLM) for semiconductor design. It’s not an attention-grabbing topic like faster verification or improved PPA in implementation, but now massive IP-based design is routine, IP’s are sourced from multiple suppliers each cycling though multiple revisions and now that design … Read More
Lip-Bu on Opportunity
Given a chance to talk with someone as connected as Lip-Bu Tan (President and CEO of Cadence and Chairman of the VC firm Walden International), it is tempting to ask all the usual questions about industry growth and directions in cloud, automotive, IIoT, AI and so on. I wanted to try something different. If you make a living (or plan… Read More
A Self-Contained Software-Driven Prototype
You’re building an IP, subsystem or SoC and you want to use a prototype together with a software testbench to drive extensive validation testing. I’m not talking here about the software running on the IP/SoC processor(s); the testbench should wrap around the whole DUT. This is a very common requirement. The standard approach to… Read More
The CDNLive Keynotes
I’m developing a taste for user-group meetings. In my (fairly) recently assumed role as a member of the media, I’m only allowed into the keynotes, but from what I have seen, vendors work hard to make these fresh and compelling each year through big-bang product updates and industry/academic leaders talking about their work in bleeding-edge… Read More
Webinar: Getting to Formal Coverage
Facing rapidly growing challenges in getting to respectable coverage, designers have been turning more and more to formal verification, not just to plug gaps but increasingly to take over verification of significant components of the testplan. Which is great, but at the end of the day any approach to verification must be measured… Read More
Virtual Reality
In the world of hardware emulators, virtualization is a hot and sometimes contentious topic. It’s hot because emulators are expensive, creating a lot of pressure to maximize return on that investment through multi-user sharing and 24×7 operation. And of course in this cloud-centric world it doesn’t hurt to promote cloud-like… Read More
An Ultra-Low Voltage CPU
A continuing challenge for large scale deployment of IoT devices is the need to minimize service/cost by extending battery life to decades. At these lifetimes, devices become effectively disposable (OK – a new recycling challenge) and maintenance may amount to no more than replacing a dead unit with a new unit. Getting to these… Read More
Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural Pivot