Taylor Barton is a Lead Analog/Mixed-Signal and I/O IC Design Engineer at Certus Semiconductor, where he has worked since December 2022. He has designed more than 20 silicon-proven I/O and ESD libraries and has led analog and I/O IP projects, including ADC and SerDes designs. Taylor holds B.S. and M.S. degrees in Electrical Engineering… Read More
Using AI for Root Cause Analysis of Simulation FailuresI’ve been working with AMIQ EDA for almost…Read More
Agentic AI accelerates 3D IC engineering for the AI factory eraBy Sudarshan Deo, software R&D Manager for 3D…Read More
Intel’s Tiny Bridges Could Lead to Very Big PaychecksIntel’s next big opportunity could come from something…Read More
The Compass: Finding Tomorrow in the Minds of YesterdayWhat makes a breakthrough possible? Intelligence, certainly, but…Read MoreGenerating Chip Subsystems Automatically: A New Answer to Manage Chip Design Complexity
By Defacto Staff
Today’s chips are no longer just processors, they are entire systems. A System-on-Chip (SoC) brings together CPU clusters, accelerators, memories, interconnects and dozens of peripherals, often coming from many different teams and vendors. With AI, high-performance computing and IoT driving demand for … Read More
Reimagining 3D IC Design: From Architecture to Signoff
By Keith Felton, Andras Vass-Varnai and Todd Burkholder, Siemens EDA
The semiconductor industry is undergoing a fundamental transformation. Heterogeneous integration, the practice of combining multiple chiplets and specialized components into a single advanced packaging platform, has emerged as a powerful alternative… Read More
GSA Honors Sanjay Mehrotra as Memory Takes Center Stage in Computing
The Global Semiconductor Alliance will present Micron Technology Chairman and CEO Sanjay Mehrotra with its 2026 Dr. Morris Chang Exemplary Leadership Award, recognizing a career that connects foundational flash memory innovation with the demands of modern computing. The presentation is scheduled for GSA’s Annual Awards… Read More
NIST Sets a Clearer Course for the Post-Quantum Security Transition
NIST’s report, Transition to Post-Quantum Cryptography Standards, gives government agencies and technology suppliers a clearer framework for replacing cryptography vulnerable to future quantum computers. Its significance extends beyond selecting algorithms: it connects security priorities, application requirements… Read More
CTO Interview with Ed Plowman of Imagination Technologies
Ed Plowman is Chief Technology Officer at Imagination Technologies, where he leads technology strategy, advanced architecture research and long-term innovation initiatives. He focuses on the convergence of graphics, compute and artificial intelligence, helping shape the next generation of efficient and adaptable computing… Read More
IP update from Alphacore at DAC 2026
Rusafa Shahreen, Director of Technical Marketing at Alphacore met with me at DAC 2026 to provide an update on what’s new in their IP for AMS, RF, imaging and rad-hard designs. Her background includes MSEE and MBA degrees, plus seven years at Alphacore in Arizona. The founders of the company have a rad-hard background and their early… Read More
Ceva’s next NeuPro generation opens new possibilities across AI
Ceva is broadening the possibilities for AI silicon with a new generation of its NeuPro neural processing unit portfolio, bringing a common architecture and unified software environment to applications spanning sensors, intelligent devices and cloud infrastructure.
Announced on October 28, the portfolio reflects an opportunity:… Read More
How Allegro MicroSystems Increased OEE by Several Percentage Points with yieldHUB Live
Allegro MicroSystems’ experience with yieldHUB Live shows how better use of production data can translate into measurable manufacturing gains. At its high-volume semiconductor operation in the Philippines, Allegro set out to improve overall equipment effectiveness, or OEE, by one percentage point. According to the customer… Read More
Interview with Sweta Gupta, VP of Engineering of Analog Bits
Sweta Gupta is the Vice President of Engineering at Analog Bits, where she leads development and execution of mixed-signal IP’s, managing circuit and layout teams.
Ms. Gupta has been a part of the Analog Bits team since 2004 and she has successfully managed and delivered high quality IP’s including low jitter PLL’s, low power crystal… Read More



Intel’s Tiny Bridges Could Lead to Very Big Paychecks