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There is a new breed of EDA emerging. Until recently, EDA tools were focused on building better chips, faster and with superior quality of results. Part of that process is verifying and debugging the resultant design. Thanks to ubiquitous AI workloads and multi-chip architectures, the data to be verified and debugged is exploding,… Read More
Industrial control systems (ICS) underpin the world’s most critical infrastructure: power grids, manufacturing plants, transportation networks, water systems, oil and gas facilities, and chemical processing operations. For decades, these systems relied on isolation, proprietary communication protocols, and hardware… Read More
In a field as white-hot as AI it can be difficult to separate cheerleading from reality. I am as enthusiastic as others about the potential but not the “AI everywhere in everything” message that some emphasize. So it was interesting to find a survey which looks at the deployment reality outside our narrow domain of electronic and … Read More
By Jason Liu, RFIC-GPT Inc.
Radio frequency integrated circuits (RFICs) have become increasingly critical in modern electronic systems, driven by the rapid growth of wireless communication technologies (5G/6G), the Internet of Things (IoT), and advanced radar systems. With the desire for lower power consumption, higher… Read More
In a resounding affirmation of innovation in semiconductor intellectual property (IP), Ceva, Inc. (NASDAQ: CEVA) has been honored with the prestigious “Best IP/Processor of the Year” award at the 2025 EE Awards Asia, held in Taipei on December 4. The accolade went to the Ceva-XC21, a groundbreaking vector digital… Read More
Siemens recently released a white paper on a methodology to enhance test coverage for designs with tight DPPM requirements. I confess when I first skimmed the paper, I thought this was another spin on fault simulation for ASIL A-D qualification, but I was corrected and now agree that while there are some conceptual similarities… Read More
In the rapidly evolving semiconductor industry, Design Rule Checking (DRC) remains a critical bottleneck in chip design workflows. Siemens EDA’s presentation at the 2025 TSMC Open Innovation Platform Forum, titled “AI-Driven DRC Productivity Optimization,” showcases how artificial intelligence … Read More
As AI and HPC systems scale to thousands of CPUs, GPUs, and accelerators, interconnect performance increasingly determines end-to-end efficiency. Training and inference pipelines rely on low-latency coordination, high-bandwidth memory transfers, and rapid communication across heterogeneous devices. With model sizes… Read More
Tarun Verma, Managing Partner of Silicon Catalyst, delivered a keynote at Verification Futures Austin titled “Revitalizing Semiconductor StartUps.” Drawing from his role in the world’s only accelerator focused on the global semiconductor industry, Tarun outlined the sector’s resurgence, persistent… Read More
I’ve blogged about Methodics before they were acquired by Perforce back in 2020, so I wanted to get an update on Perforce IPLM (Integrated Product Lifecycle Management) by attending their recent webinar. Hassan Ali Shah, Senior Product Manager and Rien Gahlsdor, Perforce IPLM Product Owner were the two webinar presenters. Their… Read More
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