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Trusted Convergence Governance: Preserving Admissibility Integrity Across Heterogeneous Semiconductor Systems

Trusted Convergence Governance: Preserving Admissibility Integrity Across Heterogeneous Semiconductor Systems
by Moh Kolb on 05-26-2026 at 8:00 am

Picture1 TCG (1)

As semiconductor systems evolve toward heterogeneous integration, chiplets, 2.5D and 3D packaging, distributed observability, runtime adaptation, Fleet Learning, and lifecycle convergence governance, the industry is entering a fundamentally new operational reality.

Convergence decisions are no longer driven only… Read More


Are You Ready for Spec-Driven Verification?

Are You Ready for Spec-Driven Verification?
by Bernard Murphy on 05-26-2026 at 6:00 am

Many specs with bugs

Quick recap: verification is checking that your implementation of a design matches the in-house design/test specification. In contrast, validation means checking that the implementation matches design intent as defined by a customer specification, use cases, etc. Let’s focus on verification; for simplicity I’ll use “design… Read More


TSMC Powers Up: 408,000 Batteries Get a Safety Intelligence Upgrade

TSMC Powers Up: 408,000 Batteries Get a Safety Intelligence Upgrade
by Daniel Nenni on 05-25-2026 at 10:00 am

TSMC’s Lithium Iron Battery Generation Upgrade Project

As semiconductor manufacturing becomes increasingly dependent on uninterrupted power and energy efficiency, battery reliability has emerged as a critical operational issue for advanced fabs. Taiwan Semiconductor Manufacturing Company, better known as TSMC, is addressing this challenge through an ambitious global initiative… Read More


Library Characterization gets a Boost from AI

Library Characterization gets a Boost from AI
by Daniel Payne on 05-25-2026 at 10:00 am

solido characterizer

The semiconductor industry creates increasingly complex SoC and chiplets using lots of IP and all of that IP needs to be characterized at the cell level. As we design with 3nm and 2nm nodes, the sheer volume of data required for accurate static timing analysis (STA) is greatly increasing. Modern design flows rely on characterized… Read More


Power-SOI: The Reliability Engine Behind Functional Safety ICs

Power-SOI: The Reliability Engine Behind Functional Safety ICs
by Daniel Nenni on 05-25-2026 at 6:00 am

Power SOI The Reliability Engine Behind Functional Safety ICs

Power-SOI technology is rapidly emerging as a foundational platform for next-generation functional safety integrated circuits used in autonomous vehicles, industrial automation, humanoid robotics, and other mission-critical systems. The growing convergence of high-voltage power management and low-voltage digital… Read More


CEO Interview with Vivek Raghunathan of Xscape Photonics

CEO Interview with Vivek Raghunathan of Xscape Photonics
by Daniel Nenni on 05-24-2026 at 4:00 pm

Vivek Raghunathan Xscape Photonics

Vivek Raghunathan has over 18 years of experience in silicon photonics. He was a Sr. Principal Engineer, Product Architect and Program Leader for Integrated Silicon Photonics at Broadcom driving key core technology development required to co-package optics with switches and demonstrated industry’s first 25.6T Ethernet … Read More


CEO Interview with Baratunde Cola of Carbice

CEO Interview with Baratunde Cola of Carbice
by Daniel Nenni on 05-24-2026 at 2:00 pm

Baratunde Cola Bio

Baratunde Cola is the CEO and founder of Carbice, an Atlanta, Georgia-based company that develops scalable interface solutions to protect semiconductors and electrical components from overheating in any physical environment. He received his bachelor’s and master’s degrees from Vanderbilt University and … Read More


Podcast EP347: Agentic Workflows from Caspia Technologies for Advanced Chip Security Verification with Stuart Audley

Podcast EP347: Agentic Workflows from Caspia Technologies for Advanced Chip Security Verification with Stuart Audley
by Daniel Nenni on 05-22-2026 at 10:00 am

Daniel is joined by Stuart Audley, vice president and general manager of product management at Caspia Technologies, where he focuses on agentic security workflows. He has decades of experience designing and deploying cryptographic hardware and security IP for top defense and leading semiconductor companies. He previously… Read More


ASML High-NA EUV is Not Ready for High-Volume Production

ASML High-NA EUV is Not Ready for High-Volume Production
by Daniel Nenni on 05-22-2026 at 8:00 am

ASML Elephant High NA EUV

Contrary to the popular press, ASML High-NA EUV is not ready for logic production yet—and it may never be, at least not in the form originally envisioned. If you remember how long it took conventional EUV to become production-worthy—arguably 5–10 years—this should not come as a surprise. More importantly, this is no longer just… Read More


What Winemakers and Chip Designers Have in Common

What Winemakers and Chip Designers Have in Common
by Daniel Nenni on 05-22-2026 at 6:00 am

What Winemakers and Chip Designers Have in Common

Consider this a standout presentation at the Silicon Catalyst Spring Portfolio Update Meeting held yesterday at the Computer History Museum. Mahesh Tirupattur, CEO of Analog Bits, is a modern-day, multidimensional semiconductor hero and one of my trusted few. Analog Bits is a premier member of the semiconductor ecosystem,… Read More