IMGTC Webinar SemiWIki

TSMC’s AI Design Kit: Bringing Agentic AI Into Chip Design

TSMC’s AI Design Kit: Bringing Agentic AI Into Chip Design
by Daniel Nenni on 10-01-2026 at 10:00 am

TSMC’s AI Design Kit Bringing Agentic AI Into Chip Design

TSMC is introducing an AI Design Kit, or ADK, to help artificial intelligence tools make better use of its semiconductor manufacturing knowledge. The idea is to give AI agents that run chip-design workflows a technology-specific foundation, so they can adjust designs toward performance, power and area targets with less manual… Read More


OpenAI and Synopsys Announce GPT-Synopsys: Why AI-Powered Chip Design Matters

OpenAI and Synopsys Announce GPT-Synopsys: Why AI-Powered Chip Design Matters
by Daniel Nenni on 10-01-2026 at 8:00 am

Synopsys OpenAI

Wow, OpenAI and Synopsys just announced a multiyear partnership to develop GPT-Synopsys, a specialized artificial intelligence model for semiconductor design. The agreement combines OpenAI’s frontier models with Synopsys’ electronic design automation software and engineering expertise. Its ambition is to help engineers… Read More


Why the energy sector must plan for post-quantum cyber security now

Why the energy sector must plan for post-quantum cyber security now
by Daniel Nenni on 10-01-2026 at 6:00 am

Why ASML Is Racing to Build 110 EUV Machines

In a September 2026 World Economic Forum article, Ali El Kaafarani argues that energy companies should begin preparing their systems for post-quantum cryptography now. The reason is practical: power infrastructure lasts for decades, while replacing its security can take years. Equipment purchased today may still be operating… Read More


TSMC OIP Ecosystem Forum 2026: Broadcom’s View of ASICs and Ecosystems

TSMC OIP Ecosystem Forum 2026: Broadcom’s View of ASICs and Ecosystems
by Mike Gianfagna on 09-30-2026 at 12:00 pm

TSMC OIP Ecosystem Forum 2026 Broadcom’s View of ASICs and Ecosystems

I spent a significant part of my career in the ASIC business. This segment of semiconductors has always been challenging, difficult and invigorating. There is something special about delivering a working custom chip that enables your customer to bring a world-changing product to market. It has always been a highly competitive… Read More


The Pivotal Moments That Gave Rise to Silicon Valley

The Pivotal Moments That Gave Rise to Silicon Valley
by Admin on 09-30-2026 at 10:00 am

IMAGE 1 Robert Noyce with microscope

The little-known decisions and breakthroughs—and the remarkable role of Robert Noyce—that helped shape the modern semiconductor industry

by Sunil Mehta

When people tell the story of how Silicon Valley came into being, they usually begin with a familiar sequence of events.

The transistor was invented at Bell Labs. William Shockley… Read More


SiFive and AMD Bring ROCm to RISC-V Datacenter Servers—and Why It Matters

SiFive and AMD Bring ROCm to RISC-V Datacenter Servers—and Why It Matters
by Daniel Nenni on 09-30-2026 at 8:00 am

BigSky 2U + Full Rack Render

SiFive and AMD demonstrated an AI workload that brings together two open technologies: the RISC-V processor architecture and AMD’s ROCm GPU software platform. At the AI Infra Summit on September 15, 2026, the companies showed ROCm 10.0 running on SiFive’s BigSky datacenter development server. SiFive P870-D CPUs served as the… Read More


Quantum Equivalence Checking. Innovation in Verification

Quantum Equivalence Checking. Innovation in Verification
by Bernard Murphy on 09-30-2026 at 6:00 am

Innovation New

Can quantum computing have any relevance to EDA? This month’s paper suggests it might have a role someday, in accelerating one of the most fundamental of EDA algorithms: SAT. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A)… Read More


Why Advanced Chip Packaging Is Becoming a Design Problem

Why Advanced Chip Packaging Is Becoming a Design Problem
by Daniel Nenni on 09-29-2026 at 2:00 pm

Why Advanced Chip Packaging Is Becoming a Design Problem

As chipmakers put more computing power into a single system, the challenge extends beyond making individual chips faster. They must connect multiple chips, memory stacks, power supplies, and sometimes optical components in a compact package. In the2026 TSMC OIP Forum talk “Addressing Inter-Die Complexity for 3D Multi-Die… Read More


Pollen Metrology: From a Decade-Long Bet to a Proven AI Platform for Semiconductor Manufacturing

Pollen Metrology: From a Decade-Long Bet to a Proven AI Platform for Semiconductor Manufacturing
by Lauro Rizzatti on 09-29-2026 at 12:00 pm

image001 (2)

Recently, I had the opportunity to speak with Johann Foucher, founder and CEO of Pollen Metrology, a French company whose journey offers a rare vantage point on how artificial intelligence is reshaping semiconductor manufacturing from the inside out. What makes Pollen Metrology’s story compelling isn’t just … Read More


Managing Power, Performance and Reliability in the Chiplet Era

Managing Power, Performance and Reliability in the Chiplet Era
by Kalar Rajendiran on 09-29-2026 at 10:00 am

Test Drivers proteanTecs (Chiplet Webinar)

Next-gen AI accelerators, high-performance processors, and complex computing architectures depend heavily on advanced packaging. Bringing multiple dies, chiplets, high-bandwidth memory, and advanced interconnects together into a single 2.5D or 3D package yields massive performance gains. However, this design evolution… Read More