Intel 18A-P Pushes RibbonFET and Backside Power Beyond the First GenerationIntel Foundry has a blog on LinkedIn that is…Read More
Building a Faster Path from Semiconductor Idea to Commercial SiliconSEMI and Silicon Catalyst’s new strategic partnership addresses…Read More
DAC 2026: A Discussion of Who Owns the Intelligence Behind Tomorrow’s Chips and How to Make it BetterThe industry is moving from simple documentation chatbots…Read More
How Agentic AI Turns IC Engineers into ArchitectsThere is an interesting article by Kexun ZHang…Read More
Keysight ADS Enables First-Pass Silicon at 3 THz for AttoTudeAttoTude has expanded its use of Keysight Technologies’…Read More
On Tuesday at #DAC2026 I attended the exhibitor presentation, Synopsys: How Silicon Startups are Addressing the AI Memory Gap. Vikram Bhatia from Synopsys introduced the two presentations from Wenbo Yin, SVP of IC Design at TetraMem and R. Scott Hills, VP of Business Development at ANAFLASH. Datacenters consume large amounts… Read More
AI can compress the path to tape-out. The next challenge is compressing physical realization.
Something important is beginning to happen in semiconductor development: the design cycle itself is becoming compressible.
AI-assisted engineering can accelerate architecture exploration, RTL development, verification, physical… Read More
Advanced semiconductor packaging has become essential to improving computing performance as conventional transistor scaling grows more difficult and expensive. Instead of manufacturing an entire processor as one large monolithic die, chipmakers can divide it into smaller chiplets and combine logic, memory, input/output… Read More
Sander is an Applied-physics graduate from TU Delft. Worked at a semiconductor start-up during his studies, decided building a company would be the most interesting way to shape his career. In 2010, a TU Delft professor suggested combining light and electron microscopy. Sander and co-founder Andries Effting took the patent … Read More
SEMICON West 2026 arrives at a pivotal moment for the global chip industry. Scheduled for October 13–15 at San Francisco’s Moscone Center, the event returns to the Bay Area after its 2025 edition in Phoenix. Organized by SEMI under the theme “Transform Tomorrow,” it will bring together semiconductor manufacturers, equipment… Read More
Daniel is joined by Dr. Germain Fenger, Senior Director of Product Management at Synopsys where he leads advanced mask solutions and computational lithography technologies. With a background spanning semiconductor manufacturing, lithography research, engineering, and product leadership, Germain has held roles at imec,… Read More
Timothy Regan has substantial experience in analog/ mixed signal design and its supporting EDA technologies. His career began in linear engineering at Texas Instruments.
He then worked as an applications specialist for both GE-Calma and Valid Logic Systems. After that, he spent 10 years as managing director at Design Resources… Read More
While semiconductor design intellectual property (IP) is a $9.45 billion market, it acts as the absolute architectural bottleneck for the entire global semiconductor value chain. The choices made at the IP layer today dictate the cost, power, and security of a downstream technology economy rapidly marching toward a trillion… Read More
Plessey Semiconductors manufactures monolithic MicroLED displays for near-eye augmented-reality systems, where pixel pitch, brightness, uniformity, and defect density directly determine usable yield. Its process integrates device design, epitaxy, wafer fabrication, bonding, and production in one facility. The displays… Read More
Preamble
Hardware-assisted verification (HAV) platforms, including hardware emulators and FPGA-based prototyping systems, are the two dominant methodologies for validating long workloads on complex System-on-Chip (SoC) designs before tape-out. HAV sits within a broader continuum of verification engines: simulation… Read More
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Comparing Advanced Packaging from TSMC, Intel Foundry, and Samsung Foundry