At Hot Chips 2026, OpenAI presented Jalapeño, an inference ASIC built with AI in the design loop. As reported from the session by ServeTheHome and Tom’s Hardware, OpenAI showed measured block-level wins over a human baseline — 56% on a BF16 multiply, alongside a 10% smaller matrix-unit area — within a roughly nine-month path from… Read More
What DARPA Taught Me About Building Trust into SiliconBy Sajeed Mohammad The most memorable slide I…Read More
Delivering Silicon Systems Through AI Disruption, Part 1: Writing the ScoreScore: the written music for an orchestra, with…Read More
A Migration Feasibility Study Can Turn an Uncertain Re-Design into a Measurable Engineering ProjectMoving semiconductor IP to a new process technology…Read More
Teradyne Unveils Magnum E2 for the Next Wave of AI MemoryTeradyne has announced Magnum E2, a memory test…Read More
VSORA’s Sandra Rivera on the Inference Era: Demand Is Real, But Not Everyone SurvivesSandra Rivera, Chair of VSORA, joined Bloomberg’s The…Read MoreChipAgents Expands AI Across Chip Design. The Test Is Faster, Verified Results
ChipAgents is expanding its agentic AI platform across digital and analog semiconductor engineering, aiming to connect fragmented design workflows through a common system that can plan tasks, operate engineering tools and evaluate results.
The Santa Clara company says its IC-Star engine combines organizational design … Read More
Rethinking Phase Jitter: An Algorithmic Approach to Signal Integrity
Byline: Richard Shreiner
Modern semiconductor architectures are pushing the absolute limits of physical scaling. As data rates climb into sub-picosecond regimes across high-performance computing, 5G/6G infrastructure, and advanced AI clusters, physical layer (Layer 1) signal integrity has shifted from an engineering… Read More
Siemens and NVIDIA Accelerate Lithography for Next-Generation AI Chips
Siemens has announced advances in its collaboration with NVIDIA to accelerate computational lithography, addressing a demanding step in manufacturing advanced AI semiconductors. By integrating NVIDIA’s cuLitho library with Siemens Calibre manufacturing software, the companies aim to make sophisticated photomask optimization… Read More
CEO Interview with Francisco Almada Lobo of Critical Manufacturing
Francisco Almada Lobo is CEO and co-founder of Critical Manufacturing. He began his career at a CIM research institute and joined Siemens Semiconductors in 1997. In 2004 he led the migration of an MES in a running high-volume facility, and from 2005 to 2009 he managed the Porto Development Center for Infineon and Qimonda, responsible… Read More
Maskless EUV Lithography: An Alternative to E-Beam
Semiconductor manufacturing depends on lithography: the process of transferring tiny circuit patterns onto a silicon wafer. Conventional extreme-ultraviolet (EUV) lithography projects light with a wavelength of 13.5 nanometers through a reflective optical system, using a custom photomask to define each layer. It can … Read More
CEO Interview with Dr. Raj Talluri of Kulicke & Soffa
Dr. Talluri joined K&S in August 2026 as a member of the Board and assumed the role of President and Chief Executive Officer of K&S in September 2026. Prior to joining K&S, Dr. Talluri served as President, Chief Executive Officer and a member of the Board of Directors at Enovix Corporation, a Nasdaq-listed advanced … Read More
Podcast EP374: How proteanTecs Tames Multi-Die Packaging Challenges with Nir Server
Daniel is joined by Nir Sever, an industry veteran with over 30 years of technological and managerial experience in advanced VLSI engineering. Before joining proteanTecs, Nir served for 10 years as the COO of Tehuti Networks, a pioneer in the area of high-speed networking Semiconductors. Prior to that, he served for 9 years as … Read More
TSMC’s AI Expansion Signals a Broader Shift in Computing
TSMC is describing an artificial intelligence boom that reaches beyond accelerator chips into the wider computing infrastructure needed to support increasingly capable AI systems. On the recent investor call, Chairman and CEO Dr. C.C. Wei presents strong demand, persistent supply constraints and an ambitious expansion … Read More
Terafab’s Single Roof: Why Packaging, Not Lithography, Decides High Volume
By Shaurya Seth
Terafab is one of the most ambitious projects of the decade: $16.8 billion for phase one and up to $119 billion across four phases. A research fab in Austin iterates on process recipes, transistor designs, and packaging variants at a few thousand wafers per month. A volume fab in Grimes County targets 100,000 wafer… Read More


Rethinking Phase Jitter: An Algorithmic Approach to Signal Integrity