The face of EDA is changing. For forty years, this industry has focused on optimizing algorithms for design, verification and implementation of chips. That work has delivered some ground-breaking innovations. Logic synthesis is a good example. There are so many more. Thanks to the innovations commonly referred to as Frontier… Read More
Keysight Design Engineering Software at DAC 2026: Going Deep on Chiplets, RF and AI-Driven DesignKeysight Technologies returns to 2026 DAC, The Chips…Read More
Tuple Technologies Develops AI-powered Infrastructure at 2026 DACTuple Technologies develops AI-powered infrastructure and operations platforms…Read More
TSMC CoWoS versus Intel EMIB Semiconductor PackagingThere has been talk at the latest conferences…Read MoreMust-See DAC Panel – Build vs Buy: Who Owns the Intelligence Behind Tomorrow’s Chips?
This year, DAC will be buzzing about AI from every direction. The debate of build vs. buy will also be a popular topic. And the debate of who owns the intellectual property embodied in chip designs and how to control it will also get a significant amount of airtime. These are all interesting and compelling discussion points. It turns… Read More
BRONCO AI: WIN THE RACE TO TAPE-OUT | BOOTH 935
Bronco AI builds AI agents for chip design and verification. Our goal is to get teams from spec to RTL-freeze as fast as possible by surfacing the nastiest bugs sooner and fixing them faster.
Our agents work the way strong engineers do: they read the spec, form hypotheses, run experiments, and chase a problem until it is root-caused,… Read More
The Other Side of Bug Localization
Automated debugging – starting from an unexpected behavior to find a bug root-cause or a small set of possible root-causes – is a hot topic now that agentic systems are playing a bigger role in automation. Unsurprising since debug remains the most time and resource-consuming aspect of verification, in turn the most time/resource-consuming… Read More
Agentrys Weighs in on LLM Benchmarking for Chip Design at DAC 2026
Si2 is conducting quite a few sessions at DAC this year covering everything from power model standards to agentic AI. There is one session that is a bit different, focusing on LLM benchmarking. Since AI is popping up everywhere, the ability to accurately assess and measure the quality of new models becomes more important. That’s… Read More
CEO Interview with Dan Fritchman of Generation Alpha Transistor
Dan Fritchman is an electrical engineer and semiconductor-software entrepreneur. He is the founder and CEO of Generation Alpha Transistor, a San Francisco startup developing AI-based tools for integrated-circuit design.
He earned a Ph.D. in Electrical Engineering and Computer Sciences from UC Berkeley in 2023. His dissertation,… Read More
RISC-V Advantage in Accelerator Control Highlights System Verification Challenges
When considering best-fit applications for RISC-V, the appeal of extending the instruction set and competitive pricing for storage and edge applications has been pretty clear. But I have always struggled to understand the appeal in head-on competition with Arm in premium applications such as servers and infrastructure systems.… Read More
Silicon Creations at DAC 2026: Solutions for clocking, SerDes, and sensing in 2nm (and beyond)
Silicon Creations provides world-class IP for precision and general-purpose timing (PLLs and oscillators), high-performance multi-protocol, latency optimized and protocol-specific SerDes, high-speed I/Os, and accurate VT sensors. Applications include high-performance computing for AI, smart phones, wearables,… Read More
The Architecture of Success: Why a Unified Semiconductor IP Strategy Is the Foundation of Modern SoC Design
As architects push toward advanced nodes and increasingly demanding workloads, modern silicon design has entered an era of unprecedented complexity. A single design respin can cost millions of dollars and delay market entry. Against this backdrop, designs must be balanced for performance, bandwidth, power efficiency, security… Read More
Whalechip Uses ChipAgents to Compress Root Cause Analysis into Minutes
AI-powered platform identified four critical SoC bugs and helped prevent up to two weeks of potential development delays
Semiconductor verification is increasingly constrained not by simulation capacity, but by the engineering effort required to understand why a simulation failed. Modern ASIC and system-on-chip designs… Read More




TSMC CoWoS versus Intel EMIB Semiconductor Packaging