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How Customized Foundation IP Is Redefining Power Efficiency and Semiconductor ROI

How Customized Foundation IP Is Redefining Power Efficiency and Semiconductor ROI
by Kalar Rajendiran on 02-26-2026 at 10:00 am

chip design for blog

As computing expands from data centers to edge devices, semiconductor designers face increasing pressure to optimize both performance and energy efficiency. Advanced process nodes continue to provide transistor-level improvements, but scaling alone cannot meet the demands of hyperscale AI infrastructure or ultra-low-power… Read More


Akeana Partners with Axiomise for Formal Verification of Its Super-Scalar RISC-V Cores

Akeana Partners with Axiomise for Formal Verification of Its Super-Scalar RISC-V Cores
by Daniel Nenni on 02-26-2026 at 8:00 am

Akeana Partners with Axiomise

Akeana Inc. announced a key milestone in the development of its advanced RISC-V technology: a successful partnership with Axiomise Limited to formally verify its super-scalar test chip, Alpine. The collaboration highlights the growing importance of formal verification in ensuring correctness, performance, and efficiency

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An AI-Native Architecture That Eliminates GPU Inefficiencies

An AI-Native Architecture That Eliminates GPU Inefficiencies
by Lauro Rizzatti on 02-26-2026 at 6:00 am

VSORA SemiWiki 2026

A recent analysis highlighted by MIT Technology Review puts the energy cost of generative AI into stark perspective. Generating a simple text response from Llama 3.1-405B—a model with 405 billion parameters, the adjustable “knobs” that enable prediction—requires on average 3,353 joules, nearly 1 watt-hour (Wh). Once cooling… Read More


Caspia Technologies Unveils A Breakthrough in RTL Security Verification Paving the Way for Agentic Silicon Security

Caspia Technologies Unveils A Breakthrough in RTL Security Verification Paving the Way for Agentic Silicon Security
by Daniel Nenni on 02-25-2026 at 10:00 am

Caspia CODAX

In a significant advancement for the semiconductor industry, Caspia Technologies announced the broad availability of CODAx V2026.1, its flagship RTL security analyzer. The new release strengthens early-stage hardware security verification and positions the company to deliver fully agentic workflows that automate vulnerability… Read More


Designing the Future: AI-Driven Multi-Die Innovation in the Era of Agentic Engineering

Designing the Future: AI-Driven Multi-Die Innovation in the Era of Agentic Engineering
by Daniel Nenni on 02-25-2026 at 8:00 am

1 abhijeet chakraborty chiplet summit keynote 2026

At the 2026 Chiplet Summit, Synopsys presented a bold vision for the future of semiconductor innovation: AI-driven multi-die design powered by agentic intelligence. As the semiconductor industry shifts rapidly toward chiplet-based architectures and 3D stacking, the complexity of design, verification, and system integration… Read More


An Agentic Formal Verifier. Innovation in Verification

An Agentic Formal Verifier. Innovation in Verification
by Bernard Murphy on 02-25-2026 at 6:00 am

Innovation New

In a break from our academic-centric picks, here we look at an agentic verification flow developed within a semiconductor company. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A) and I continue our series on research ideas.… Read More


Reimagining Compute in the Age of Dispersed Intelligence

Reimagining Compute in the Age of Dispersed Intelligence
by Jonah McLeod on 02-24-2026 at 10:00 am

Yuning(lr) copy

At the 2025 RISC-V Summit, amid debates over cloud scaling and AI cost, DeepComputing CEO Yuning Liang offered a radical view: the future of intelligence isn’t in the cloud at all — it’s already in your pocket. His lunchtime conversation began with iPhones and ended with the death of the operating system. In between, he sketched … Read More


Siemens to Deliver Industry-Leading PCB Test Engineering Solutions

Siemens to Deliver Industry-Leading PCB Test Engineering Solutions
by Daniel Nenni on 02-24-2026 at 8:00 am

Siemens Acquires ASTER Technologies to Deliver Industry Leading PCB Test Engineering Solutions

Siemens has strengthened its position in EDA and manufacturing by acquiring ASTER Technologies, a specialist in test and reliability solutions for printed circuit boards. The acquisition represents a strategic step in Siemens’ broader vision to deliver a fully integrated, end-to-end digital thread for electronics design,… Read More


Agentic EDA Panel Review Suggests Promise and Near-Term Guidance

Agentic EDA Panel Review Suggests Promise and Near-Term Guidance
by Bernard Murphy on 02-24-2026 at 6:00 am

Massive AI datacenter

NetApp recently hosted a webinar on Agentic AI as the future for EDA and implications for infrastructure. Good list of panelists including Mahesh Turaga (VP Cadence Cloud) with an intro preso on infrastructure and agentic AI at Cadence, then our own Dan Nenni (Mr. SemiWiki) moderating, Khaled Heloue (Fellow AMD, CAD CAD/Methodology/AI),… Read More


Hardware is the Center of the Universe (Again)

Hardware is the Center of the Universe (Again)
by Lauro Rizzatti on 02-23-2026 at 10:00 am

Hardware is the Center of the Universe (Again) Figure 1

The 40-Year Evolution of Hardware-Assisted Verification — From In-Circuit Emulation to AI-Era Full-Stack Validation

For more than a decade, Hardware-Assisted Verification platforms have been the centerpiece of the verification toolbox. Today, no serious semiconductor program reaches tapeout without emulation or FPGA-prototyping… Read More