AI was a hot topic at DAC this year. If you attended the event, you’ve already heard about many new tools and systems that aim to improve time to market and quality for advanced semiconductors and systems. I had the pleasure of chairing an Accellera sponsored luncheon panel on Tuesday at DAC that took a different view of AI.
As AI and machine learning are increasingly integrated into EDA workflows, new challenges are emerging around interoperability, data exchange, trust, and reproducibility. These are the areas that the panel addressed. We also used a unique survey tool that allowed everyone in the audience to voice their opinions. Here are some of the comments and insights from the DAC 2026 Accellera luncheon panel on Embracing AI for Advanced Design and Verification.
The Panel
I was fortunate to have an excellent panel. The group is shown in the photo above. Going left to right:
- Dr. Jiang Hu, IEEE Fellow, Eric Rubin Professor, Texas A&M University. Jian brought a broad and forward-looking perspective to the panel on topics such as optimization and machine learning techniques for chip design and verification, approximate computing and hardware security. If you look carefully at the photo, you will see Jiang is wearing the coveted shirt that indicates he is part of the group that makes DAC happen. Jiang served as a general chair for ACM Symposiums on physical design and MLCAD, and he was named an IEEE fellow in 2016. Currently, he is the Editor-in-Chief of the ACM Transactions on Design Automation of Electronic Systems.
- David Zhi LuoZhang, Co-founder and CEO of Bronco AI. David represents one of the new breed of AI companies that aims to change the way chip design is done. Bronco’s focus is AI-Native EDA systems for chip design and design verification, from spec to sign-off. Before starting Bronco AI, David built AI fighter jets at Shield AI, training AI pilots that could out-maneuver and win against human pilots with a focus on the AI system’s reliability and transparency.
- Simon Davidmann, AI+EDA Researcher. Simon brought a broad view of the design problem. He is a renowned EDA industry pioneer and serial technology entrepreneur with over 40 years of experience in simulation and verification. His career has been instrumental in shaping the foundational languages and methodologies used in modern chip design, particularly those now critical for AI/ML hardware. He served as a Visiting Professor at Queen Mary University of London for 10 years, focusing on digital music and entrepreneurship.
With this panel of industry luminaries, we dug into some questions.
Panel Sentiments
The first question I posed was: AI is changing a broad class of design and verification tasks across the entire flow. This impacts many tools across many vendors and ecosystem players. In this scenario, clearly defined interoperability is key to success and standards are the best way to implement it. What is the most important standard in development today for AI, and are you happy with the progress being made?
A few key topics bubbled to the top. One was data formats to facilitate interchange of information between tools. Another was the importance of a Python-based API to integrate AI-fueled flows. Tcl has been the standard for EDA flows, but Python is in wide use for AI/ML. And a third was the need for a standard format for the knowledge base that stores results and strategies. This intelligence must be easily shared among tools.
Another topic was the need for better characterization and integration of EDA workflows. This will be needed to allow deeper integration of AI into the overall operation of a company. The discussion also went broader to include things like government regulation and topics such as data transparency, data privacy, algorithmic bias, and benchmarking/certification processes. These are all areas where standards work is underway.
Overall, expectations are that many current languages and standards will be rendered obsolete as the new and unique requirements of AI take hold.
The second question was: In the next 12 months, what part of the design and verification flow will AI impact the most? How will chip design change as a result?
RTL design and verification are clearly the first areas of high impact for new AI approaches. But physical implementation isn’t far behind. Some of the results reported by NVIDIA at the show were cited as proof of the progress being made in these areas.
Stepping back a bit, it was observed that interaction with AI is evolving at a rapid pace. What used to be “debug this problem” is now moving toward “look at this design and tell me what’s wrong with it”. These are attributes of goal-driven, long horizon, autonomous workflows. As these new workflows mature and become more ingrained in the design process, we may see chip design change in some dramatic ways. Said another way, doing the same things faster may be eclipsed by an approach where different, higher impact things are accomplished faster.
My last question for this segment looked at the darker side of AI in design and verification. These tasks represent the crown jewels of innovation and differentiation. What are the risks associated with deploying AI here, and how can those risks be minimized?
Trust was a predictably large part of the conversation. Methods and standards to establish that trust are important. Parts of this topic include ensuring sensitive IP is protected and cannot “leak”, and another is how to build trust that the AI agents you are using are doing the right thing. This last item requires humans in the loop, but it also requires AI to deliver complete and thorough information regarding what it did, so those humans have a focus point for judgement.
We all agreed that verification was the largest bottleneck in chip design. In the new world of autonomous chip design, verification is still the main challenge. But the task changes to verification of the process that made the chip vs. verification of the chip itself.
Audience Survey
We then moved to the audience survey part of our event. Using a real-time feedback system on everyone’s cell phone, we posed a few multiple-choice questions and watched as everyone weighed in.
We had a full house for the panel, so I was hopeful the size of the group would yield useful results. More on that in a bit.
The first question allowed only one choice for the response. Are you currently using AI in your design and verification projects?
For each question, I will show you the results as displayed on the large screen.
Most of the audience seemed to be embracing AI in the design flow at some level.
For the next few questions, the choice of up to three responses was allowed. Where would AI be most beneficial to your current project today?
The first response was in line with what we had discussed. The second most popular response, Documentation/Spec Generation, was an interesting addition.
The third question was: Where do you believe standards from Accellera are most needed to support AI in EDA?
The first response aligned well with the panel’s discussion. The strong additional responses verified broad agreement on the need for many enabling standards.
The fourth question was: What is your biggest concern about adopting AI in semiconductor workflows?
Clearly, trust comes first.
And the fifth and last question allowed only one response: What type of AI support is most important for you?
The good news here is we’ve moved from basic assistance to semi-autonomous workflows. There was a lot of interesting discussion with the panel as the audience answers took shape. In the interest of keeping this (somewhat) short I won’t dive into that part. I do want to mention one very interesting comment that came at the end of this section.
Harry Foster, Chief Scientist Verification at Siemens EDA was in the audience, and he told us that he was just completing the 2026 Wilson Research Report. This report is widely cited in the industry, and its sample size is vastly larger than our lunch group at DAC. What was surprising in a good way was that Harry said the parts of his survey that dealt with AI in the design flow tracked the general trends we found in our panel event.
Final Question
My last question to the panel was: How will the design and verification of semiconductor devices be different in five years because of AI?
There was discussion of the tradeoff between doing a design faster vs. taking the same amount of time to deliver a much better version of the design. The impact of having a broader perspective on the design and the ability to tape it out faster was also discussed. Simon had the last word here, and I think his response was the most realistic. He described the exponential improvement curve we’ve been on for a long time now. What used to take months now takes minutes. In an environment like that, predicting the changes we will see in five years is simply not possible.
As I thought about it, I realized five future years are like 20 current years, given the accelerating pace of innovation. So, Simon’s final words rang true for me. I need a better panel conclusion question.
To Learn More
Accellera is working on a vast array of topics to help move our industry forward. The panel began with an informative overview from Lu Dai, Accellera Chair. This post is already too long, so I won’t repeat his comments here. If you want to learn more about the great work being done at Accellera, this is a good place to start.
And that’s what happened at the DAC 2026 Accellera luncheon panel on Embracing AI for Advanced Design and Verification.
Also Read:
Accellera Updates at DVCon 2026
Accellera Strengthens Industry Collaboration and Standards Leadership at DVCon U.S. 2026
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