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SPI Inspires a New Generation of SOC Designs

SPI Inspires a New Generation of SOC Designs
by Tom Simon on 02-15-2018 at 12:00 pm

When I started dabbling in hardware again for fun using Arduinos about five years ago, it had been a long time since I had played with microprocessor chips. The epiphany for me was seeing how easy it was to load programs onto the onboard flash on something like an Atmel AVR using the SPI interface. My previous experience decades early brought up visions of bulky parallel interfaces with complicated programming units. The USB to SPI interface was essentially one chip and a few discretes. I also played with the SPI, in its most basic form, to drive programmable LED strips. Of course, SPI has mushroomed into a popular and essential interface for many embedded and SOC based systems. I was therefore pleased to see a webinar by Silvaco that delved into SPI and its many applications today.

The webinar, cleverly named SPI vs SPI, aired recently, but is now available for viewing on the Silvaco website. For those who are missing the SPI vs SPI reference, look up Mad Magazine, another one of my childhood favorites. With Silvaco’s acquisition of IP Extreme, they have become a significant player in the IP market. The webinar was hosted by Jim Bruister, Director of Digital Systems at Silvaco. MCU programming aside, the main application for SPI is the broader field of flash memory enabled devices. These cover a large range of consumer, IoT and networked products.


External flash memory for these products is enabled by SPI and helps solve many system and SOC level problems. Nonvolatile memory is needed for storing boot images and startup. However, onboard flash can be a problem due to cost or process compatibility. Rather than have embedded flash availability dictate SOC process selection, off-chip flash decouples the choices.

Even though SPI started out as a single data line serial interface, it has increased in speed and added bus width to boost performance. It has evolved from 1 bit at 1MHz to up to 8 bits running at 200MHz. At the same time is has preserved its simple and effective clocking and bus arbitration scheme. Jim pointed out during the presentation that with the newer SPI IP, a serial SPI bus running at 80MHz can exceed the throughput of a 32 bit parallel bus with a 90ns access time. At the same time SPI requires one 8 PDFN part, and the parallel interface would need 2 of the 64 BGA parts and the 64 traces that go with them.


Silvaco has IP for Quad and Octal SPI controllers. These interface with a large number of commercial flash memories and integrate inside SOC’s with ARM’s AMBA AHB and AXI interfaces. The story really gets interesting when Execute in Place (XIP) comes into the picture. XIP allows for external flash to be used as if it were system memory. This vastly expands system architecture choices. With XIP there is DMA support, which can be used to load encrypted images from external flash devices for increased security.


Jim’s talk articulates several scenarios where XIP, DMA and other advanced features of their high-performance SPI IP are used. Jim also discusses the software support available for system operation and debug. Silvaco offers a QSPI Boot Loader that copies external boot code stored on flash memory into internal SRAM and then re-boots. They also have a QSPI flash loader that is useful copying data to flash memory chips.
SPI is one of those long running success stories, from its origins in the 1990’s it has evolved and become newly important to an entire class of SOC based designs. With quad and octal designs running at high speeds, it has kept pace with data and throughput requirements. SPI enables data transfers with vastly fewer traces and with smaller and less expensive packages. SPI IP is an ideal example of how system level IP can help improve customers’ time to market, lower expenses and increase predictability. The webinar which is online now describes in more detail how a variety of solutions can be designed to incorporate flash memory by using Silvaco SPI IP.

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