Low Frequency Noise Challenges IC Designs

AMS and RF IC designers have known for years that their circuits are sensitive to noise, because if you amplify noise on an input source to an amplifier circuit then your chip can start to produce wrong answers. Even digital SoC designers need to start taking notice because every SoC is filled with SRAM IP blocks, and at each shrinking process node the contribution of Random Telegraph Noise (RTN) increases and then cuts into the Vdd design margins. So one of the first steps to mitigating the effects of noise is to have an accurate method for noise characterization of all silicon devices (MOS, resistors, capacitors, etc.).

Here are a couple of charts to help us visualize the effects of noise on circuits:

Increased statistical variation of 1/f (flicker) noise, AMS and RF designs.
Source: C.Y. Chen, UCB, 2010

Increased RTN impacts Vdd margins on SRAM designs
Source: K.V. Aadithya, DATE, 2011

Low Frequency (LF) noise variation goes up as node geometries shrink, and Random Telegraph Signal (RTS) noise starts to increase. One of the sources for RTS noise is oxide traps, however if the fabs can improve the oxidation process it will improve the crystallization quality and reduce the surface roughness.

LF noise variation for a 28nm nMOS device

LF noise impacts many circuits: A/D converters, OpAmps, RF components (diffusion and poly resistors). Fabs realize that by producing silicon with lower noise characteristics and less variation, then the performance of semiconductor IP blocks improves. Accurate noise characterizations and accurate modeling are necessary steps for fabs as they create their PDKs used by circuit designers. In recent years, designers from top fabless design houses started using it as a key metric to evaluate foundry processes and improve design through a better understanding of process and devices because of the pressure of shrinking design margins. The amount of noise characterization data is exploding, and the need for different types of devices at different conditions is increasing dramatically.

So how does a process engineer go about measuring noise when the signals are quite small, the testing environment itself can inject noise, the measurement hardware adds noise and it can take a long time for measurements to stabilize? An ideal on-wafer measurement system for noise would be accurate, efficient, work for all silicon devices, have a wide bandwidth, provide high resolution, cover a wide voltage range, be sensitive to low currents, and be easy to setup and use. One vendor has been offering such a measurement system called the 9812B from ProPlus Solutions used around the globe by foundries, IDMs and research institutes for the past decade or so.

Some three years ago ProPlus upped the ante by introducing a successor to the 9812B called the 9812D for noise analysis that has been adopted by all of the leading foundries, many IDMs and top fabless companies, here’s what the equipment looks like:

9812D Noise Analyzer from ProPlus

Why upgrade from the B to D model? Plenty: highest accuracy, built-in Dynamic Signal Analyzer (DSA), support for high voltage and very low current, about 3-10X efficiency improvement, 10MHz bandwidth for on-wafer measurements. Here’s how you can setup a 9812D with an IV meter and prober station to make on-wafer noise measurements:

A 9812D with integrated DSA boosts the measurement efficiency and data quality, plus it eliminates the need for an external bench DSA or added spectrum analyzer to reduce your total system costs by about 50%. As a comparison, if you used a stand-alone DSA and did 20 time measurement averages, it would take about 65 seconds. While using the 9812D and integrated DSA, you can get over 100 time measurement averages in just 25 seconds.

All of the measurements from the 9812D can be controlled by software called NoiseProPlus running on a PC.

What’s Next?
Just to whet your appetite I’ll share a little bit about what comes after the 9812D for noise analysis and it’s called the 9812DX, with new specifications like:

• Increased voltage and current range to 200V and 200 mA
• Noise measurements at extreme low bias current, down to 0.1nA and below
• Lots of device types: MOSFET (FinFET, FD-SOI), BJT, LDMOS, TFT, JFET, diodes (photo, laser, Zener), resistors (10-10M Ohm, and voltage controlled)
• Wide range of impedance matching for both high-impedance and low-impedance devices
• Ready for advanced process nodes: 16nm, 14nm, 10nm, 7nm
• 3-5X faster across the whole current range with typical speed of 10 sec/bias
• Under 0.7nV/sqrt(Hz) floor noise voltage, and 5e-27A^2/Hz floor noise current

The success of the 9812B and 9812D has proven the accuracy and reliability of the system architecture for almost 20 years. The main motivation of 9812DX is to build a system with the highest accuracy that can do it all, including high voltage, high current, extreme low current and all types of device types and bias conditions. And more important, can provide the highest speed for all conditions so that the user can quickly take noise data to meet advanced process development and circuit design needs. Like its predecessors 9812B and 9812D, the new all-in-one system is targeting to setting new standards for all specifications of on-wafer noise characterization.

Like what you see in the 9812DX, then expect shipments in Q4’16. Register for the webinar to learn more about this new system.

Summary
Noise characterization and analysis is a critical step for foundries to perform so that they can create the most accurate PDKs for customers doing circuit design work in AMS, RF and SRAM semiconductor IP. An emerging trend comes from designers who are doing advanced designs and using noise characterization to evaluate a process and understand device characteristics at the fabless side.

The engineers at ProPlus have been at this noise analysis business for over a decade and look to have a strong roadmap for continued support of noise analysis for the latest processes in development today.