Validating Hard IP & Std Cell Libraries at DAC

The building blocks for every SoC are standard cell libraries that are assembled, designed and verified together. But how do we really know if all the data formats used during design are correct and consistent? To answer that question I spoke with Johan Peetersof Fractal Technologiesat DAC.

Johan Peeters, Rene Donkers

Q: Who would use your EDA tools?

Chip engineers who design libraries, Characterization Groups and anyone that create macro IP blocks.

Q: What problems do your EDA tools help with?

Our tools help to verify the consistency of formats for std cell libraries or macro IP blocks. The tool checks the quality of the various data formats used in these designs.

We support all standard formats used in the industry and for custom formats we provide an API functionality to create parsers for these custom formats.

Q: Can you tell me which customers are using these tools?

Customers – Mostly under NDA, so no names are mentioned.

Q: How long have you been in business?

We started our company Q1, 2010

Q: How is your company funded?

We are privately funded.

Q: What should I expect to see in the next year?

Recently we have added Spectre and Spef as new supported formats. New formats and checks will be added and there is a constant need for speed improvements.

We will continue to work closely with customers and add their most-needed features.

Q: Are you part of any 3rd party programs?

Yes, for Third party – Si2 (Open Access), Synopsys.

Q: What is the competition to your validation tools?

Our Competition are internal scripts developed by our potential customers because historically no independent tool provider developed a tool to check the quality of design formats.

Fractal is an independent tool provider. We do not care what data format from what provider is used, we simply check the quality of the formats used in your designs.

Q: When did you get into EDA?

My career started in 1986, and I’ve been to maybe 20 DAC shows.

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