eMMC Mobile Memory

eMMC is the standard for mobile memory used in smartphones and tablets. The latest standard, released just this year, is eMMC 5.0. The previous standard, 4.51, was only released last year so things are moving quickly.

Arasan have a webinar next week to bring you up to speed on eMMC 5.0 in general and, of course, their own IP offering in the space in particular. It is at 6pm on Tuesday evening December 3rd (convenient both for the west coast of the US and also for Asia).

The new standard, as you would expect, supports higher bandwidth at 3.2Gbps. See the table below for other changes between the two standards.

[TABLE] class=”cms_table_grid” style=”width: 500px”
|- class=”cms_table_grid_tr”
| class=”cms_table_grid_td” |
| class=”cms_table_grid_td” | eMMC 4.51

| class=”cms_table_grid_td” | eMMC 5.0

|- class=”cms_table_grid_tr”
| class=”cms_table_grid_td” | Throughput

| class=”cms_table_grid_td” | 1.6Gbps
| class=”cms_table_grid_td” | 3.2Gbps
|- class=”cms_table_grid_tr”
| class=”cms_table_grid_td” | Pins

| class=”cms_table_grid_td” | 10 pins
| class=”cms_table_grid_td” | 11 pins
|- class=”cms_table_grid_tr”
| class=”cms_table_grid_td” | I/O voltages

| class=”cms_table_grid_td” | 1.2V/1.8V/3.3V
| class=”cms_table_grid_td” | 1.2V/1.8V
|- class=”cms_table_grid_tr”
| class=”cms_table_grid_td” | Data bus width

| class=”cms_table_grid_td” | 4 or 8 bit
| class=”cms_table_grid_td” | 8 bit
|- class=”cms_table_grid_tr”
| class=”cms_table_grid_td” | Clock

| class=”cms_table_grid_td” | 200 MHz (SDR)
| class=”cms_table_grid_td” | 200 MHz (DDR)
|-

One other big difference is that eMMC 5.0 has a hard IP analog PHY, including DLLs for Tx, Rx and Rx STRB. This standard is expected to be widely used. IHS iSuppli predict shipments of almost a billion units by 2015.

So just what is eMMC? It is a full managed flash memory solution, including features such as bad block management, error detection and correction and NAND flash wear leveling. The previous version of the standard is already widely used in most smartphones and tablets. It is a complete memory subsystem including both hardware and software.

One challenge with new standards is that there are no devices available using the standard because it is so new. So a hardware validation platform is required that functions as an eMMC 5.0 host to enable early validation and software development. This consists of a standard PC motherboard along with an eMMC 5.0 host IP board build using FPGA technology.

Arasan is the only company with eMMC 5.0 IP shipping. It is available now in TSMC 28nm, both HPM and LP (high performance and low power variants of the process) and is silicon proven. The IP is delivered as:

• NV-DDR2 PHY in GDSII
• Controller IP core in RTL along with timing and behavioral models
• Software stack in C++ for Linux
• Available hardware validation platform

Once again the Arasan webinar is next Tuesday, December 3rd, at 6pm Pacific. Registration is here.

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