Full Name: Fin Field-Effect Transistor
Also Known As: 3D Tri-Gate Transistor, Multi-Gate FET
Category: Advanced CMOS Transistor Technology
Introduced by Industry: ~2011 (Intel 22nm)
Invented by: Chenming Hu and colleagues at UC Berkeley (1999)
Replaced: Planar CMOS Transistors
Successor Technology: Gate-All-Around … Read More
Full Name: Walden C. Rhines
Date of Birth: November 1946
Nationality: American
Fields: Semiconductors, Electronic Design Automation (EDA), Materials Science, Leadership
Notable Titles:
Former Chairman & CEO, Mentor Graphics
Former EVP, Texas Instruments
Node Name: Samsung 2nm
Internal Name: SF2 (Samsung Foundry 2nm)
Technology Type: Gate-All-Around (GAA) – MBCFET™
Developer: Samsung Electronics (Samsung Foundry Division)
Announced: May 2022
Targeted Risk Production: 2025
Targeted High Volume Manufacturing (HVM): 2026
Successor to: Samsung 3GAP (3nm Gate-All-Around… Read More
Official Names:
Samsung 3GAE (3nm Gate-All-Around Early)
Samsung 3GAP (3nm Gate-All-Around Plus)
Technology Type: Gate-All-Around (GAA) FET – MBCFET™
Developer: Samsung Electronics (Samsung Foundry)
Announced: 2021 (3GAE), 2022 (3GAP)
Mass Production Start:
3GAE: June 2022
3GAP: Expected 2024–2025
Predecessor: 4nm
Full Name: High Numerical Aperture Extreme Ultraviolet Lithography
Abbreviation: High-NA EUV
Technology Type: Advanced semiconductor photolithography
Developed By: ASML, Zeiss, in collaboration with Intel, TSMC, imec, and others
First Deployment Target: Intel (expected ~2025–2026)
Main Use: Sub-2nm logic node patterning… Read More
Name: SystemVerilog
Type: Hardware Description and Verification Language (HDVL)
Developed by: Originally by Accellera; standardized by IEEE
IEEE Standard: IEEE 1800™
First Released: 2002 (merged into IEEE 1800-2005)
Latest Version: IEEE 1800-2017 (as of 2025)
Predecessor: Verilog
Successor/Alternative: SystemC (C++… Read More
Node Name: Intel 18A
Process Class: ~1.8nm (Angstrom-class node)
Announced: July 2021
First Production Tapeout: Late 2024 (risk production)
High-Volume Manufacturing: Expected in 2025
Transistor Type: RibbonFET (Gate-All-Around)
Power Delivery: PowerVia (Backside Power Delivery Network)
Foundry Availability: Yes… Read More
Name: PowerVia™
Type: Backside Power Delivery Network (BSPDN)
Developer: Intel Corporation
First Production Node: Intel 20A (2nm-class)
Announced: July 2021
Expected Production Deployment: 2024 (Intel 20A), with high-volume in 2025
Successor Technologies: Integrated with RibbonFET (Intel’s Gate-All-Around)
Competes… Read More
Node Name: Intel 3
Process Class: 3nm (Intel naming)
Technology Type: FinFET (last FinFET node before transition to GAA)
Announced: July 2021 (as part of Intel’s process roadmap)
Production Start: Late 2023 (initial ramp), volume production in 2024
Primary Use Cases: Data center, high-performance computing (HPC), networking,… Read More
Full Name: Lisa Tzwu-Fang Su
Date of Birth: November 7, 1969
Place of Birth: Tainan, Taiwan
Citizenship: United States
Occupation: Chair and Chief Executive Officer, Advanced Micro Devices (AMD)
Education:
B.S., M.S., and Ph.D. in Electrical Engineering, Massachusetts Institute of Technology (MIT)
Dr. Lisa Su is… Read More
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