Rapidus 2nm is Japan’s flagship next-generation logic process node, under development by Rapidus Corporation in collaboration with IBM and imec, targeting high-performance, energy-efficient, leading-edge semiconductor manufacturing. The goal is to achieve mass production readiness by 2027, marking Japan’s re-entry… Read More
Senior Vice President, Operations
Taiwan Semiconductor Manufacturing Company (TSMC)
Y.P. Chyn (sometimes spelled “Chin”) serves as Senior Vice President of Operations at TSMC, where he oversees the company’s global fab manufacturing network, including high-volume fabs in Taiwan, the United States, Japan, and … Read More
Senior Vice President, Corporate Strategy Development
Taiwan Semiconductor Manufacturing Company (TSMC)
— Previously served as SVP, Research & Development and VP of Operations/Technology
Dr. Lo is a highly respected semiconductor executive at TSMC, overseeing corporate strategy and previously leading … Read More
Dr. C.C. (Chih-Chi) Wei
Chief Executive Officer (CEO), Vice Chairman of the Board
Taiwan Semiconductor Manufacturing Company (TSMC)
Dr. C.C. Wei is a Taiwanese semiconductor executive who serves as the CEO and Vice Chairman of TSMC, the world’s largest dedicated semiconductor foundry. A seasoned technologist… Read More
Open Chiplet Architecture (OCA) is an open standard developed by Tenstorrent to address the growing complexity and interoperability challenges of chiplet-based system design. Unlike monolithic SoCs, chiplet-based systems use multiple smaller dies—called chiplets—that are fabricated independently and integrated into… Read More
Gigafab is a term used in the semiconductor industry to describe an ultra-large semiconductor fabrication plant (fab) capable of producing wafers at a scale exceeding 100,000 wafer starts per month (WSPM). These facilities represent the pinnacle of scale, automation, and capital intensity in advanced chip manufacturing.… Read More
Samsung X-Cube™ is a 3D IC packaging technology developed by Samsung Electronics that enables vertical stacking of multiple active logic dies using through-silicon vias (TSVs) and micro-bump bonding. As part of Samsung’s Advanced Package (AVP) portfolio—which also includes I-Cube™ (2.5D interposer-based packaging) and… Read More
Foveros is a 3D chip stacking technology developed by Intel that enables high-density vertical integration of multiple active logic dies using face-to-face (F2F) hybrid bonding and through-silicon vias (TSVs). First unveiled in December 2018, Foveros allows for heterogeneous integration of compute, graphics, AI, and IO… Read More
EMIB (Embedded Multi-die Interconnect Bridge) is an advanced 2.5D packaging technology developed by Intel that enables high-density, high-bandwidth, low-latency interconnects between chiplets (dies) within a single package—without requiring a full silicon interposer. EMIB offers a modular and scalable approach to … Read More
CoWoS® (Chip-on-Wafer-on-Substrate) is a 2.5D advanced packaging technology developed by TSMC that allows multiple dies—including logic, memory, and analog ICs—to be integrated side-by-side on a high-density silicon interposer. CoWoS is a cornerstone of TSMC’s 3D Fabric™ platform and plays a critical role in enabling … Read More
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