Defacto Technologies Wiki

Defacto Technologies is an innovative chip design software company providing breakthrough RTL platforms to enhance integration, verification and Signoff of IP cores and System on Chips.

New segment markets such as automotive, mobile, virtual reality and artificial intelligence require leading edge SoCs with greater functionality, higher performance and much lower consumption. Meeting time-to-market requirements and lowering the overall cost including design steps is becoming a critical factor of success.

By adopting Defacto’s STAR design solutions, major semiconductor companies are continuously moving from traditional and painful SoC design tasks to the Defacto’s joint “Build & Signoff” design methodology. The related ROI has been proven for hundreds of projects.

After a first success on moving traditional DFT checks to RTL, Defacto shifted its focus, 10 years ago, on providing SoC design solutions to help reaching aggressive PPA requirements cost-effectively. Defacto has proven the effectiveness of STAR as a design platform for large SoCs.

RTL BUILD & SIGNOFF DESIGN SOLUTIONS FOR COMPLEX SOCS

SoC design groups continue facing high pressure to innovate quickly and deliver consistently.

Through a unified database with different APIs, Defacto’s STAR enables a cost-effective SoC Build & Signoff process which opens new design optimization capabilities before and after logic synthesis.

During the design process of complex SoCs, STAR helps to:

• Face challenges of moving to sophisticated RTL coding styles like with System Verilog
• Manage into a unified design flow the RTL conciliation process with the variety of multi-domain design standards:
  • Power intent such as UPF
  • Timing constraints such as SDC
  • Physical design information
  • Architectural design formats such as IPXACT
  • Libraries
  • etc.
• Provide the automation to generate ready for synthesis RTL by considering physical, power, timing & DFT constraints

SOC INTEGRATION

Before synthesis, STAR enables full implementation capabilities towards IP and connectivity insertion with real-time integration progress monitoring.

High Level Benefits

• Reduce design cycles – From months to days
• Increase IP reuse ratio

Key Features 

• Multi-format IP Insertion
• Automated connectivity insertion
• Monitor SoC integration progress real-time
• Generate full chip views based on specification file

DESIGN OPTIMIZATION

Reaching power, performance and area (PPA) requirements for complex SoCs is becoming a real challenge. STAR helps optimizing large design netlists to reach aggressive PPA requirements, cost-effectively.

Layout density improvement towards area savings

Hierarchical manipulation based on floorplan changes

High Level Benefits

• Save Area – Between 5 to 10%
• Reduce design optimization runtime from days to hours

Key Features 

• Layout density improvement
• Optimize logic structures
• Hierarchical manipulation
• Automatic feedthrough insertion
• Power/Physical -Aware design restructuring
• UPF/SDC update
• Ability to generate custom reports about design changes

STRUCTURAL VERIFICATION & SIGNOFF

STAR augments existing RTL verification flows by providing fully automated structural checks. Users can define and build their custom checks.

High Level Benefits

• Detect earlier the connectivity and testability issues
• Monitor real time the IP integration process
• Validate quickly 3rd party source IPs
• Highlight complex and difficult to maintain RTL code

IN-HOUSE DEVELOPMENT OF CUSTOM RTL DESIGN APPLICATIONS

Defacto’s STAR is also an application development environment for CAD Teams to develop in-house and custom RTL applications.

It allows multi-APIs access to “RTL Build & Signoff” capabilities with higher flexibility beyond Tcl.

High Level Benefits

• Provide unique customization capabilities
• Open an in-depth access to a unified data model
• Allow high-level capabilities for RTL editing, design exploration and hierarchy handling
• Reduce up to 80% of software development workload

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