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Nimbic (formerly Physware) – 3D Field Solver in the Cloud or Desktop

Nimbic (formerly Physware) – 3D Field Solver in the Cloud or Desktop
by Daniel Payne on 06-13-2011 at 12:57 pm
Categories: EDA, Siemens EDA

I met with Bala Vishwanath, CMO at Nimbic on Monday morning. They had just announced a $6.9M round of venture capital which is something that you rarely hear about in EDA these days, especially during a slow economic recovery.

Intro

Physware – served the package and board markets, co-design challenges (can add IC noise sources). As complexity increased customers wanted more capacity in compute, how about unlimited capacity using the cloud ?

What’s New
Parallelization – both distributed and multi-core. The cloud can handle this configuration, always accurate with full 3D field solving. Product name is nCloud.

Still have enterprise tools on your desktop or on a compute farm.

Cloud – can pay by the hour, or mixed with enterprise.
SaaS – pay by the hour.

Pricing models – by the hour, subscribe annually on the cloud. If Enterprise is 100% , then the could would be double the cores to 8 for the same price.

Security – Even Nimbic cannot see the data. Each HW is separated per client, secure channels used with RSA key pairs in transit (data at rest, on dedicated HW, encrypted Disk, key lives in the instance, all the virtualized layers come from Amazon, then we add on top of that).

Private Cloud – sure that could be used. The Amazon API has been broadly used.
Cloud machines – they reside in Virginia, but could be located anywhere they want.
Managers – can setup monthly budgets to not exceed
Venture financing – $6.9M in Series B, existing Investor and one new one added.

Runing Ubuntu Linux in the cloud right now.

Plan to add more of a flow management system.

How long is your data there? Not archival duration. Results stay there as long as you want. Don’t consider it archival. S3 = Simple Storage Service.
Chile, development (Founder from Chile)

Partnership release with Amazon to be coming.
Nimbic GUI (nWave) – running on Windows, 10 Amazon machines with 8 cores each. GUI also runs on Linux.

Summary
Nimbic re-invents itself by offering a 3D Field solver in the Cloud and securing new venture funding. The trend of EDA companies offering their tools in the Cloud continues at DAC 2011.

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The Secret of Analog Design

The Secret of Analog Design
by Paul McLellan on 06-09-2011 at 5:15 pm
Categories: Uncategorized
1 Comment

Everybody knows that digital designers run on pizza and soda, what one might describe as poor food and weak drinks. At DAC in San Diego I discovered a restaurant that gave away the secret to analog design. And you thought it was a good layout editor and a good circuit simulator. But it turns out that the secret to analog is good food and strong drinks.

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Magma, ARM, GLOBALFOUNDRIES

Magma, ARM, GLOBALFOUNDRIES
by Daniel Payne on 06-06-2011 at 11:07 am
Categories: EDA, Foundries, GlobalFoundries

Introduction
Monday morning at DAC I attended the breakfast presentation from Magma, ARM and GLOBALFOUNDRIES. The 28nm node is ready for business using Magma tools and ARM libraries.

During breakfast I met Karim Arabi, Ph.D. from QualComm. He’s a senior director of engineering in San Diego and wanted to learn more about the 28nm node and how Magma tools could be used in a flow.

Notes

Rod Metcalf – Magma, 28nm Reference Flow Development, using the Talus flow manager for the entire IC design flow. We ran a testcase to ensure silicon validation. Goal is to use the Magma flow on a 28nm Global Foundries process and get 1st silicon success.

– Use the existing libraries which are characterized at specific corners, or create your own corners.
– They used an OpenCore design as their reference example.
– ARM supplied the 28nm libraries, standard cells, memories. Multi Vt libraries were used.
– Talus from Magma: The RTL-to-GDS II tool flow. Offers high capacity, silicon proven at 28nm, high speed designs.
– Low power technologies used, CPF and UPF.
– Talus Flow Manager: a way to capture a complete tool flow. Analysis results are in HTML, easy to read or email complete with links for more details. Pie charts, timing violations.
– Talus Flow Manager – the reference flow provides correct setups for all tools needed, much less work for users to

GLOBALFOUNDRIES – Our largest competitor reports their test chips as tape-outs, we don’t count those as tape-outs.

Summary: Flow of Magma tools and ARM libraries on the GLOBALFOUNDRIES 28nm process are ready to go now, proven, validated.

Jim Ballingall, Ph.D. VP Marketing – GLOBALFOUNDRIES uses high K metal Gate (HKMG). Photo of a quad-core CPU with a GPU from AMD producing 500Gflops performance (beats Sandy Bridge from Intel).

– Ramp of HKMG process is going well. Gate first HKMG approach (Intel uses Gate last HKMG). Intel is using FUD, don’t believe it.
– Market requirements for foundry customers.
o 28nm SLP (Super low power) – low mask count, no stress engineering for lowest costs
o 28nm HPP (High performance process) – uses stressors, >3GHz performance,
– Gate first can be 10 to 20% smaller std cells with Gate First compared to Gate Last approach
– CPU speed versus cost: SLP is lower clock speed and lower cost, while HPP is higher speed and higher cost

Global Solutions – an ecosystem with EDA tool vendors, mask making, assembly. A successful program.
– Design Kits for 28nm SLP are ready now, HPP coming soon.
– Investment of $5.4B in 2011 for GLOBALFOUNDRIES.

Common Platform Partners – IBM, Samsung, ST (Fab synch agreement)

Dresden Fab 1 – plan for 1 million wafers per year at 45nm and below nodes

Fab 8 in NY – shell is complete, equipment moving in, on schedule. 60K wafers/month.

Multi Program Wafers (MPW) – run every quarter, fully subscribed, allow lower costs.

20nm – In development now, partnered with IBM. Results due in 2012/2013. First shuttles started in 2011 Q4.

Q&A

Q: What about fin FET?
A: Looks like a 14nm technology to us.

Q: Is 20nm Gate Last?
A: Yes, that’s true. We choose that for fewer design rules. Gate First was good down to 28nm. At 20nm litho dominates and we choose Gate Last.

Q: What about DFT?
A: We partner with companies like SynTest for DFT tools, they can be integrated into our Talus Flow Manager like any Magma tool.

Largest DAC Banner
Yes, it’s the number 1 EDA company, Synopsys:

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Sunday Night at DAC

Sunday Night at DAC
by Daniel Payne on 06-05-2011 at 7:23 pm
Categories: Uncategorized
2 Comments

San Diego Arrival
It’s another picture perfect day in San Diego as I arrived and checked into the Hyatt. The view from the 40th floor looked magnificent, with the Convention Center just a few minutes away in the distance:

Registration

Check in at DAC is quite automated and it took only a minute to receive my official badge with an Independent Media sticker.

EDAC Party
Tonight is the kick-off event first at 6PM sponsored by EDAC and it’s the annual networking event of the year for us in EDA.

Here I met dozens of former co-workers and EDA clients.

Kathryn Kranen (CEO of Jasper) tried valiantly to address the crowd however the din of networking was just too great. Next year I would try just projecting the key messages on a wall, and let them cycle through instead of live speeches.

Gary Smith
Next up is the 7PM event from Gary Smith EDA. I’m really hoping that these two events are in different rooms so that we may actually get to hear over the roar of networking in the back of the room.

We enjoyed a separate meeting room at Gary Smith’s DAC event on Sunday night. 4G signal coverage was not available with my CLEAR device, so no tweeting this year. Others nearby had zero cell-phone signal as well.

Mary Olsson – 3D packaging. Qualcomm is a big user of TSV and 3D packaging.

Current State of Technology
– TSV: not really cheaper, faster or smaller
– Whatever happened with Multi Chip Modules (MCM)?
– 3 fabs are ready at 200nm now, 300 mm ready in 5 years (too much stress and cracking)
– Today: Mostly memory stacking, wafer stacked SOC, image sensors

3D TSV
– Mostly research and University oriented still
– Bleeding Edge Drivers: Intel, Samsung, Qualcomm, TI, STM, Altera
– Xilinx, Nokia, Nvidia, Broadcom, Cisco
– Tessera, Tezzaron, eSilicon

Standard Drivers : GSA, JEDEC, Si2 Open3D

TSMC Revenue by Technology – 1st quarter numbers, 65% of revenue for 90nm to 40nm nodes, mostly standard packages
– 35% of revenue from above 135nm nodes and larger

Top IDMs and Foundries: Where is their capacity?
– Sweet spot is between 45nm and 60nm
– Intel/Samsung vs everybody else
– Qualcomm driving the bleeding edge of 3D packaging technology

TSMC Foundry Drivers
– 48% communications
– 23% consumer
– 18% industrial
– 11% industrial

PCs – shipped 379M units in 2010

iPad (Tablets) – 136m units in 1Q2011

2015 Time frame – next big push from emerging nations to start consuming personal electronics

What is true 3D/TSV?
– Today we see 2.5 and 3D TMV (stacked die for memory, SOC, SiP, Flip Chip, PoP, Cu pillar bump, many via types

AMKOR photos of molded via, package on package techniques

EDA – Sigrity (Orbit10 Planner), Micro Magic (Max 3D), Apache (RedHawk, Sentinel)

What to look for – OSATs, eSilicon, Tessera, Tezzaron

RF challenges

3D Summary

Read the GSA Guide (Herb Reiter)

Follow the money – OSATs spend money on copper wire bonders, new test equipment

Watch those hiring – Intel, Qualcomm

Gary Smith

EDA 2Q 2011 Forecaast
$4896 2011
$5325 2012
$5671 2013
$5885 2014
$6612 2015

The Semiconductor Infrastructure
– The semi cycle: VC funding, EDA, embedded sw, compute power, process r&d, semi equipment, foundry, packaging
EDA – tools to enable design (at a cost that allows operating at a profit)

Costs – Design companies cost more than EDA tools (embarrassed by low price of EDA tools)

Cost of SOC Design – Keep the cost of a new SOC below $25M will attract VCs again.
– Costs above $50M hurts even IDMs

ITRS Cost Chart for 2010

Is EDA affordable?

Design Teams – 100 to 200 engineers
– For 104 million gates (should be about 30 HW design engineers, costing $18.7m)
– 160 SW engineers cost $56M, total of $75M

Cost Curves for HW Design Teams (Needs to be kept under $25M)

Ideal Number of Blocks: 5
– Most designs have 25 to 35 blocks (more blocks slows design process down)

What is Block Size?
– 100 million gate (90 million gates on platform, 10 million left to design)
– Number of engineers per block 6 engineers

EDA Tools Handle gates?
– 4 million minimum, 20 million needed

At 22nm – need 88m gates capacity
At 16nm – need 177m gates
At 11nm – need 354m gates

R&D Engineers – do you know how design uses the EDA tools?

How to Follow Moores Law?
– Productivity tools, keep close to design engineers
– Get involved in sw productivity

EDA History
– Cadence as technology leader 1990 to 1997
– 2004 to 2007 Fister’s Folly as
– 2003 SNPS is #1 technology after Avant! Acquisition
– 2008 and 2009 SNPS as #1 tech leader
o Mentor and Magma still close in technology
o Who handles 22nm design? Large or small companies?

Summary
The mood at DAC this year is optimistic, there’s talk of hiring and people are eager for the Keynote address on Monday and the flurry of events planned. I’ll be blogging each day as I visit EDA vendors that offer transistor-level tools like: SPICE, DRC, LVS, 3d extraction, Custom IC layout tools, and more. On Tuesday I’ll be at the Panel Session on “3D Extraction: Coming to a Design Near You?“

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GLOBALFOUNDRIES 28nm Design Ecosystem!

GLOBALFOUNDRIES 28nm Design Ecosystem!
by Daniel Nenni on 06-01-2011 at 11:00 am
Categories: Arm, EDA, Foundries, GlobalFoundries

GLOBALFOUNDRIES will show off its 28nm design ecosystem at #48DAC next week in San Diego. The company will feature a full design ecosystem for its 28nm High-k Metal Gate (HKMG) technology, including silicon-validated flows, process design kits (PDKs), design-for-manufacturing (DFM), and intellectual property (IP) in partnership with industry leaders. 28nm is the second node of HKMG production for GFI with 32nm AMD Llano dice already in the field. CPU’s and GPU’s are the most difficult designs to manufacture and Llano is both.

“We have been in production of real HKMG products for months,” said Mojy Chian, senior vice president of design enablement at GLOBALFOUNDRIES. “We have been leveraging this experience by collaborating with ecosystem partners to build this knowledge into the design infrastructure and tools we provide to customers at 28nm. This focus on early design-technology co-optimization and silicon validation will translate to accelerated time-to-market for the next generation of power-sensitive consumer electronics and mobile devices.”

Top Ten Reasons
Why You Should Visit GLOBALFOUNDRIES at DAC

Okay, 10 is a little much so here are my:

Top Three Reasons
Why You Should Visit GLOBALFOUNDRIES at DAC

[LIST=1]

  • Processor Cores (ARM)
  • 28nm SLP
  • Foundation IP (ARM) and DRC+

    Per Eric Esteve’s article on ARM and GlobalFoundries: a key relationship in the future:Although there has been always a strong relationship between ARM and GlobalFoundries, it is interesting to notice that Intel has helped to boost it and make it even stronger.……

    The mobile internet craze continues to drive semiconductor growth and who owns the heart and soul of mobile internet? That would be ARM. Bundle that with a Gate-First HKMG low power process (longest battery life), high yielding foundation IP, and the hottest DFM program (DRC+) and you get a superior price/performance/power mobile platform. Just my opinion of course.

    Will ARM processors continue to dominate the mobile internet craze? In a keynote address at Computex in Taiwan, ARM President Tudor Brown said, “Today we have about 10 percent market share [in mobile PCs]. By the end of 2011 we believe we will have about 15 percent of that market share as tablets grow. By 2015, we expect that to be over 50 percent of the mobile PC market.” If I was a gambler, which I am, I would not bet against ARM on this one.

    Don’t forget to share this on LinkedIn:

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    ARM vs Intel step 2…Intel’s nervous breakdown about Microsoft… and cut ATOM price

    ARM vs Intel step 2…Intel’s nervous breakdown about Microsoft… and cut ATOM price
    by Eric Esteve on 06-01-2011 at 8:52 am
    Categories: Uncategorized
    1 Comment

    In the unspoken war between ARM and Intel, a couple of interesting facts have surfaced during the last few days:

    • Intel nervous breakdown in respect with their 30 years old accomplice in the Wintel gang
    • ATOM latest version Cedar Trail fabbed on 32nm technology, targeted for mobile computing, will be priced at a 30% to 50% discount… should we thank ARM for this price drop?

    Let’s have a look at the facts before to give our thoughts about these “strategic” moves from Intel. At its analyst meeting on Tuesday, Intel chief executive Paul Otellini talked about Windows 8 porting on ARM processor core:“I believe that Intel is still the only architecture at the chip level whose silicon runs every major operating system out there,” Otellini said during the analyst meeting. “And you all know the story on this – the ARM guys are getting a port to Windows. But what the ARM guys are getting are four ports to Windows. Every operating system has to write to the chip and with the writing at Microsoft’s doing is doing four versions for ARM vendors, just like Android writes to multiple versions of the ARM chips, and to Intel, now.” The “four ports” were assumed to be four separate versions of the OS, which Microsoft denied.“Intel’s statements during its Intel Investor Meeting about Microsoft’s plans for the next version of Windows were factually inaccurate and unfortunately misleading,” Microsoft said in a statement. It look like the first crack which may cause a rift in the 30 years old friendship…

    Price drop: Intel had also announced a strategy shift toward developing ultra mobile chips, while later showing off Atom-based phones, tablets, and some cool new PC technologies.

    When INTEL launches Cedar Trail, the latest version of the Atom-processor fabbed on 32nm process technology, we can expect to see the cost drop between 30% and 50% according to several netbook manufacturers in Taiwan that SemiAccurate has spoken with. The manufacturers prefer to remain anonymous since they are not officially allowed to discuss pricing on an unreleased product.

    Intel will launch 2 different versions of Cedar Trail. One for netbooks and one for nettops. The mobile versions will be named N2600 and N2800. The Atom N2600 will be priced at $42 and N2800 at $47.

    According to one analyst who queried Otellini at the analyst day, with Windows on ARM, that spiral would then shift over to ARM and its licensees. And that would supposedly take a deep bite into Intel’s profit margin. Otellini, however, dismissed the claim. First off, he said, Intel was “very competitively priced with ARM-based products,” at least where tablets and smartphones are concerned. (Intel announced yet another delay to its X86 smartphone program on Tuesday, pushing X86 phones back into 2012.) Arguments that Hewlett-Packard or other OEMs could somehow use ARM as a lever to differentiate themselves and design a cheaper but still profitable PC “don’t understand the way this business works,” Otellini said.”

    The outcome is clearly that Intel is nervous. Attacking Microsoft through their new partnership with ARM is not only unfair, it is also somehow stupid: it could be like sending a boomerang. Microsoft is just acting on the market like Intel, they both benefit from a monopoly position to sell for high price, high GPM (Gross Profit Margin), products which used to be innovative – in the past. Nevertheless, as a consumer, we should enjoy this nervous breakdown from Intel, when it comes to the ATOM price drop. The ARM vs Intel war starts to be positive, if it pushes Intel to lower the prices!

    When I say that Intel is no more innovative, I agree that I am slightly biased. But, as a matter of fact, Intel is still struggling to launch their X86 processor for smartphone, as the program has been further delayed, back into 2012. Intel, with revenue greater than GDP of Senegal, Paraguay and Cambodia aggregated (a 35 million population) and with a R&D budget greater than total R&D spending of Sweden, is simply not able to catch up with the Qualcomm, STM, TI or Nvidia, and launch a competitive wireless application processor like OMAP5.

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    Eric Esteve

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    Sagantec 2 Migrate iPad2s @ #48DAC

    Sagantec 2 Migrate iPad2s @ #48DAC
    by admin on 05-30-2011 at 2:53 pm
    Categories: EDA

    Sagantec is the leading EDA provider of process migration solutions for custom IC design. Sagantec’s EDA solutions enable IC designers to leverage their investment in existing physical design IP and accomplish dramatic time and effort savings in the implementation of custom, analog, mixed-signal and memory circuits in advanced process technologies.

    These solutions have been used commercially by tier-1 semiconductor companies, and have been proven to reduce layout time and effort by factors of 3x to 20x and enable dramatically faster introduction of IC products in new technology nodes.

    Apple does not allow iPad2 “giveaways” so Sagantec will be “migrating” iPad2s to a select few conference goers that register for SemiWiki.com. If you are already registered for www.SemiWiki.com just stop by and check-in to qualify for the “migration”.

    Sagantec at DAC 2011

    Featuring the following presentations and demos:

    ·Custom, analog and mixed-signal IP migration
    ·Migration to latest technologies: 40, 32 and 28nm migration
    ·Automatic PDK update, design rule changes, and DRC correction
    ·Standard cell library migration and optimization

    ·Custom, analog mixed-signal IP migration

    Migration of custom IP to next process node or different foundry
    ·Supporting all process technologies
    ·Maintain and enforce geometric constraints like symmetry, matching, alignments, etc.
    ·Maintain original design hierarchy and structure
    ·Support Cadence Virtuoso® IC5 and IC6 database
    ·Support Pcells and all other Virtuoso data objects
    Check out analog IP migration success story

    ·Migration to latest technologies (including 28nm)

    Sagantec migration technology has been used and proven down to 28nm
    ·Overcoming topology and device changes
    ·Overcoming new restrictive design rules
    ·Used an proven on multiple designs
    Check out new 28nm migration success story article

    ·PDK and design rule changes
    Adjusting layout to new PDK and design rule changes
    ·Swap between Pcells and PDKs
    ·Update new design rule values
    ·Automatic correction of DRC errors
    ·Implement recommended DFM rules without changing layout foot-print
    ·For custom, analog/ mixed-signal blocks and IP
    ·For large digital blocks and full chips
    Check out new PDK adjustment success story article

    ·Standard Cell Library Migration & Optimization

    Migrate, modify and optimize standard cell libraries in the most advanced technologies
    ·Migrate libraries to next technology node or between foundries
    ·Supports topology and routing changes (e.g. for 28nm and 22nm)
    ·Create new library derivatives (HS, LP, etc)
    ·Analyze and optimize libraries for yield


    Process migration Change #tracks

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    Going to DAC? There’s an app for that

    Going to DAC? There’s an app for that
    by Paul McLellan on 05-30-2011 at 1:51 pm
    Categories: General

    Are you going to DAC in San Diego? Do you have an iPhone? In which case Bill Deegan’s dac48 app is something you should install before you get there. It’s free, which makes a nice change from EDA software pricing.

    The app substitutes for the various paper, agendas and maps that you need to consult to find exhibitors, check up when sessions are and put them on your calendar. It’s not perfect (he ran out of time); for instance the booth numbers are not linked on the exhibitor map.

    And yes, it’s only on iPhone so far, Android probably has to wait until DAC49.

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    New TSMC 28nm Design Ecosystem!

    New TSMC 28nm Design Ecosystem!
    by Daniel Nenni on 05-28-2011 at 9:23 pm
    Categories: EDA, Foundries, TSMC

    TSMC rolled out the new reference flows for 28nm design as part of the Open Innovation Platform. The biggest surprise (to me) is that Cadence is STILL in the TSMC reference flows!

    The updated TSMC OIP wiki is here, the Reference Flow 12.0 wiki can be found here, the AMS 2.0 reference flow wiki is here, and the official TSMC PR is here. The latest slides are included in the wikis for your viewing pleasure. TSMC customers can download the official materials at TSMC Online.

    “TSMC customers can immediately take advantage of our 28nm advanced technology and manufacturing capacity while preparing for 20nm in the near future,” said Cliff Hou, TSMC Senior Director, Design and Technology Platform. “We have enabled customers to achieve their product design goals by closely collaborating with our EDA and IP partners to deliver a solid 28nm design ecosystem. In addition, the introduction of Reference Flow 12.0 and AMS Reference Flow 2.0 address critical design issues for the next generation of 28nm and 20nm applications.”

    This announcement is a big fat hairy deal for several reasons:

    [LIST=1]

  • Cadence is still partners with TSMC
  • 2.5D design
  • Emerging companies dominate
  • 28nm Power, Performance and DFM Design Enablement

    While Cadence executives pledge their allegiance to the open TSMC iPDK standard, Cadence product people continue to release INCOMPATIBLE products. The upcoming release of Virtuso GXL 6.1.5 (the high end version) will NOT allow a non SKILL based PDK to run (core dumps). My guess is that Virtuoso XL and L versions will soon follow. How will Cadence get away with this travesty? Big Cadence customers (80% of their revenue base) build their own PDK’s even if they use TSMC. Closed skill based PDK’s for Cadence customers versus open PDK’s for everyone else, great corporate strategy……. NOT! Cadence will be punished for this short sighted behavior by customers, it’s coming, believe it.

    TSMC will be the first fully 3D IC design capable foundry, no argument there. 2.5D design includes multiple dies to be integrated with a silicon interposer. Reference Flow 12.0 features new design capabilities in: floor planning, P&R, IR-drop, and thermal analysis to accommodate multiple nodes simultaneously. Also included is a new design for test methodology for 2.5D design.

    In addition to the “EDA Monopoly”, emerging companies continue to impregnate the TSMC reference flows:

    Apache, Arteris, AtopTech, Carbon Design System, CLK DA, Extreme DA, Sigrity, Sonics, SpringSoft, Berkeley DA, Ciranova, CST, EdXact SA, CWS, Helic, Integrand, Lorentz, and my personal favorite Solido DA. EDA innovation comes from emerging companies so TSMC is doing the semiconductor design ecosystem a big fat hairy favor here by putting new tools in silicon. NO OTHER FAB DOES THIS!

    Timing degradation from wire and via resistance, power leakage, hotspot checking and fixing are also addressed in the reference flows. Smaller geometries bring bigger problems, believe it.

    TSMC has a monster booth at DAC with a partner pavilion. The TSMC DAC page is herewith:

    In case you don’t follow my Twittering @DanielNenni: TSMC and UMC will be back at 95% utilization in Q3 due to surging orders from the mobile internet craze. Most of which include ARM processors @ 40nm bearing the names: Snapdragon for Qualcomm, Tegra2 for NVIDIA, Armada for Marvell, and i.MX for Freescale at TSMC and OMAP4 for Texas Instruments at UMC. TSMC also has 100+ tape-outs coming in at 28nm so don’t expect excess fab capacity anytime soon.

    Taiwan was absolutely crazy this month. The drought continues, the streets of Hsinchu were packed with scooters, and at2pmon Wednesday there was a bombing drill. For 30 minutes we were required to stay inside while the streets were cleared. This has been going on for years and it reminded me of elementary school where we hid from atomic bombs (cold war) under our desks.

    Don’t forget to share this on LinkedIn:

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    65nm to 45nm SerDes IP Migration Success Story

    65nm to 45nm SerDes IP Migration Success Story
    by Daniel Nenni on 05-25-2011 at 3:43 pm
    Categories: Uncategorized
    4 Comments

    The problem:To move a single lane variable data rate SerDes (serializer-deserializer) from a 65nm process to a 45nm process, achieving a maximum performance of up to 10.3 Gbps. This is a large piece of complex mixed-signal IP with handcrafted analog circuits. Circuit performance and robustness are critical and must be maintained in the migrated implementation.

    The original design consisted of over 30 blocks with a hierarchical device count of around 30,000 (about 200,000 flat).

    After the first migration, business opportunities arose requiring the same SerDes IP to be moved to two further different 40nm processes.

    Design Environment: 65nm Serdes has been designed in Cadence Virtuoso XL, using the 65nm foundry provided PDK (technology files, pcells, etc). Target 45nm migrated result should be restored into a Cadence Virtuoso XL database environment using the new target 45nm foundry provided PDK. All the Cadence database specific object need to be maintained (pcells, via cells, connectivity, etc.)

    The main changes : There were many changes in design rules between the two processes: Dummy poly insertion and pitching being the most challenging. In addition, all devices were resized and the new sizes needed to be gathered from the netlist (netlist-driven migration).

    A layout clip showing devices after automatic dummy poly insertion and gate gridding (enforcing strict poly pitch)

    The main requirements:

    • · The basic topology needed to be preserved.
    • · The design hierarchy needed to be preserved.
    • · Matching devices and routing should remain as such. Other topology sensitive features such as symmetry, alignment, etc, should be maintained.
    • · The migrated SerDes should be LVS clean. This includes both connectivity as well as matching the new schematic device sizes.
    • · The flow should allow quick sizing and ECO iterations
    • · The migrated SerDes should have minimal remaining DRC violations requiring manual fixup.
    • · Maintain data integrity: Virtuoso data structure and all objects kept intact

    The schedule: The productivity goal was set to at most 1/5 of original layout time. (minimum 80% effort and time savings) .

    Quick Initial Prototyping: One of the first goals was to figure out the effective scaling factor of the migrated IP. This is one of the clear benefits of automated migration which allows designers to try multiple scaling and sizing scenarios based on the target technology devices and rules. Many experiments can be done quickly and very early on, to figure out the effective scaling, footprint, effect on performance, and other consequences of each scaling and sizing scenario.

    How the migration was addressed: The entire Serdes IP comprises over 30 main blocks, each having up to 10 level of hierarchy and an average of 1000 devices (hierarchical count).To facilitate concurrent layout-circuit optimizations with quick turn-around time, a block-by-block execution method was chosen.While performing each block at a time, the migration flow also takes care of global (top) level metals and over-the-block supply rails to make sure that the blocks are properly positioned and connected within the top level. Most of the blocks are custom handcrafted using device level programmable cells (Pcells) of the original 65nm foundry PDK . These Pcells as well as other symbolic structures had to be mapped to and substituted by similar devices and structures from the target foundry 45nm process. The migration software uses this mapping to generate the new devices and objects using the right parameters, make room for each of their instances, place them and connect them in the migrated layout. A few blocks also used digital control sections that were implemented using a specific logic cell library shared among all the blocks. This common logic cell library was also migrated to the 45nm target process rules and maintained as a common library across the entire IP, and then used during the block-level migration.

    Device Sizing     : Final sizing for devices was not fully determined before starting the project. Initial sizing was done based on schematics and then was subsequently refined after layout extraction and circuit validation. This is where having an automated migration flow makes a huge difference as once the flow is in place, all subsequent sizing and tuning layout iteration are run very quickly ( in less than an hour). Using this block-by-block approach enabled having a virtual “assembly line” pipeline of blocks in different stages of migration and tuning and accelerated the overall project significantly.

    Results: The SerDes migration was delivered on-time. LVS was virtually clean (there were a few minor issues due to incompatibilities between the PDK libraries). DRC quality was better than expected, with most blocks having under 50 DRC violations left. In fact the project exceeded its initial productivity goals: each block takes only minutes to run, and the last few remaining DRC errors took only a few hours to clean up. The overall effort, including the manual layout cleanup, took less than 1/10 of the original layout time (90% effort and time savings).
    Automatic migration preserves symmetry and matching. Same clip before and after migration.

    65nm (green) versus 45nm (purple)

    Why Sagantec:The IP design team looked at different commercial solutions for Analog/MS migration and evaluated a few alternative offerings from multiple EDA vendors. While other vendors addressed some aspects of the problem, the customer found Sagantec as having the most complete solution and one that most effectively addresses the size, complexity and the overall layout effort productivity goals. Another significant factor was supporting and maintaining the Cadence Virtuoso database and objects which was important to the design team. Overall the Sagantec approach seemed the most practical and least disruptive to the team’s current design flow and tools.

    Consecutive Successes:     Following the success of this migration project, the IP design team decided to use the same flow to migrate this IP to two other 40nm processes (using different PDKs and technology files respectively). Each of these subsequent process migrations was also a success, completed on-schedule and exhibited similar productivity gains. Overall this migration methodology and flow enabled the team to respond quickly to new business opportunities and process requirements, leveraging their original design investment and minimizing their efforts per each process implementation.

    Custom IP migration: Moving a complex custom IP block from one process to a different process can either be done by an experienced layout team or using an automated flow that handles almost all of the work automatically, such as Sagantec’s migration technology. For migration to older process nodes or between similar processes, it is possible that a shrink followed by manual fix-up of violations would work, but in advanced process nodes and when the processes have very different rules, the number of violations generated can be overwhelming and impractical for such approach. The alternative would be a complete redesign, which in this case would be prohibitively expensive in both schedule and resources required. In addition to licensing migration software, Sagantec has also experienced application engineers that can do migrations as a service to minimize turn-around time, get the highest quality results and maximize ROI.

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