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Semiconductor Expert Forum

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Semiconductor Industry Standards Update 2012

Semiconductor Industry Standards Update 2012
by Daniel Nenni on 05-27-2012 at 12:11 am
Categories: EDA

Standards have been proven to reduce cost of operations, drive greater process efficiencies and offer greater opportunities for start-up companies to infuse fresh technology in the design and manufacturing of IC’s. Si2 standards have been targeted to resolve “pinch-points” in the overall semiconductor supply chain with a steadfast focus on rapid adoption of these standards.

This day-long program, consisting of 4 individual events, will showcase activities currently underway with an eye towards demonstrating the value of these programs to the program participants and to the overall semiconductor industry. Therefore, this day-long session should entice engineers and technologists working at both current and cutting-edge technology nodes and also managers responsible for driving both design and manufacturing strategy, and related financial and staffing decisions. A featured part of the program will celebrate the 10th Anniversary of OpenAccess.

  • A complimentary luncheon and an afternoon reception will highlight this occasion.
  • All sessions are free, register here.
  • For admission into the Moscone Center you will need to register here for DAC.
  • Note that there is a Free Monday option, which will be sufficient to get into the convention hall and then to Room 301. Register here for a Free Pass!

[TABLE] cellspacing=”3″ style=”width: 100%”
|-
| style=”width: 53px” | 09:00am – 10:30am
| OPS Comes to Life
The Open Process Specification (OPS) standard, from Si2’s OpenPDK Coalition, contains all of the data elements that are necessary to create a Process Design Kit (PDK) in any EDA vendor’s or company proprietary design flow. This session is designed to appeal to any engineer working with PDKs and any engineering manager making budgeting or ROI decisions concerning PDK development. It will describe the structure and organization of this very important new standard in the industry and examples of the use cases that this standard will cover.

Presentations:

  • Introduction: Jim Culp (IBM)
  • Status / Next Steps: Gilles Namur, (STMicro)
  • Symbols: James Masters, (Intel)
  • Callbacks and Parameters: Gilles Lamant, (Cadence)

|-
| style=”width: 53px” | 10:45am – 12:15pm
| DRC+ – The Next Frontier
DRC+ augments standard DRC by applying fast 2D pattern matching to physical verification to quickly identify problematic 2D patterns called hotspots In contrast to more time consuming lithographic simulations used after tapeout, DRC+ is transparent to designers as part of their normal DRC checks and it’s fast enough to be inserted throughout the entire design flow.

This award winning technology has been contributed to Si2 and it forms the basis for our next generation OpenDFM standard. This session will cover process characterization, pattern recognition and physical verification using DRC+ acceleration that can be used by any DRC engine.

Presentations:

  • Introduction / Quick Refresher on DRC+: Vito Dai (GLOBALFOUNDRIES)
  • Standardization Status: SW Paek (Samsung)
  • Next Steps: Jake Buurma (Si2)
  • Panel: Rachid Salik (Cadence), Vito Dai (GLOBALFOUNDRIES), SW Paek (Samsung), Concetta Riccobeni (LSI), Fred Valente (TI)

|-
| style=”width: 53px” | 12:15pm – 01:45pm
| Lunch: Si2 Open Luncheon, A celebration of the 10th Anniversary of OpenAccess
This complimentary lunch will briefly host the annual open Si2 meeting that will include a short presentation on the “state-of-the-union” at Si2 and announcement of the results of the annual election of Si2’s board of directors. This will be a preamble to the celebration of the 10th anniversary of Open Access. It will cover the road traveled from the genesis of a dream to the reality of today. It will showcase presentations and testimonials, and will recognize key individuals who have contributed to the success of OpenAccess. This event is sponsored by Cadence Design Systems, GLOBALFOUNDRIES, LSI, NanGate, and Spectral Design & Test.
|-
| style=”width: 53px” | 02:00pm – 03:00pm
| New Si2 Standards In Action On Real-World Tools
This session will demonstrate the recently published Si2 Open Process Design Kit (OpenPDK) standards and Open Design for Manufacturability (OpenDFM) standards working with commercially available tools. Si2 standards promote interoperability and these demos are designed to illustrate that point. The demos will show the OpenPDK symbol standard validating the correctness or incorrectness of a schematic symbol change as compared to the standard in real time. The OpenDFM standard will demonstrate an integrated physical verification flow from an electronic Design Rule Manual (eDRM) to XML, to OpenDFM and to four different DRC engines.
|-
| style=”width: 53px” | 03:15pm – 04:30pm
| Standards for a 3D World
Si2 is focusing on developing design flow standards, its area of expertise, to support both 2.5D and 3D designs using through silicon vias (TSV). Specific areas being covered at this time include standards for sharing constraints for power distribution networks, thermal constraints to define such things as “keep-out areas” and constraints to import IP (both dies and blocks) into pathfinding and constraints out of pathfinding into downstream design of individual dies, stacks and interposers. To ensure consistency in standards and to prevent duplication, the Open3D TAB is connected to other relevant groups to ensure a complete solution.

So, this short session will include a presentation of status of activities in the TAB followed by a panel discussion which will include industry experts who will present some of the issues being addressed now and also cover some of the future challenges.

  • Presentation: Open3D TAB Status / Next Steps: Riko Radojcic (Qualcomm)
  • Panel: Arif Rahman (Altera), Ravi Varadarajan (Atrenta), Aveek Sarkar (Ansys), Keith Felton (Cadence Design Systems), Dusan Petranovic (Mentor Graphics), Riko Radojcic (Qualcomm), Alex Samoylov (Invarian)

|-
| style=”width: 53px” | 04:30pm – 06:00pm
| Si2 Open Networking Reception
This complimentary reception will continue the celebration for the 10th Anniversary of OpenAccess. Free hors d’oeuvres and refreshments will be provided. This event is sponsored by Cadence Design Systems, GLOBALFOUNDRIES, LSI, NanGate, and Spectral Design & Test.
|-

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Apache Ansys Update 2012

Apache Ansys Update 2012
by Daniel Nenni on 05-26-2012 at 9:26 pm
Categories: Ansys, Inc., EDA

Apache is one of the brightest stars in the EDA universe. Paul McLellan has done a nice job covering them before and after the Ansys acquisition. Check out the Apache SemiWiki landing page HERE. The Apache wikis are also very well done and it has been a pleasure working with the Apache marketing team. Expect more innovative things from Apache Ansys right around the corner, believe it.
Continue reading “Apache Ansys Update 2012”

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The Apple iPhone5 Olympic Launch Scenario

The Apple iPhone5 Olympic Launch Scenario
by Ed McKernan on 05-25-2012 at 9:23 am
Categories: General
1 Comment

Just days after I posted a blog on an early September iPhone 5 launch, the spies from Asia started flooding the rumor mills with Apple supply chain maneuvers that are not easily hidden suggesting that D-Day logistics are farther along than we imagined. This flood of information, coupled with the heightened Samsung-Apple Battle Royale set for 2H 2012, left me wondering if there was an alternative scenario: An Apple iPhone 5 Launch right before the Samsung sponsored Summer Olympics that start July 27[SUP]th[/SUP] in London. Call it the Marketer’s Dream Scenario for disrupting the enemy’s well-planned, already in motion, expensive plans that can be leveraged to catapult Apple firmly into Mobile Tsunami dominance.

Over the course of the past year, the smartphone market has consolidated around Samsung and Apple as their combined market share has increased by 20% to roughly 53%. Apple’s market share is ecosystem driven that delivers high profits for the pleasure of iOS across all devices. Samsung, on the other hand, is cost driven with more of its units selling at lower price points. If current trends continue, meaning Google or Nokia don’t generate traction with their new smartphones, the game could be over in another 12-18 months as the duopoly head to 70% share or more. What’s more, if Apple does get an injunction on Samsung for shipping what they see as an IP violating Android O/S based smartphone, then the game tips further to Apple’s advantage. Samsung would need to retool with a more expensive Microsoft O/S.

In the course of the past two weeks, word has arrived that the supply of 3.5” LCD displays used on the current iPhone are expected to be reduced by 20% in this quarter and by a third for the rest of the year. Sounds like a move to the $99 slot. A few days later, word from the reputable WSJ arrives that the new 4” iPhone 5 display will ramp in production in June, which seems early if the fully product launch is September or October. WSJ has been known to only publish Apple articles that have a legitimate source (meaning Apple inspired or contrived).

On Monday, a report by PiperJaffray confirms what I wrote on May 9th, that Apple has cornered Qualcomm’s 28nm 4G LTE supply. This means Samsung, HTC and everyone else are impacted with limited supply through the end of 2012. As the only vendor with a low power 4G LTE solution, Apple seeks to retain its premium position while expanding market share. In addition, Apple will follow through on the product theme that all new devices and PCs will contain high-resolution “Retina” screens and an option for 4G LTE. The new iPAD launched in March will be followed by Ivy Bridge based Mac Book Pro’s and Mac Air’s to be launched at WWDC in mid June. So while Samsung announced a 4G LTE Galaxy III a couple weeks ago, the availability has been delayed until July, prior to the Olympics. But what if the quantity is limited, where will customers turn?

If, as I suspect, Apple knew Qualcomm would be stretched to ramp 28nm this summer, then it makes sense that they would take advantage of the situation by locking down supply and launching as soon as possible, even to the point of taking orders 4-6 weeks in advance of shipment as they have done in the past. The rest of the market would be frozen while Apple proceeds to suck all the oxygen out of the room. In terms of actual iPhone5 product SKUs, Apple would likely reserve 4G LTE for the $399 spot while offering 3G versions at $199 and $299.

In terms of timing of an “Olympic Launch”, my best guess would be Tuesday July 24[SUP]th[/SUP] which gives the press multiple days to fawn over the new product before everyone turns their attention to the games. The announcement would precede an earnings call on July 26[SUP]th[/SUP] in which the majority of the focus would be not on the recently concluded quarter but on the revenue outlook for 2H 2012. Tim Cook would then have successfully crossed the chasm of an iPhone revenue downturn that occurs when the general public gets wind of a new device. My guess is that the iPhone 5 hardware will be more stable going forward than the iPAD, where Apple has lots of room to expand the product line further up into the PC space and down into the Amazon Kindle direction.

What is the message from Apple’s iPhone 5 launch and the projected growth to come? For some vendors, a decision must be made as to whether to enter the Apple Keiretsu or focus on other markets. After all, according to IHS iSuppli, Apple is expected to buy $27B of semiconductors this year, or roughly 9% of the worldwide total. DRAM, Flash and processors are firmly under their control. Apple may soon have the upper hand in its negotiations with Qualcomm and Intel related to preferred pricing and supply of baseband and leading edge foundry capacity. The two may, in the end, need each other in order to have enough heft to protect their assets from commoditization.

Full Disclosure: I am long AAPL, INTC, QCOM, ALTR

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3D Transistors and IC Extraction Tools

3D Transistors and IC Extraction Tools
by Daniel Payne on 05-24-2012 at 4:05 pm
Categories: EDA, Siemens EDA
1 Comment

Have you ever heard of a Super Pillar Transistor? It’s one of many emerging 3D transistor types, like Intel’s popular FinFET device.

In the race to continuously improve MOS transistors, these new 3D transistor structures pose challenges to the established IC extraction tool flows.

Foundries have to provide an Effective Profile to EDA companies that describes the shapes used to fabricate any MOS device plus all of the interconnect levels. TCAD tools can be run to simulate what the shapes of an effective profile should be.

How can foundries keep their process proprietary yet provide a geometry for extraction tools to actually use?

Now that’s a constant challenge. I met with Carey Robertson of Mentor Graphics to better understand how the challenges of 3D transistors are being met with the latest generation of IC extraction tools like Calibre xACT 3D.

Q: Intel has an early lead in production-ready 3D FinFETs. When will the Foundries offer FinFETs?
A: The foundries are saying that FinFETS will be used at the 14nm node, however there is much speculation that we could see FinFETS at the 20nm node.

Q: How does a 3D transistor effect the job of IC extraction?
A: The complexity of the effective profile is always increasing, so we have to use more elaborate 3D models that in return require more processing time for detailed extraction used by memory and analog designs.

Q: Will rule-based methods be sufficient in IC extraction?
A: Only for the M1 and higher interconnect layers, for the lower layers near the MOS device you need to really use a field solver to get the accuracy.

Q: How is extraction changing now with 3D?
A: Before we could have a wide distinction between interconnect models and transistor models for parasitics. Now we are using a 3D field solver to extract the R and C values for the MOS source and drain connections.

With 3D devices the MOSFET can even be broken up into multiple fins. We are moving from a table-based and rule-based extraction approach, to explicit calculations. These calculation are just more computational and require longer run times.

Q: What is different about Mentor’s 3D field solver?
A: Our tool is called xACT 3D and is a field-solver used by designers and is well suited for FinFETS and 3D devices. Caliber xACT 3D has a deterministic field solver (similar to Raphael in the past, although faster), and the output is a SPICE netlist. The extraction input is a GDS II file and foundry decks, so it feels like a standard extraction tool.

The old Raphael was 1,000x slower than rule-based approaches so is limited to TCAD and small transistor counts.

xACT 3D is maybe 3 to 4x slower than rule-based solvers, however to get results faster you can add more hardware and still stay within 2% of TCAD tool results.

Q: What is the capacity of your 3D field solver?
A: xACT 3D has been run on multi-million transistor memory layouts (see the STARC paper at DAC), flat. It’s not meant for digital sign off. If you want to send the most accurate netlist to SPICE or Fast SPICE for circuit simulation then xACT 3D is the tool for you.

If you want to analyze multi-million digital gates into PrimeTime, then consider a selected net flow.

Q: What is new with xACT 3D this year compared to last year?
A: Well, we have performance improvements (memory up to 4X, analog about 1.5X to 2X), foundry decks at 20nm, more foundry support, plus faster and better viewing of results.

Q: Who would be interested in using a 3D field solver?
A: Memory designers using pillar transistors would need to use a field solver.

Q: Does your field solver work hierarchically?
A: No, it’s not a hierarchical tool although it can read a hierarchical layout and produce a hierarchical netlist.

Q: Will you be presenting at DAC this year?
A: We may be in a panel discussion organized by Ed Sperling, so stay tuned.

Q: What are some other trends happening in IC design today?
A: With Double Pattern Technology (DPT) being used at 20nm it is creating more corners for simulation, so at 28nm we had 5 corners and at 20nm we will have from 11 to 15 corners. More corners means more simulation time.

Q: Who else at Mentor is presenting at DAC this year?
A: Claudia Relyea is presenting with ST in a poster session on 3D extraction.

Karen Chow has a presentation on sensitivity analysis with STARC.

Summary
The DAC conference and trade show is going to be exciting this year as the EDA vendors have adapted their IC design tools to enable design with 3D transistors. Find Mentor Graphics in booth #1530 at DAC.

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Solido Design Automation Update 2012

Solido Design Automation Update 2012
by Daniel Nenni on 05-24-2012 at 10:27 am
Categories: EDA, Solido

Having spent a considerable amount of time with Solido, they were one of the founding members of SemiWiki, I can tell you that at 20nm the Variation Designer Platform is a critical part of the emerging 20nm design methodology. You can read more on Solido’s SemiWiki landing page HERE. It is well worth the click.

With technology rapidly going mobile, demand is driving IC development to high-integration, higher-performance at lowest power, a competitive cost, and still in time to meet market demands. In creating these SoCs at the leading edge, process nodes increased variability is a serious risk. Solido is THE leading solution provider to derisk variation, providing maximum yield at the performance edge, with specific solutions for memory, standard cell, low power and analog/RF design.


You can tell a lot about a company by their DAC content. For a relatively small company Solido is delivering a very big value proposition:

Solido Variation Designer Memory+ is used for memory design to achieve maximum yield on high-performance designs. Solido will demonstrate how Memory+ runs the billions of Monte Carlo samples needed for high-sigma (up to 6-sigma) verification of bit cells and sense amps, giving fast and accurate visibility into the increasing effects of variation on design in nanometer technologies. Using the industry-standard simulators commonly used in memory design to achieve SPICE-accurate results, Memory+ is fast enough for use in the design loop. Memory+ will be demonstrated both from the command line and from a graphical environment.

Solido Variation Designer Standard Cell+ delivers the highest-quality standard cell libraries in less time. Solido will demonstrate how Standard Cell+ optimizes a library of cells across the increasingly significant variation effects in nanometer technologies, allowing efficient migration of a standard cell library to a smaller process node or second source. Attendees will see how to leverage Solido’s meta-simulation technology to enhance standard SPICE simulation and manage performance-yield tradeoffs. Operating at the command line for full batch operation, Standard Cell+ is also used as an environment for design debug and results visualization.

Solido Variation Designer Low Power+. To minimize power in today’s portable devices, numerous power states in SoCs need to be considered and verified against thousands of corner cases. Solido will demonstrate how its Low Power+ uses Fast PVT meta-simulation technology, delivering a typical 2x-10x productivity gain in design verification coverage across power states, PVT corners, and layout RC corners. Attendees will see how Low Power+ actively finds and simulates only the worst-case corners while providing predictive results for non-worst-case conditions, giving full coverage at a fraction of the simulation cost.

Solido Variation Designer Analog+. Solido will demonstrate how its Analog+ product builds on the well-established Cadence® Virtuoso® Custom Design Platform to delivers simulation efficiency and design closure against worst-case PVT corners and extracted 3-sigma statistical corners. Analog+ delivers a 10x average efficiency increase for PVT signoff, more consistent Monte Carlo analysis with multiple stop-on-yield criteria, fast extraction of statistical corners at a target sigma, and efficient, intuitive, interactive design sizing. All capabilities provide extensive visualization and debug to assist in efficiently achieving high-yielding designs.

You can sign up for a Solido DAC meeting HERE. Send me a note and I will meet your there!

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Analog FastSPICE added to Tanner EDA

Analog FastSPICE added to Tanner EDA
by Daniel Payne on 05-24-2012 at 10:18 am
Categories: EDA, Tanner EDA
9 Comments

Last year when I visited Tanner EDA at DAC I heard about how they integrated the Analog FastSPICE circuit simulator from Berkeley DA.

This made sense to me because BDA has a good reputation for speeding up SPICE without compromising on accuracy, and Tanner users may want to mix and match tools from multiple EDA vendors.

This year they’ve taken that technical integration one step further by having an OEM agreement, where Tanner EDA sells and supports a version of the BDA Analog FastSPICE simulator.

As a Tanner EDA user there are a couple of SPICE simulation choices now:

  • T-SPICE
  • Analog FastSPICE

For small circuit sizes or short simulation runs the T-SPICE simulator should work out just fine however for larger circuit sizes or longer simulation runs then consider using Analog FastSPICE instead to get your simulation results quicker.

DAC
If you’re traveling to SFO in June for the DAC show then sign up for Tanner EDA at booth #1126to see demos on:

  • Analog design suite – now with support for Open Access
  • Analog FastSPICE
  • Layout generators
  • T-SPICE plus HDL simulation using Aldec Riviera PRO
  • Static Timing, Logic Synthesis, P&R
  • MEMS tools

My Futures
I know that you can simulate HDL plus T-SPICE today however I’d like to see:

  • A single waveform viewer instead of two
  • Co-simulation including Analog FastSPICE and HDL
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Network on Chip in Automotive: Arteris

Network on Chip in Automotive: Arteris
by Eric Esteve on 05-24-2012 at 9:20 am
Categories: Arm, Arteris, IP

The recent announcement from Arteris that iC-Logic chose FlexNoC and C2C to create a flexible and high speed communication chip to respond to the increasing demand of high speed connectivity in car infotainment systems is very interesting, as it shows that SoC designed for the Automotive market segment also require advanced IP functions which are widely used in the most advanced SoC, like application processor for smartphone or multimedia controller for Set-Top-Box. These chips from IC-Logic are supporting the infotainment segment in automotive, not the motor control, and will be used in the passenger cell, nevertheless, it’s significant to see complexes functions like NoC being used in the automotive segment, usually closer to the military or aeronautic segments than to the consumer electronic or wireless handset!

Let’s listen to the reasons why IC-Logic has selected Arteris FlexNoc and inter chip communication C2C IP: “iC-Logic licensed Arteris FlexNoC and C2C because we needed fast design cycle time and full compatibility with other SoCs. FlexNoC’s ease of use and integrated simulation and verification features helped us to optimize our SoC integration and development time,” said Martin Damrau, Managing Director at iC-Logic. “And our choice of the C2C chip to chip interconnect IP ensures our compatibility with application processors using C2C. Thanks to the collaboration with Arteris, iC-Logic added C2C integration expertise to our skill set enabling us to quickly design SoCs with this sophisticated interface.”

Just a remark: C2C is a technology initially developped by Texas Instruments… like OMAP is the flagship SoC family from TI, initially developed to support smartphone and media tablet applications.

If we look at first at C2C, and remember –or take a look at- the blog from Kurt Shulerabout the various high speed interface protocols currently used in the wireless handset (and smartphone) IP ecosystem, and cross this information with the above comment made by Martin Damrau, we realize that IC-Logic integrates C2C to ensure their chip compatibility with application processors using C2C. I have no insight information, but I would bet that this application processor could be OMAP platform from TI! If you replace the “cellular modem” chip by the chip designed by IC-Logic, that means that the system integrator could get the same benefit in automotive infotainment than in smartphone: share the same memory device between the application processor and the SoC designed by IC-Logic, and consequently save the cost of one memory devices.

Even if the production volumes in automotive are not the same than in wireless handset, these volumes are in the million units range, per year, and longevity is a lot longer: five to ten years to be compared with a dozen months. Using C2C can help to save several million of dollar during the product life. And, from a pure technical standpoint, C2C is a low latency (100 ns for a round trip), high bandwidth chip to chip connection link, allowing supporting gigabit per second range for data exchange based on standard parallel I/Os (LPDDR1 or 2) so you don’t need integrating (and acquiring the license of) SerDes based high speed PHY like MIPI M-PHY if you would use USB SSIC or MIPI LLI.

Using a chip to chip connection link to exchange data and benefiting from Bill Of Material (BOM) cost reduction makes sense, whichever the market segment your chip is serving. But I remember, back in 2006, not that long ago, that NoC was considered as a rocket science type of function, reserved for the most complexes SoC. In other words, only a few people understood how it worked! Seeing NoC being used in market segment like automotive, where the chip architect have to carefully select the function to be implemented, simply because the time to market is a lot longer than in consumer like segment, as well is the production period (five to ten years is common), is a strong sign about the democratization of the NoC. Which is very good for Arteris, and for existing Arteris’ customers, as this means that the technology is here to stay!

According with the Press Release from Arteris, iC-Logic chose FlexNoC and C2C to create a flexible and high speed communication chip to respond to the increasing demand of high speed connectivity in car infotainment systems. iC-Logic’s use of FlexNoC and C2C has helped reduce design schedules and increased the potential market for users of their SoC. “iC-Logic’s use of Arteris FlexNoC and C2C interconnect IP for its high speed communication SoC is an innovative way to reduce SoC time to market and grow the market size for application processor SoCs,” said K. Charles Janac, President and CEO of Arteris.

Eric Esteve from IPNEST

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After Planning Comes Implementation for Pulsic

After Planning Comes Implementation for Pulsic
by Paul McLellan on 05-24-2012 at 7:00 am
Categories: Uncategorized

Automation for digital design has been mainstream for a couple of decades but place and route for analog is still in its infancy. Many attempts have been made over the years to automate analog design in one way and another, the bodies are piled up on the hillside. Much analog design is still largely done with custom layout and circuit simulation. Analog design will probably never be automated in the same way as digital design, partially because analog designers have expertise that needs to get incorporated into the design, and partially because analog designs are often small enough that it is reasonably to partially hand-craft it, which is obviously not the case with a block of few million standard cells. But analog designs are getting larger and the process restrictions more complex meaning that a purely manual approach doesn’t scale.

Last year at DAC Pulsic announced the Pulsic Planning Solution. After planning comes implementation so this year at DAC Pulsic is announcing the Pulsic Implementation Solution providing designers with easy-to-use, guided flows to automatically implement precise, hand-crafted quality design layouts.

The products that make up the Pulsic implementation solution are the Unity Analog Router, the Unity Custom Digital Router and the Unity Custom Digital Placer. Pulsic’s customers have been running into the bottlenecks of analog and custom digital design. Throwing more engineers at the problem is not a solution, and using regular digital place and route isn’t able to handle the delicate issues in custom digital and analog design that require shielding, matching two halves of the design and so forth.

The constraint drive shape-based routing technology, based on over 200 man-years of experience in analog routing has led to a flow focused on the specific needs of analog designers to create precision routes at hand-crafted quality. The weakness of many analog solutions is that creating the constraints to drive the tools is an enormous task that doesn’t really scale any better than handcrafting the design. But proprietary geometry recognition algorithms mean that minimal set up and tool knowledge is required. There is full support for features such as mirrors, symmetry, common centroid and current density limits. The designer retains full control and can use the router interactively or automatically.

Under the hood, there is a tightly integrated suite of shape-based routing technologies. The router encompasses hundreds of specialized utilities that work together simply on the same shape-based data model to give custom digital design teams precise, handcrafted quality results with automated speed. It has been engineered to work with the latest complex process rules (28nm and below) and makes efficient use of available area, even for areas with extreme aspect ratios or high congestion.
More details are here.



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Software-based Wi-Fi: DSP IP core

Software-based Wi-Fi: DSP IP core
by Eric Esteve on 05-23-2012 at 10:05 am
Categories: Ceva, IP

The recent announcement from CEVA that it has joined the Wi-Fi Alliance® to further advocate for a software-based Wi-Fi® strategy shows that the new CEVA-XC4000 DSP can be used in various communication protocols, not limited to the traditional baseband processing for the wireless handset phone, where DSP IP core usage is massive. This follows on from the company’s recent announcement of a new software-based, reference architecture targeting multi-mode Wi-Fi 802.11 mobile stations (STA) and access points (AP) together with partner Antcor, S.A. CEVA’s Wi-Fi reference architecture is based on the new CEVA-XC4000 DSP architecture framework and is ideal for cost-efficient, ultra-low power applications.

If you look at the various challenges that chip makers are facing today in the market segments exhibiting the higher growth, wireless handset or media tablet for example, you realize that time-to-market is probably the most crucial. These segments are consumer oriented, the end user behavior relatively to a new product can have a stronger than ever impact on companies turnover and generate a new deal, just look at what has happened to respected OEM like Nokia or RIM within a couple of years only, simply because they did not properly “smell” their customers behavior, and have been a little too slow to react… In this environment, being able to reduce development time and minimize risk by choosing software based solution whenever it’s possible from a technical standpoint, preserving a great user experience, should be the best approach for a chip maker who need to launch a new product as fast as possible.

“The advent of the next generation of Wi-Fi standards including 802.11ac poses new challenges for the development of multi-standard, high performance Wi-Fi enabled SoCs,” said Eran Briman, vice president of marketing at CEVA. “The continuous evolvement of these standards together with greater processing requirements dictates a new silicon design approach that will enable semiconductor companies to reduce development time, minimize risk and also extend product’s life-cycle. CEVA believes that a software-based Wi-Fi approach based on the CEVA-XC4000 DSP architecture framework is the optimal way to address both the performance and flexibility issues with current hardwired designs and we look forward to sharing our expertise in this area with the Wi-Fi Alliance and its members.”
Reference architectures highlights:

  • Addresses both PHY and Lower-MAC with minimal complementary hardware acceleration
  • Built around a single CEVA-XC4210 processor with minimal complementary hardware accelerators
  • Offers industry’s most competitive SDR platform in terms of both cost and power consumption
  • Supports up to full 160MHz channel bandwidth
  • Maximal throughput of 867Mbps (scalable to 1.7Gbps) with up to 4×2 MIMO beam-forming, with 256-QAM support
  • Extremely low power solution targeting low power process for mobile Wi-Fi stations (STA)
  • High operating margins enabling customer differentiation by software

“We congratulate CEVA, Inc. on becoming a member of Wi-Fi Alliance,” said Edgar Figueroa, CEO of Wi-Fi Alliance. “By joining our organization, CEVA has demonstrated its commitment to advancing Wi-Fi technology while preserving a great user experience.”

The CEVA-XC4000is a fully programmable low-power DSP architecture framework supporting the most demanding communication standards including LTE-Advanced, LTE and HSPA+, alongside Wi-Fi, DTV demodulation, white space, smart grid and more. The CEVA-XC4000 architecture is offered in a series of six fully programmable DSP cores, offering modem developers a wide spectrum of performance capabilities while complying with the most stringent power constraints. Built around the highly successful CEVA-XC DSP architecture with more than 15 design wins to date, the CEVA-XC4000 delivers up to a 5X performance improvement for the most demanding communication standards over previous CEVA-XC DSPs, while consuming 50% less power.

Eric Esteve from IPNEST –

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Beyond 28nm: New Frontiers and Innovations in Design For Manufacturability at the Limits of the Scaling Roadmap

Beyond 28nm: New Frontiers and Innovations in Design For Manufacturability at the Limits of the Scaling Roadmap
by Daniel Nenni on 05-22-2012 at 9:00 pm
Categories: Foundries, GlobalFoundries

The introduction of 28nm high-volume production for IC semiconductor devices will usher the era of “extreme low-k1” manufacturing, i.e. the unprecedented situation in the long history of the silicon technology roadmap, where computationally intensive (and EDA-driven) Design-Technology Co-Optimization will become the key enabler to a product success in terms of yield, time-to-market and profitability.

This talk will provide a review and technical analysis of the methodological innovations in Design Enablement flows which are being introduced for early production at 28nm, particularly advanced DFM physical verification and DFM-aware router implementations. Rule-based, model-based and the newly released pattern-matching based hybrid verification, pioneered, industry-first, at GLOBALFOUNDRIES are prominent examples of these new enablement flows.

DFM methodologies are complemented by a set of novel foundry-based flows identified as Design-Enabled Manufacturing (DEM). While DFM provides process awareness into the design cycle through accurately calibrated models and verification flows (DFM sign-off), DEM enables manufacturing/design co-optimization, using automated physical design analysis and characterization, which in turn drive process optimization, fine-tuned to specific customer product designs.

The presentation will conclude with a preview of the “variability-challenge” intrinsic in the 20nm node and with an anticipation of the innovative EDA solutions which are currently being developed in the new Foundry-supported collaborative eco-system.

Luigi is a very engaging speaker on the leading edge of process technology, you definitely do not want to miss this one. See you there……

Register for this and other GLOBALFOUNDRIES Technical seminars @ DAC 2012 HERE.

BIOGRAPHY: Luigi Capodieci, Ph.D.
Director DFM/CAD – R&D Fellow – GLOBALFOUNDRIES

Dr. Luigi Capodieci has been working on lithographic imaging and process simulations for more than 15 years, with applications to Optical Proximity Correction, Phase Shift Masks, Resolution Enhancement Technology and Design/Process Co-Optimization.

At Advanced Micro Devices, in California, he pioneered the field of Design For Manufacturability (DFM) integrating physical design CAD flows with rigorous layout printability process modeling and novel verification algorithms.

He is currently an Engineering R&D Fellow and the Director of DFM/CADat GLOBALFOUNDRIES (www.globalfoundries.com), coordinating DFM R&D from 45 and 32/28nm, down to the next generations of 20 and 14nm technology nodes.

Dr. Capodieci holds a Doctor degree in Electronic Engineering and Computer Science from the University of Bologna, Italy and a Ph.D. in Electrical Engineering, from the University of Wisconsin-Madison, where he worked at the Center for Nanotechnology (CNTech, formerly Center for X-Ray Lithography).

Dr. Capodieci has authored and co-authored more than 35 journal and conference technical publications and is the principal inventor or co-inventor in more than 30 U.S. Patents. He is also an active member of the IEEE and ACM technical organizations.