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GLOBALFOUNDRIES 28nm Design Ecosystem!

GLOBALFOUNDRIES 28nm Design Ecosystem!
by Daniel Nenni on 06-01-2011 at 11:00 am
Categories: Arm, EDA, Foundries, GlobalFoundries

GLOBALFOUNDRIES will show off its 28nm design ecosystem at #48DAC next week in San Diego. The company will feature a full design ecosystem for its 28nm High-k Metal Gate (HKMG) technology, including silicon-validated flows, process design kits (PDKs), design-for-manufacturing (DFM), and intellectual property (IP) in partnership with industry leaders. 28nm is the second node of HKMG production for GFI with 32nm AMD Llano dice already in the field. CPU’s and GPU’s are the most difficult designs to manufacture and Llano is both.

“We have been in production of real HKMG products for months,” said Mojy Chian, senior vice president of design enablement at GLOBALFOUNDRIES. “We have been leveraging this experience by collaborating with ecosystem partners to build this knowledge into the design infrastructure and tools we provide to customers at 28nm. This focus on early design-technology co-optimization and silicon validation will translate to accelerated time-to-market for the next generation of power-sensitive consumer electronics and mobile devices.”

Top Ten Reasons
Why You Should Visit GLOBALFOUNDRIES at DAC

Okay, 10 is a little much so here are my:

Top Three Reasons
Why You Should Visit GLOBALFOUNDRIES at DAC

[LIST=1]

  • Processor Cores (ARM)
  • 28nm SLP
  • Foundation IP (ARM) and DRC+

    Per Eric Esteve’s article on ARM and GlobalFoundries: a key relationship in the future:Although there has been always a strong relationship between ARM and GlobalFoundries, it is interesting to notice that Intel has helped to boost it and make it even stronger.……

    The mobile internet craze continues to drive semiconductor growth and who owns the heart and soul of mobile internet? That would be ARM. Bundle that with a Gate-First HKMG low power process (longest battery life), high yielding foundation IP, and the hottest DFM program (DRC+) and you get a superior price/performance/power mobile platform. Just my opinion of course.

    Will ARM processors continue to dominate the mobile internet craze? In a keynote address at Computex in Taiwan, ARM President Tudor Brown said, “Today we have about 10 percent market share [in mobile PCs]. By the end of 2011 we believe we will have about 15 percent of that market share as tablets grow. By 2015, we expect that to be over 50 percent of the mobile PC market.” If I was a gambler, which I am, I would not bet against ARM on this one.

    Don’t forget to share this on LinkedIn:

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    ARM vs Intel step 2…Intel’s nervous breakdown about Microsoft… and cut ATOM price

    ARM vs Intel step 2…Intel’s nervous breakdown about Microsoft… and cut ATOM price
    by Eric Esteve on 06-01-2011 at 8:52 am
    Categories: Uncategorized
    1 Comment

    In the unspoken war between ARM and Intel, a couple of interesting facts have surfaced during the last few days:

    • Intel nervous breakdown in respect with their 30 years old accomplice in the Wintel gang
    • ATOM latest version Cedar Trail fabbed on 32nm technology, targeted for mobile computing, will be priced at a 30% to 50% discount… should we thank ARM for this price drop?

    Let’s have a look at the facts before to give our thoughts about these “strategic” moves from Intel. At its analyst meeting on Tuesday, Intel chief executive Paul Otellini talked about Windows 8 porting on ARM processor core:“I believe that Intel is still the only architecture at the chip level whose silicon runs every major operating system out there,” Otellini said during the analyst meeting. “And you all know the story on this – the ARM guys are getting a port to Windows. But what the ARM guys are getting are four ports to Windows. Every operating system has to write to the chip and with the writing at Microsoft’s doing is doing four versions for ARM vendors, just like Android writes to multiple versions of the ARM chips, and to Intel, now.” The “four ports” were assumed to be four separate versions of the OS, which Microsoft denied.“Intel’s statements during its Intel Investor Meeting about Microsoft’s plans for the next version of Windows were factually inaccurate and unfortunately misleading,” Microsoft said in a statement. It look like the first crack which may cause a rift in the 30 years old friendship…

    Price drop: Intel had also announced a strategy shift toward developing ultra mobile chips, while later showing off Atom-based phones, tablets, and some cool new PC technologies.

    When INTEL launches Cedar Trail, the latest version of the Atom-processor fabbed on 32nm process technology, we can expect to see the cost drop between 30% and 50% according to several netbook manufacturers in Taiwan that SemiAccurate has spoken with. The manufacturers prefer to remain anonymous since they are not officially allowed to discuss pricing on an unreleased product.

    Intel will launch 2 different versions of Cedar Trail. One for netbooks and one for nettops. The mobile versions will be named N2600 and N2800. The Atom N2600 will be priced at $42 and N2800 at $47.

    According to one analyst who queried Otellini at the analyst day, with Windows on ARM, that spiral would then shift over to ARM and its licensees. And that would supposedly take a deep bite into Intel’s profit margin. Otellini, however, dismissed the claim. First off, he said, Intel was “very competitively priced with ARM-based products,” at least where tablets and smartphones are concerned. (Intel announced yet another delay to its X86 smartphone program on Tuesday, pushing X86 phones back into 2012.) Arguments that Hewlett-Packard or other OEMs could somehow use ARM as a lever to differentiate themselves and design a cheaper but still profitable PC “don’t understand the way this business works,” Otellini said.”

    The outcome is clearly that Intel is nervous. Attacking Microsoft through their new partnership with ARM is not only unfair, it is also somehow stupid: it could be like sending a boomerang. Microsoft is just acting on the market like Intel, they both benefit from a monopoly position to sell for high price, high GPM (Gross Profit Margin), products which used to be innovative – in the past. Nevertheless, as a consumer, we should enjoy this nervous breakdown from Intel, when it comes to the ATOM price drop. The ARM vs Intel war starts to be positive, if it pushes Intel to lower the prices!

    When I say that Intel is no more innovative, I agree that I am slightly biased. But, as a matter of fact, Intel is still struggling to launch their X86 processor for smartphone, as the program has been further delayed, back into 2012. Intel, with revenue greater than GDP of Senegal, Paraguay and Cambodia aggregated (a 35 million population) and with a R&D budget greater than total R&D spending of Sweden, is simply not able to catch up with the Qualcomm, STM, TI or Nvidia, and launch a competitive wireless application processor like OMAP5.

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    Eric Esteve

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    Sagantec 2 Migrate iPad2s @ #48DAC

    Sagantec 2 Migrate iPad2s @ #48DAC
    by admin on 05-30-2011 at 2:53 pm
    Categories: EDA

    Sagantec is the leading EDA provider of process migration solutions for custom IC design. Sagantec’s EDA solutions enable IC designers to leverage their investment in existing physical design IP and accomplish dramatic time and effort savings in the implementation of custom, analog, mixed-signal and memory circuits in advanced process technologies.

    These solutions have been used commercially by tier-1 semiconductor companies, and have been proven to reduce layout time and effort by factors of 3x to 20x and enable dramatically faster introduction of IC products in new technology nodes.

    Apple does not allow iPad2 “giveaways” so Sagantec will be “migrating” iPad2s to a select few conference goers that register for SemiWiki.com. If you are already registered for www.SemiWiki.com just stop by and check-in to qualify for the “migration”.

    Sagantec at DAC 2011

    Featuring the following presentations and demos:

    ·Custom, analog and mixed-signal IP migration
    ·Migration to latest technologies: 40, 32 and 28nm migration
    ·Automatic PDK update, design rule changes, and DRC correction
    ·Standard cell library migration and optimization

    ·Custom, analog mixed-signal IP migration

    Migration of custom IP to next process node or different foundry
    ·Supporting all process technologies
    ·Maintain and enforce geometric constraints like symmetry, matching, alignments, etc.
    ·Maintain original design hierarchy and structure
    ·Support Cadence Virtuoso® IC5 and IC6 database
    ·Support Pcells and all other Virtuoso data objects
    Check out analog IP migration success story

    ·Migration to latest technologies (including 28nm)

    Sagantec migration technology has been used and proven down to 28nm
    ·Overcoming topology and device changes
    ·Overcoming new restrictive design rules
    ·Used an proven on multiple designs
    Check out new 28nm migration success story article

    ·PDK and design rule changes
    Adjusting layout to new PDK and design rule changes
    ·Swap between Pcells and PDKs
    ·Update new design rule values
    ·Automatic correction of DRC errors
    ·Implement recommended DFM rules without changing layout foot-print
    ·For custom, analog/ mixed-signal blocks and IP
    ·For large digital blocks and full chips
    Check out new PDK adjustment success story article

    ·Standard Cell Library Migration & Optimization

    Migrate, modify and optimize standard cell libraries in the most advanced technologies
    ·Migrate libraries to next technology node or between foundries
    ·Supports topology and routing changes (e.g. for 28nm and 22nm)
    ·Create new library derivatives (HS, LP, etc)
    ·Analyze and optimize libraries for yield


    Process migration Change #tracks

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    Going to DAC? There’s an app for that

    Going to DAC? There’s an app for that
    by Paul McLellan on 05-30-2011 at 1:51 pm
    Categories: General

    Are you going to DAC in San Diego? Do you have an iPhone? In which case Bill Deegan’s dac48 app is something you should install before you get there. It’s free, which makes a nice change from EDA software pricing.

    The app substitutes for the various paper, agendas and maps that you need to consult to find exhibitors, check up when sessions are and put them on your calendar. It’s not perfect (he ran out of time); for instance the booth numbers are not linked on the exhibitor map.

    And yes, it’s only on iPhone so far, Android probably has to wait until DAC49.

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    New TSMC 28nm Design Ecosystem!

    New TSMC 28nm Design Ecosystem!
    by Daniel Nenni on 05-28-2011 at 9:23 pm
    Categories: EDA, Foundries, TSMC

    TSMC rolled out the new reference flows for 28nm design as part of the Open Innovation Platform. The biggest surprise (to me) is that Cadence is STILL in the TSMC reference flows!

    The updated TSMC OIP wiki is here, the Reference Flow 12.0 wiki can be found here, the AMS 2.0 reference flow wiki is here, and the official TSMC PR is here. The latest slides are included in the wikis for your viewing pleasure. TSMC customers can download the official materials at TSMC Online.

    “TSMC customers can immediately take advantage of our 28nm advanced technology and manufacturing capacity while preparing for 20nm in the near future,” said Cliff Hou, TSMC Senior Director, Design and Technology Platform. “We have enabled customers to achieve their product design goals by closely collaborating with our EDA and IP partners to deliver a solid 28nm design ecosystem. In addition, the introduction of Reference Flow 12.0 and AMS Reference Flow 2.0 address critical design issues for the next generation of 28nm and 20nm applications.”

    This announcement is a big fat hairy deal for several reasons:

    [LIST=1]

  • Cadence is still partners with TSMC
  • 2.5D design
  • Emerging companies dominate
  • 28nm Power, Performance and DFM Design Enablement

    While Cadence executives pledge their allegiance to the open TSMC iPDK standard, Cadence product people continue to release INCOMPATIBLE products. The upcoming release of Virtuso GXL 6.1.5 (the high end version) will NOT allow a non SKILL based PDK to run (core dumps). My guess is that Virtuoso XL and L versions will soon follow. How will Cadence get away with this travesty? Big Cadence customers (80% of their revenue base) build their own PDK’s even if they use TSMC. Closed skill based PDK’s for Cadence customers versus open PDK’s for everyone else, great corporate strategy……. NOT! Cadence will be punished for this short sighted behavior by customers, it’s coming, believe it.

    TSMC will be the first fully 3D IC design capable foundry, no argument there. 2.5D design includes multiple dies to be integrated with a silicon interposer. Reference Flow 12.0 features new design capabilities in: floor planning, P&R, IR-drop, and thermal analysis to accommodate multiple nodes simultaneously. Also included is a new design for test methodology for 2.5D design.

    In addition to the “EDA Monopoly”, emerging companies continue to impregnate the TSMC reference flows:

    Apache, Arteris, AtopTech, Carbon Design System, CLK DA, Extreme DA, Sigrity, Sonics, SpringSoft, Berkeley DA, Ciranova, CST, EdXact SA, CWS, Helic, Integrand, Lorentz, and my personal favorite Solido DA. EDA innovation comes from emerging companies so TSMC is doing the semiconductor design ecosystem a big fat hairy favor here by putting new tools in silicon. NO OTHER FAB DOES THIS!

    Timing degradation from wire and via resistance, power leakage, hotspot checking and fixing are also addressed in the reference flows. Smaller geometries bring bigger problems, believe it.

    TSMC has a monster booth at DAC with a partner pavilion. The TSMC DAC page is herewith:

    In case you don’t follow my Twittering @DanielNenni: TSMC and UMC will be back at 95% utilization in Q3 due to surging orders from the mobile internet craze. Most of which include ARM processors @ 40nm bearing the names: Snapdragon for Qualcomm, Tegra2 for NVIDIA, Armada for Marvell, and i.MX for Freescale at TSMC and OMAP4 for Texas Instruments at UMC. TSMC also has 100+ tape-outs coming in at 28nm so don’t expect excess fab capacity anytime soon.

    Taiwan was absolutely crazy this month. The drought continues, the streets of Hsinchu were packed with scooters, and at2pmon Wednesday there was a bombing drill. For 30 minutes we were required to stay inside while the streets were cleared. This has been going on for years and it reminded me of elementary school where we hid from atomic bombs (cold war) under our desks.

    Don’t forget to share this on LinkedIn:

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    65nm to 45nm SerDes IP Migration Success Story

    65nm to 45nm SerDes IP Migration Success Story
    by Daniel Nenni on 05-25-2011 at 3:43 pm
    Categories: Uncategorized
    4 Comments

    The problem:To move a single lane variable data rate SerDes (serializer-deserializer) from a 65nm process to a 45nm process, achieving a maximum performance of up to 10.3 Gbps. This is a large piece of complex mixed-signal IP with handcrafted analog circuits. Circuit performance and robustness are critical and must be maintained in the migrated implementation.

    The original design consisted of over 30 blocks with a hierarchical device count of around 30,000 (about 200,000 flat).

    After the first migration, business opportunities arose requiring the same SerDes IP to be moved to two further different 40nm processes.

    Design Environment: 65nm Serdes has been designed in Cadence Virtuoso XL, using the 65nm foundry provided PDK (technology files, pcells, etc). Target 45nm migrated result should be restored into a Cadence Virtuoso XL database environment using the new target 45nm foundry provided PDK. All the Cadence database specific object need to be maintained (pcells, via cells, connectivity, etc.)

    The main changes : There were many changes in design rules between the two processes: Dummy poly insertion and pitching being the most challenging. In addition, all devices were resized and the new sizes needed to be gathered from the netlist (netlist-driven migration).

    A layout clip showing devices after automatic dummy poly insertion and gate gridding (enforcing strict poly pitch)

    The main requirements:

    • · The basic topology needed to be preserved.
    • · The design hierarchy needed to be preserved.
    • · Matching devices and routing should remain as such. Other topology sensitive features such as symmetry, alignment, etc, should be maintained.
    • · The migrated SerDes should be LVS clean. This includes both connectivity as well as matching the new schematic device sizes.
    • · The flow should allow quick sizing and ECO iterations
    • · The migrated SerDes should have minimal remaining DRC violations requiring manual fixup.
    • · Maintain data integrity: Virtuoso data structure and all objects kept intact

    The schedule: The productivity goal was set to at most 1/5 of original layout time. (minimum 80% effort and time savings) .

    Quick Initial Prototyping: One of the first goals was to figure out the effective scaling factor of the migrated IP. This is one of the clear benefits of automated migration which allows designers to try multiple scaling and sizing scenarios based on the target technology devices and rules. Many experiments can be done quickly and very early on, to figure out the effective scaling, footprint, effect on performance, and other consequences of each scaling and sizing scenario.

    How the migration was addressed: The entire Serdes IP comprises over 30 main blocks, each having up to 10 level of hierarchy and an average of 1000 devices (hierarchical count).To facilitate concurrent layout-circuit optimizations with quick turn-around time, a block-by-block execution method was chosen.While performing each block at a time, the migration flow also takes care of global (top) level metals and over-the-block supply rails to make sure that the blocks are properly positioned and connected within the top level. Most of the blocks are custom handcrafted using device level programmable cells (Pcells) of the original 65nm foundry PDK . These Pcells as well as other symbolic structures had to be mapped to and substituted by similar devices and structures from the target foundry 45nm process. The migration software uses this mapping to generate the new devices and objects using the right parameters, make room for each of their instances, place them and connect them in the migrated layout. A few blocks also used digital control sections that were implemented using a specific logic cell library shared among all the blocks. This common logic cell library was also migrated to the 45nm target process rules and maintained as a common library across the entire IP, and then used during the block-level migration.

    Device Sizing     : Final sizing for devices was not fully determined before starting the project. Initial sizing was done based on schematics and then was subsequently refined after layout extraction and circuit validation. This is where having an automated migration flow makes a huge difference as once the flow is in place, all subsequent sizing and tuning layout iteration are run very quickly ( in less than an hour). Using this block-by-block approach enabled having a virtual “assembly line” pipeline of blocks in different stages of migration and tuning and accelerated the overall project significantly.

    Results: The SerDes migration was delivered on-time. LVS was virtually clean (there were a few minor issues due to incompatibilities between the PDK libraries). DRC quality was better than expected, with most blocks having under 50 DRC violations left. In fact the project exceeded its initial productivity goals: each block takes only minutes to run, and the last few remaining DRC errors took only a few hours to clean up. The overall effort, including the manual layout cleanup, took less than 1/10 of the original layout time (90% effort and time savings).
    Automatic migration preserves symmetry and matching. Same clip before and after migration.

    65nm (green) versus 45nm (purple)

    Why Sagantec:The IP design team looked at different commercial solutions for Analog/MS migration and evaluated a few alternative offerings from multiple EDA vendors. While other vendors addressed some aspects of the problem, the customer found Sagantec as having the most complete solution and one that most effectively addresses the size, complexity and the overall layout effort productivity goals. Another significant factor was supporting and maintaining the Cadence Virtuoso database and objects which was important to the design team. Overall the Sagantec approach seemed the most practical and least disruptive to the team’s current design flow and tools.

    Consecutive Successes:     Following the success of this migration project, the IP design team decided to use the same flow to migrate this IP to two other 40nm processes (using different PDKs and technology files respectively). Each of these subsequent process migrations was also a success, completed on-schedule and exhibited similar productivity gains. Overall this migration methodology and flow enabled the team to respond quickly to new business opportunities and process requirements, leveraging their original design investment and minimizing their efforts per each process implementation.

    Custom IP migration: Moving a complex custom IP block from one process to a different process can either be done by an experienced layout team or using an automated flow that handles almost all of the work automatically, such as Sagantec’s migration technology. For migration to older process nodes or between similar processes, it is possible that a shrink followed by manual fix-up of violations would work, but in advanced process nodes and when the processes have very different rules, the number of violations generated can be overwhelming and impractical for such approach. The alternative would be a complete redesign, which in this case would be prohibitively expensive in both schedule and resources required. In addition to licensing migration software, Sagantec has also experienced application engineers that can do migrations as a service to minimize turn-around time, get the highest quality results and maximize ROI.

    Sagantec Demo Suite Registration

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    3D IC @ #48DAC

    3D IC @ #48DAC
    by Daniel Nenni on 05-23-2011 at 4:54 pm
    Categories: EDA, Events

    A three-dimensional integrated circuit (3D IC ) is a chip in which two or more layers of active electronic components are integrated both vertically and horizontally into a single circuit. The semiconductor industry is hotly pursuing this emerging technology in many different forms, as a result the full definition is still somewhat fluid.

    If you need to increase your system- and/or IC designs’ performance, while reducing power dissipation, space required and eventually cut NRE and unit cost, you want to update yourself at #48DAC on our industry’s progress regarding 3D ICs.

    3D Tour Guide for DAC 2011:
    To assist you in this effort, the GSA’s 3D IC Working Group compiled this year again the “Tour Guide to 3D-IC Design Tools and Services”. It includes 3D-centric information from 14 EDA vendors, 4 R&D centers and industry organizations, 3 market research firm and 1 value chain provider. This 3D Tour Guide can be downloaded here:

    If you want to know more about the 3D IC Working Group’s activities, you can download presentations given by 3D experts at recent meetings here:

    3D-focused DAC Event:
    On Monday morning, June 6, Herb Reiter will moderate a pavilion panel on the exhibit floor (Booth 3421) with the title : “3D IC: Myth or Miracle?”

    Riko Radojcic from Qualcomm, Ivo Bolsens from Xilinx and Suk Lee from TSMC will outline their view of 3D technology and answer questions from the audience.
    More about this panel here:

    At the end of this 3D panel the GSA will offer you – in exchange for your business card – a hard copy of the 3D Tour Guide with its 60+ pages of 3D information.

    Please join us on Monday morning, 10.30 am at Booth 3421. Utilize the 3D Tour Guide to direct you to Tools and Services for 3D IC design and manufacturing.

    Other 3D-focused events BEFORE the summer break:
    June 29 to July 1will be the “Design for 3D” conference in Grenoble, France.
    More about agenda, registration here.

    In addition to the IC-design focused events about, our industry’s manufacturing experts are also going to address 3D Technology in several workshops and on the exhibit floor at the upcoming Semicon West in San Francisco, from July 12 to 14. More here:

    If you want to join the GSA 3D IC Working Group and contribute to general 3D topics or specific efforts (3D test, data exchange formats, 2.5D, …) please contact Herb Reiter with a brief outline of your strengths and the topics you want to influence.

    Herb Reiter
    Chair of the GSA 3D IC Working Group
    herb@eda2asic.com

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    48th Annual Design Automation Conference

    48th Annual Design Automation Conference
    by Daniel Nenni on 05-23-2011 at 8:08 am
    Categories: EDA, Events

    The 48[SUP]th[/SUP] Design Automation Conference (DAC) is now upon us. DAC is billed as “the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions” for which I would have to agree with 100%.

    The first DAC I attended was in 1984, Albuquerque New Mexico, which was one of the first to allow exhibitors. It was an exciting time in semiconductor design, so much innovation, new technology everywhere, the Design Automation Conference is and has always been the cornerstone of EDA. This will be my 28[SUP]th[/SUP] DAC and certainly not my last since the Rapture didn’t get me, unless of course the world ends on October 21st.

    SemiWiki will be at DAC giving away iPad2s in booth #1432.Register for SemiWiki on an iPad2 at the booth and you qualify to win. Current SemiWiki members just check in and qualify to win.


    This year I was part of the DAC planning process and organized two pavilion panels which is what this blog is really about:

    The first panel is Hogan’s Heroes: The Reaggregation of Ecosystem Value

    Topic Area: Business
    Tuesday, June 7, 2011
    Time:11:00 AM—12:00 PM
    Location:Booth #3421

    Summary:The semiconductor ecosystem shifts its value aggregation on somewhat predictable cycles. These are followed by longer periods of stability during which new companies are created. The latest cycle is being driven by system houses. What impact will these new trends in system design have on EDA and IP business models and enterprise value?

    Organizer:Daniel Nenni – SemiWiki, Danville, CA
    Moderator:Jim Hogan – Tela Innovation, Inc.,Campbell,CA
    Speakers:Ajoy K. Bose – Atrenta, Inc., San Jose, CA Jack Harding – eSilicon Corp., Sunnyvale, CA Grant A. Pierce – Sonics, Inc., Milpitas, CA

    The second panel isWhy the Delay in Analog PDK?

    Topic Area:     Analog/Mixed-Signal/RF Design
    Wednesday, June 8, 2011
    Time:10:30 AM — 11:15 AM
    Location:Booth #3421

    Organizer:     Daniel Nenni – SemiWiki, Danville, CA
    Moderator:Steven Klass – SMSC,Phoenix,AZ
    Speakers:Mass Sivilotti – Tanner EDA, Monrovia, CA, Tom Quan – Taiwan Semiconductor Manufacturing Co., Ltd., San Jose, CA Ofer Tamir – TowerJazz, Newport Beach, CA

    Summary:    Why does it take so long for foundries to release analog/mixed-signal process design kits (PDKs)? The amount of AMS content in your designs is growing, and the pressure to move to smaller process nodes is increasing. This is your chance to talk to the people who develop your PDKs and reference flows!

    Tom is a natural in front of the camera, he did it in one take! This is must see TV!

    As for me, if we haven’t met please introduce yourself and feel free to buy me a drink. If we already know each other just buy me a drink. This DAC I will be blogging for beverages! Don’t forget to click the LinkedIn share button below in support of the 48th Design Automation Conference. See you in San Diego!


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    FPGA Prototypes Made Easy

    FPGA Prototypes Made Easy
    by Paul McLellan on 05-23-2011 at 5:00 am
    Categories: Uncategorized
    2 Comments

    FPGA-based prototype boards are a fast, cost-effective platform for SoC system validation but they are notoriously difficult to set up and to debug. There is a big upside, however, allowing early software integration and testing and thus finding bugs in both the software and the SoC earlier. This approach is much cheaper than commercial emulators. However, problems of debug visibility and the need for repeated slow FPGA compiles limits their use to late in the design cycle.

    The basic problem is that you need to decide in advance which signals to monitor, and add code to the RTL to bring those signals out. Of course, they always turn out to be the wrong set of signals, but to make a change requires adding the new signals and recompiling the whole FPGA. The number of pins available also restricts how many signals can be probed.

    What you would really like is to be able to have thousands of signals probed, and be able to change your mind to add new probes without requiring a complete recompile of the FPGA which can take hours.


    Protolink proble visualizer is a mixture of hardware and some clever software that gives just this capability. The way it works is that the RTL for the design is augmented with a bit of code before compilation (there is an overhead of a few percent for this). After compilation, the detailed routing of the FPGA is analyzed, the dummy module is replaced with the actual gates required for Protolink and then the verification can be run with the ProtoLink interface card attached to the prototype board. If an additional signal needs to be probed then small adjustments to the FPGA are all that are required.

    The traditional approach gives the capability to monitor tens of signals for a limited number of cycles, and with the time required to add a new signal measured in hours or even days. With Prove Visuallizer it is possible to monitor thousands of signals for millions of cycles, and adding a new signal to probe is a matter of minutes.

    The whole system is interfaced through Verdi, giving a common user-interface for simulation, FPGA prototyping and conventional in-circuit emulation. Verdi’s advanced visualization, tracing and analysis all operate to produce an extremely productive test and debug environment.

    Probe Visuallizer backgrounder

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    Analyzing and Planning Electro-static Discharge (ESD) Protection

    Analyzing and Planning Electro-static Discharge (ESD) Protection
    by Paul McLellan on 05-23-2011 at 5:00 am
    Categories: Ansys, Inc., EDA

    ESD has historically been a big problem analyzed with ad-hoc approaches. As explained earlier, this is no longer an adequate way to plan nor signoff ESD protection.

    Pathfinder is the first full-chip comprehensive ESD planning and verification solution. It is targeted to address limitations in today’s methodologies. Using a full-chip modeling approach, it can verify that a design meets ESD guidelines and identify vulnerable areas of the design. It can report if current density exceeds limits for wires and vias. It works for both digital and analog circuits.

    There are three different types of analysis.

    [LIST=1]

  • First, human body model (HBM) and machine model (MM) checks. These are the ESD problems that can result from either humans touching the pins or during manufacturing test and assembly. Pathfinder will check to ensure than if ESD voltage occurs between any two pins (or bumps) then it will traverse one or more clamp cells placed between those pins. First the loop resistance through each clamp cell is estimated. If the resistance is too high then that clamp cell is ignored and only any remaining cells (if any) for that path are considered. Checks are performed to ensure that the ESD protection is sufficient between each pair of pins.
  • Charged device model (CDM) checks. This is check for build up in logic, package capacitors and other circuits such as memories that need to have low resistance discharge paths.
  • Current density checks. This involve estimating the current density in wires following the injection of current into any pin pair. It calculates the current through the wires and vias and highlights any which fail the current density limits (as defined by the process guidelines).

    Following this analysis, extensive information can be created to enable debugging: reports, histograms and graphical displays overlaid onto the layout. This makes it easy to perform what-if experiments without leaving the tool. Once any changes are confirmed, an ECO report is created to allow for implementation of those changes in the final layout of the chip.

    Pathfinder is used in two different ways. Early in the design it can be used for ESD planning, especially on bumped chips which need to contain extensive ESD protection circuitry in the core and not just in an IO ring. If this is not done, and ESD protection circuitry is only added very late in the design process, it risks causing unexpected area (and perhaps timing) problems and thus potentially major schedule impact. The second way is to analyze the final design to signoff on the ESD protection prior to tapeout.

    Pathfinder white paper