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Fast buses at DAC

Fast buses at DAC
by Paul McLellan on 04-24-2012 at 10:05 pm
Categories: EDA, Events

UPDATE: there is free WiFi on all buses.

OK, these are not the 128 bit 1GHz buses we have to hear about every day. They go roughly 40 miles in roughly an hour. But they take you from Silicon Valley to DAC and back, and they are cheaper than BART or Caltrain.

For the first time this year, DAC has buses from Silicon Valley to Moscone for DAC. They depart from the Cadence parking lot at 2655 Seely Avenue (where you can leave your car all day even if you are not a Cadence employee). The buses run Monday through Wednesday.

Into San Francisco there are buses at:

  • 7.30am
  • 8.00am
  • 8.30am.

Return buses are at:

  • 6.15pm
  • 6.45pm
  • 7.15pm.

I am trying to find out if there is WiFi on the buses. Or maybe Google and co already have all the WiFi enabled buses for their daily fleet of Gbuses that trawl from San Francisco to Mountain View and vice-versa.

You can’t just show up to get on the bus. You need to attach a bus ticket to your DAC registration. If you are already registered then use the link in your confirmation email. If you are about to register, then don’t forget to add the bus before you check out.

Full details and registration links are here.

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Audio, not your father’s MP3

Audio, not your father’s MP3
by Paul McLellan on 04-24-2012 at 9:26 pm
Categories: Uncategorized

Chris Rowen, Tensilica’s CTO, presented in Santa Cruz at the Globalpress briefing. He was basically presenting Tensilica’s audio strategy, which I’ve written about before. But he provided an interesting perspective. Globalpress (which flies journalists in from all over the world and then fills the few remaining empty seats with a few of us local guys) has been going ten years.

Ten years ago, Globalpress was, in the audio processing area:

  • talking about 0.13um (or 130nm).
  • the first mp3 player, the Rio, was just 3 years old.
  • iPod was out…just…not even for a year. The one with a mechanical touch-wheel.
  • VHS would outsell DVD for another couple of years.
  • First cell-phone with a built-in camera released in US (by Samsung) with VGA resolution (OK, that’s not audio).

And Tensilica had not introduced an audio core. But one year later, 9 years ago, they had. Now it is accepted wisdom that audio processing on a general purpose processor (i.e. ARM) is silly. You should offload it onto a specialized core such as the Tensilica one (or the ARC-based Synopsys one that we also recently covered). I was at the Linley Tech Mobile Conference (nee Microprocessor forum) and a Tensilica demo by the Wolfson Microelectronics (yeah, Edinburgh, one of my alma maters) showed it dramatically. The ARM would sleep for over 9 seconds and wake up for less than a second to feed a Tensilica core with data and then go to sleep. I forget the precise power reduction (there were ammeters and oscilloscopes to keep everyone honest) but it was dramatic.

The problem is that voice requirements are going up faster than Moore’s Law (or More that Moore as we are learning to say). Basic voice runs at 200MHz today but will go up to 600MHz in 2-3 years. And those power budgets, not so much.

We are looking forward to much higher sound performance, especially on the voice receiving side:

  • active noise control (knocking out ambient noise with its inverse)
  • beam forming microphone arrays
  • always-on voice recognition

The point of Chris’s story wasn’t so much that voice is different, but it is a pioneer going where all the other technologies: video, radio processing (bluetooth, wireless, LTE etc), camera image processing and so on are going. And it is exploding…


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Smart mobile SoCs: Texas Instruments

Smart mobile SoCs: Texas Instruments
by Don Dingee on 04-24-2012 at 9:00 pm
Categories: Arm, Arteris, Imagination Technologies, IP
12 Comments

TI has parlayed its heritage in digital signal processing and long-term relationships with mobile device makers into a leadership position in mobile SoCs. They boast a relatively huge portfolio of design wins thanks to being the launch platform for Android 4.0. On the horizon, the next generation OMAP 5 could change the entire mobile industry. Continue reading “Smart mobile SoCs: Texas Instruments”

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Broadcom announces an HFC

Broadcom announces an HFC
by Paul McLellan on 04-24-2012 at 8:00 pm
Categories: IP, TSMC

For a long time Cisco had a very high end product whose official internal name during its years of development was HFR, which stood for Huge F***ing Router (the marketing department insisted it stood for ‘fast’). Eventually it got given a product number, CRS-1, but not before I’d read an article about it in the Economist under its old name. Wikipedia is on it. I was at the Globalpress briefing in Santa Cruz today and Broadcom announced their next generation network processor, definitely a chip deserving of the HFC appellation.

Unless you are a carrier equipment manufacturer such as Alcatel-Lucent, Ericsson or Huawei then the precise details of the chip aren’t all that absorbing. If you are, it’s called the BCM88030.

What I think is most interesting is the scale of the chip. It’s an amazing example of just what can be crammed onto a 28nm chip. Not just in size, but also in performance and power (or lack of it).

Firstly, this chip is a 100Gbps full-duplex network processor. This means it handles 300M packets/second, or a packet in approximately 3ns. Since its clock rate is 1GHz, that means in the time to execute 3 instructions so the only way this is workable is through parallelism. Indeed the chip contains 64 custom processors. Even that is not enough, each processor can handle up to 32 packets at a time, by advanced hardware multi-threading. Even that is not enough, some specialized functions just aren’t suited to general microprocessors and are offloaded to one of 7 specialized engines that perform functions like lookup (MAC addresses, IP addresses etc), police funtions, timing. All this while reducing power and area compared to previous generation solutions by 80%.

That’s just the digital dimension. The chip also contains the interfaces to the outside world with 24 10Gb/s Ethernet MACs, 6 50Gb/s Ethernet MACs and 2 100Gb/s Ethernet MACs.

What is driving the need for this amount of bandwidth is that carriers are switching completely to using Ethernet as their internal backbone between the different parts of their networks, from the base-station to the access network, to the aggregation network and in the core. This extremely high performance chip is targeted at aggregation and the core.

In turn this is driven by 3 main things:

  • millions of smartphones and tablet computers
  • upgrade of networks from 3G to 4G with increased bandwidth
  • increasing use of video

These are causing an explosion in mobile backhaul, the (mostly) wired network that hooks up all the base-stations into the carriers network and to the core backbone of the internet.

The growth is quite significant. A smartphone generates 24X the data of a regular phone (I’m not sure if the includes the voice part, although in terms of bits per second that is quite low with a modern vocoder). Tablets generate 5X the data of a smartphone (and so 120X a regular phone). And the number of units is going up fast. By 2015 it is predicted that the number of connected devices will be 2X the world population. As for that video, by 2015 one million minutes of video will cross the network each second. That’s a lot of cute kittens. In total, mobile data traffic is set to increase 18 fold between 2011 and 2015.

This is driving 100G Ethernet adoption, forecast to have 170% CAGR over the next 5 years. Hence Broadcom’s development of this chip. But, like any other system of this complexity, the chip development is accompanied by an equally challenging software development problem, to develop a tool chain and a complete reference implementation so that customers can actually use the chip.

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TSMC versus Intel at 20nm!

TSMC versus Intel at 20nm!
by Daniel Nenni on 04-24-2012 at 7:00 pm
Categories: Foundries, Intel Foundry, TSMC
10 Comments

The biggest news out of the TSMC Symposium last week was the 20nm update. Lots of debate and speculation, just why is TSMC releasing one version of 20nm (20nm SoC) versus multiple versions like in 40nm (LP, G, LPG) and 28nm (HP, HPM, HPL, LP)? Here are my thoughts, I would also be interested in your feedback in the comment section. This really is a big change for both TSMC and the foundry business so it is certainly worth discussing.

Morris Chang did a candid interview in early January discussing Intel as a competitor. Morris is a very clever man, a master at the card game bridge, so you can really read a lot into of what he has said here:

“TSMC’s technologies and performance have reached quite a high level, bringing us into contact with different rivals,” Chang said

The high level is volumes of mobile chips, volumes that will certainly rival Intel’s microprocessor business in the not too distant future.

“The competitors we face are Samsung Electronics Co. and GlobalFoundries Inc., with Intel standing ‘behind a veil’ because it is a rival against many of our customers,” Chang said, adding that these TSMC customers include integrated circuit designers and integrated device manufacturers.

The strategic positioning begins! TSMC is a pure-play foundry and collaborates with customers versus IDMs (Intel/Samsung) that competes with customers. The Apple/Samsung legal drama is a glaring example of this.

At the Symposium, Morris mentioned R&D expenses of TSMC versus Intel and Samsung, the difference being, TSMC collaborates with customers/partners and leverages R&D expenses. So the equation looks like this:

Top 10 TSMC customers R&D expenses + TSMC R&D expenses > Intel + Samsung R&D expenses

Another interesting quote from the article:

Samsung and GlobalFoundries are newcomers in the industry, Chang said, and suggested that TSMC’s customers should diversify their foundry sources rather than rely on TSMC only.

Which is interesting advice coming from the Chairman of TSMC. It is certainly a message to TSMC employees that second source competition is always a threat so even with 50%+ market share there is no time to rest on previous accomplishments. Notice he does not mention Intel here. Of course Morris followed that quote with something of purpose:

“All of our customers rely on TSMC in foundry production, and Intel relies on its own foundry plants,” he said. “If our technologies are not improved enough and Intel keeps improving its technologies, our customers’ products will lose competitiveness to those of Intel. It’s horrible to imagine the outcome.”

Another competitive shot at Intel! Well played Mr Chairman. I wish I could use a bridge analogy here but I don’t play bridge. Morris ended the interview with another shot at Intel:

“TSMC will stand behind our customers and cooperate with them. The battlefield between our customers and Intel is where we compete against Intel,” he added.

So it is the fabless companies, ARM, and TSMC against Intel. I like those odds!

Back to 20nm. Intel has one version of 22nm so to better compete with Intel TSMC will focus all resources on a single SoC optimized version of 20nm, simple as that. TSMC may also offer FinFets at 20nm so customers will have a choice between planar and FinFet transistor implementations, something that Intel does not offer. It is also about capacity. TSMC’s CAPEX hike is all about 20nm and with one S0C optimized version there won’t be the shortages we see at 28nm.

Sound reasonable? Please use the comment section for further analysis.

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Mergers and Acquisitions in EDA should spark Innovation and Start ups

Mergers and Acquisitions in EDA should spark Innovation and Start ups
by Rich Goldstein on 04-23-2012 at 8:13 pm
Categories: EDA
5 Comments

With the recent closure of the Synopsys Magma deal and the economy showing a bit of uptick and some positive outlook compared to the last 3-4 years, I believe it’s time for some of the creative minds that find themselves looking for new opportunity to consider starting their own point tool as well as IP companies.

Many of these people are some of the brightest in technology worldwide yet will discover some new realities of the current job market. The first is that openings in EDA and related areas such as IP are few and far between; the other being that the industries in the Valley that are growing and hiring rapidly don’t have the interest or intelligence to open their doors to veterans of areas besides their own. This is a grim reality of the new wave of mobile, cloud, SaaS, and enterprise companies that are garnering the funds from VC’s and hiring as if it were the boom all over again. I have experienced this myself more times than I can even count in the last year or so as Ive attempted to break new ground and transfer my skills in recruiting for software start ups into these areas, just to be ignored or often times told that they want the “7-10 year” candidates that are hungry and connected to people in their space and grew up using social media and mobile applications in their daily lives at least beginning in college if not sooner.

Intellectual Property (IP) is another avenue for the jobseeker to explore; perhaps a lower cost entrée into starting a smaller company that can realize success and notoriety sooner than building a software tool from the ground floor. There have been recent successes with design services companies that own their own IP and were able to be recognized as a business worthy of acquisition

I am not a technologist, I refer to myself as “buzzword compatible”, but I do understand as the geometries of the circuits get smaller and smaller there are new challenges that need to be addressed. Through the ups and down of the economies and the consolidations that have taken place, the fact still remains that innovation will come from smaller teams of people with an eye on invention as opposed to corporate security and politics. And these pioneers will in fact resurrect the cycle that we’ve all relied on over the years of growth via acquisition. There are private avenues of funding and friends of families and people who have tasted success that can be instrumental in helping these new entrepreneurs.
——————————————————————————————————————————————
Richard Goldstein has been a recruiter and advisor to startups in EDA and IP since 1984 and has placed many of the executives and leaders at startups within this industry. He has also held corporate contract recruiting positions inside companies such as Magma Design Automation, Kilopass Technology, and Xilinx.

Rich@dacsearch.com


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DAC 2012 Must-See! Hogan’s Heros: Learning from Apple

DAC 2012 Must-See! Hogan’s Heros: Learning from Apple
by Holly Stump on 04-23-2012 at 6:30 pm
Categories: EDA, Events


Who doesn’t love the perennial Hogan’s Heros panel at DAC? Always provocative and illuminating, for technologists, entrepreneurs, and strategists.

At DAC 2012, Jim Hogan’s panel is “Learning from Apple”:Apple. We admire their devices, worship their creators and praisetheir stock in our portfolios. Apple is synonymous with creative thinking, new opportunities, perseverance and wild success. Along the road, Apple set new technical and business standards. But how much has the electronics industry, in particular EDA, “where electronics begins,” learned from Apple? It depends.

Lets ask Jim…..What have we FAILED to learn from Apple?

1. Technology vs Customers?

It’s not about being leading edge technology. It’s about the user experience: display, power until charge, applications, and content: graphics/video. A relentless push for higher quality user experience – at minimum system cost. And feature convergence – video, voice, data, audio –in every consumer device.

Job’s Law: “Never compromise the user experience.”I know for the iPAD, Jobs had five guys working directly for him to seek out and understand how people used devices, to better spec the PAD and later projects.

They don’t do things right on the leading edge, but just behind it. They also then beat the living hell out of their supply chain for cost savings, and spend it on things that matter, like displays (check out the brilliant iPAD 3 display, and new power supply spec!)

2. Business and Pricing Models? Market Excitement / Charisma / Image?

Apple business model: give people a design that is useful and trendy and you can demand a premium.And Apple is well-branded. (In the old days, Apple even paid a guy in agarage to stamp an Apple logo on every DRAM…DRAM that no one ever even saw…that’s Apple!) We buy Apple because the darn things always work and are very reliable, the apps themselves work on your device and all other Apple devices. The Brand is King. They can slap an Apple on anything and sell it, i.e. iTunes.

The i4 repositioning is another good example. The price was lowered to $99 (through carriers) thus bringing the Apple experience to many people who had not yet bought. For the carriers, it attracted new subscribers consuming their data plans.

And, EDA needs to think more about adjacent markets. Apple is the number one distributor of music in the world (surpassing Wal-Mart last year.) Think about Siri and its possible evolution….

3. Managing Wall Street?

The best way to manage Wall St. is, show 25% top growth and 25% bottom line growth. Apple showed 100% top line in 2011 and 150% bottom line. Thus they are the most valuable on earth, surpassing Exxon in March. We are indeed in the information age and energy has moved down a notch.

Jim,who are your panelists for “Learning from Apple”?

We have Dr. Jan M. Rabaey, Professor at UC Berkeley, who is currently the scientific co-director of the Berkeley Wireless Research Center and serves on Technical Advisory Boards for a wide range of companies. Dr. Jack Guedj is President and CEO at Tensilica, Inc. He also ran Magnum Semiconductor, which he spun out of Cirrus Logic. Tom Collopy, CTO at Aggios, was VP of Engineering at Qualcomm responsible for the Smartphone/Smartbook market, including Snapdragon (Smartphones, Android.)

OK,Jim, we love Apple! How much is in YOUR portfolio?

(Laughter….)

Click for more information on Hogan’s Heros at DAC 2012

Jim Hogan, Private Investor
Jim is currently the managing partner of Vista Ventures, LLC. Jim has worked in the semiconductor design and manufacturing industry for more than 35 years gaining experience as a senior executive in electronic design automation, semiconductor intellectual property, semiconductor equipment, and fabrication companies. Mr. Hogan holds a B.A degree in mathematics, a B.S. degree in computer science and an M.B.A., all from San Jose State University. He serves on the Board of Advisors at San Jose State’s School of Engineering, and on several private companies’ boards of directors: Altos (acquired by Cadence May 2011), AutoESL (acquired by Xilinx February 2011), Scoperta, CLK, Tela Innovations and Shocking Technologies, Solido and Sonics. Additionally, Jim serves as a strategic advisor to several private and public technology companies.

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Channel Routing Memories

Channel Routing Memories
by Paul McLellan on 04-23-2012 at 1:12 pm
Categories: Uncategorized
3 Comments

Back in the early days of ASIC when we had just two and then (wow!) three layers of metal, place and route was done by putting the standard cells in rows with gaps between them and then using a specialized router to do the interconnection. It would use one layer of metal horizontally and one vertically and avoid jogs. This was called a channel router. For digital place and route today we have lots more layers of metal and we are not restricted to keeping our routing contained in the channel.

But memories are different. They have fewer layers of metal and end up with long narrow areas between the memory arrays and around the outside. Memories are also early into new processes and the first that have to deal with more restricted design rules. As a result, there is a need for routing this sort of area with long jogless nets, just like in the old days of 3-layer metal ASICs.

Normal digital place and route, or a shape-based router, does not give the right results, producing too many jogs, too many vias and is not controllable enough by the designer. But a straightforward implementation of a 1980s channel router isn’t adequate either. The connection points are inside the blocks, care needs to be taken feeding signals through the blocks. What is required is a smart way to create the pins that is aware of just how the channel router is going to behave. Otherwise it is too easy to create designs where one pin blocks another route (remember, we are avoiding jogs and vias). The router needs to drive the pin placement.

Pulsic’s spine and stitch router does this. The pin placement is driven by the router so that eventually everything can be routed with long straight wires. There is an example below, although, of course, a real example would likely involve thousands of nets. The spine router with pin placement can do in 30 minutes what used to take a designer doing it manually 3 weeks. Using intelligent pin sorting the router will typically complete over 95% of the nets leaving just a handful where the designer needs to guide the tradeoffs involved.


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AMS Design using Co-Simulation

AMS Design using Co-Simulation
by Daniel Payne on 04-23-2012 at 11:13 am
Categories: Aldec, EDA, Tanner EDA
1 Comment

The big three vendors in EDA offer AMS simulation tools but what about simulation choices from other EDA vendors?

It turns out there are two privately held EDA companies that have done business since the 1980’s and have just integrated a Verilog A simulator with a SPICE circuit simulator. The two companies are Aldec with a Verilog A simulator and Tanner EDA with a SPICE circuit simulator. To learn more about this AMS simulation capability I reviewed a webinar from March 8th, 2012.

Jeff Miller presented for Tanner EDA and Jerry Kaczynski for Aldec. Each company has over 30,000 EDA licenses in use worldwide.

The AMS tool flow starts with design capture in S-Edit then an automated netlist out to T-Spice AMS which uses Verilog A in Aldec’s Riveria PRO and SPICE in Tanner’s T-Spice:

Waveforms for analog signals are viewed in the Tanner viewer, while digital signals are viewed in the Aldec tool:

With Riviera-PRO the digital simulator features:

  • Verilog, VHDL, SystemVerilog, SystemC
  • Assertion-based verification
  • Command line or GUI operation
  • Code and functional coverage
  • Transaction-level debugging
  • APIs to communicate
  • Runs on Linux, Windows XP, Vista and Windows 7

This is a co-simulation approach, not a single kernel approach like that offered by Synopsys, Cadence and Mentor. For most AMS netlists the SPICE simulation will usually limit the run time.

The demo showed an ADC design where capture is done in Tanner’s S-Edit tool then netlisted. S-Edit automatically detects what block is netlisted for Spice and for Digital. T-Spice is run on the netlist which then invokes the digital simulator, Riviera-PRO.

Q&A
Q: Does the logic netlist run through the T-Spice input file buffer, causing capacity issues?
A: There isn’t a character limit to T-Spice parsing, so we don’t know of any capacity issues.

Q: Is it better to use a 64 or 32 bit OS for my AMS simulation?
A: It really depends on your memory requirements. For large memory requirements then you could run out of memory space on a 32 bit OS, so then use the 64 bit version on Linux or Windows for Riveria. On the SPICE side you can also use either 32 or 64 bit versions.

Q: Which OS versions are supported for this AMS co-simulation?
A: Windows 32 bit or 64 bit, Linux only 32 bit on the SPICE side.

Q: If I have a mixed signal design can I independently specify a Verilog and SPICE view without using two instance names?
A: Yes, you can specify per instance if this cell is Verilog or SPICE view.

Q: Does this co-simulation work with Active-HDL?
A: Use Riviera PRO for this AMS co-simulation for now. Active-HDL could be added in the future if there’s enough demand, it’s not a technical issue just a demand issue.

Summary
If you already own a Tanner EDA or Aldec simulator and want to start doing AMS simulation for IC designs then this affordable co-simulation approach should be considered. I’d expect to see in the product roadmap a few useful features like:

  • Unified waveform viewer, instead of two viewers
  • Cross-probing between schematic, source and wave form viewer
  • Interactive simulation where you can start, stop, measure and continue

The webinar is online here.

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UMC Wins Qualcomm 28nm Second Source Contract!

UMC Wins Qualcomm 28nm Second Source Contract!
by Daniel Nenni on 04-22-2012 at 7:00 pm
Categories: Uncategorized
11 Comments

This is common knowledge in Taiwan but apparently the guys over at SemiAccurate.com did not get the memo. I hear a name change is in the works: www.RarelyAccurate.com. Remember, these are the same clairvoyants who said TSMC shut down 28nm which as we now know is absolutely false. The QCOM elite stay at the Hsinchu Royal Hotel which is 5 minutes away from UMC HQ. The Royal is also my hangout so I see and hear these guys quite a bit.

TSMC absolutely did NOT halt 28nm production!

This article is titled “UMC Wins Qualcomm’s 28nm Node Contract” but what they mean is second source contract. We all know QCOM is at TSMC 28nm, as is everyone else. QCOM mostly uses the TSMC 28nm LP process for both low power and low cost. TSMC and UMC are the only foundries today with both a 28nm LP (poly/oxynitride) process and 28nm HLP (high k metal gate) processes. GlobalFoundries only has 28nm HLP, so sorry Charlie, QCOM will NOT be “moving majority of production to GlobalFoundries” anytime soon.

If you look through the UMC 2010 annual report you will see that UMC has a handful of customers that do the bulk of the business. Leading those is Texas Instruments. TI went fab-lite 5 years ago and chose TSMC for first source and UMC for second source. First tape-outs go through TSMC because TSMC is always first to market with a new node. Once UMC ramps production the fight for the best wafer price begins and that will go to UMC, which is why TSMC’s profit margins are 31% versus UMC’s 9%.

Does TSMC enjoy doing all of the bleeding edge work only to get shut out when serious production starts? Of course not, it is very frustrating but second sourcing is the nature of the fabless semiconductor business.

TSMC 28nm Yield Explained!

Qualcomm and Broadcom are different as they buy wafers from multiple fabs at 40nm and above: TSMC, UMC, SMIC, and GFI, because that is the way they do business. Other companies like Altera, Nvidia, and Oracle, single source at TSMC which is a much more intimate relationship but capacity can always bite you in the ass which at 28nm it certainly did.

One thing you have to understand is that the Fabless – Foundry relationship is hugely contractual. Fabless companies sign up for a certain wafer count in a defined time period and there are penalties on both sides if it is not met. To my knowledge, based on what I have read and heard at the Royal Hotel, TSMC has fulfilledALL contractual commitments on 28nm. Don’t believe me? Ask that question on the next QCOM or NVDA conference call. “Did TSMC meet the contracted wafer delivery numbers at 28nm thus far?”

The Truth of TSMC 28nm Yield!

What happens if the Fabless Company needs more wafers than in the contract? That is called a “Hot Lot” or a rush order which they pay a premium for, up to 50% I have heard. Correct me if you know otherwise.

20nm will be more of the same. The TSMC 20nm first customer list will be the same as 28nm plus maybe Apple. The same yield drama will ensue only to be debunked. Some will stay at TSMC 20nm, some will second and third source if they can. TSMC’s recent CAPEX increase is for 20nm capacity so the race is definitely on!