BannerforSemiWiki 800x100 (2)
Semiconductor Expert Forum

Posted on

Semiconductor IP Becomes A Critical Element in ASIC Design

Semiconductor IP Becomes A Critical Element in ASIC Design
by Daniel Nenni on 02-19-2012 at 4:05 pm
Categories: Uncategorized
2 Comments

Clearly one of the market trends proving troublesome in the traditional ASIC value chain is the lack of silicon correlated custom IP. And make no mistake, semiconductor IP is a critical decision since it drives both chip level and system level technology differentiation.

Under the traditional ASIC model, vendors had their own IP, silicon-proven and tuned to their own fabs. This was a good thing as it assured a fast ramp to volume and more predictable yield curves. The downside was that IP catalogs were somewhat limited which constrained product differentiation. And now a staggering 49 fabs were shut down in 2009-11 as traditional ASIC vendors and IDMs continue to go fabless.

Fortunately there is a new value chain model in play today that provides all of the silicon-proven IP benefits of the classic ASIC value chain model and provides a broader portfolio of in house-developed and third party IP. As a long time IP guy I can tell you that this is of great importance! The semiconductor ecosystem revolves around IP, it is the lifeblood of our industry!

The new model, now being promoted by Global Unichip Corporation (GUC), is called the Flexible ASIC Model[SUP]TM[/SUP]. It’s built on the premise that a company should not be constrained by its own assets such as manufacturing, IP, test or assembly, but rather should be able to focus on providing the most efficient design and the fastest time-to-market. This is a critical component that makes the Flexible ASIC Model work.

Make no mistake, while GUC provides streamlined and robust integration of third-party IP, it has not overlooked, and has in fact invested heavily in, its own IP development capability. As I blogged in Semiconductor IP Dilemma, four years ago GUC was an IP baron design services provider. Now GUC has a full lP portfolio with custom IP design groups in Taiwan, China, and Silicon Valley.
Much of GUC’s in-house developed IP covers SerDes, Data Converters and DDRs. The rationale for developing these particular blocks in-house is that these are the micros with the greatest demand and differentiation for the SoC ASIC marketplace, and I agree completely.

The main advantages of using in-house developed IP is the ability to know the precise effects of packaging and boards on the signal because the company has end-to-end supply chain capabilities and often end-to-end responsibilities.

By integrating IP development and implementation with package design, board design, and chip design, a Flexible ASIC Provider can simulate the complete system performance before sending the device to the manufacturing. The real key in this whole process is the capability to test for board effects and signal integrity then to be able to predict those impacts on the system and on the IP.

The secret to achieving superior performance, low power, and area balance lies in the hybrid analog/digital IP architecture that GUC uses to design its IP. This plus the access to advanced technology nodes, thanks to its very close working relationship with manufacturing partner TSMC, creates key differences that have proved critical to ASIC developers. Remember, GUC is directly across the street from TSMC Fab 12.

IP availability is absolutely becoming a critical differentiation and a much discussed option in the design community. Which raises the question of the day:

What are some of the hardest to find critical IP that you need to fit your current and future designs?


Posted on

Semiconductors: A Decade of Invention… A World of Solutions

Semiconductors: A Decade of Invention… A World of Solutions
by Daniel Nenni on 02-17-2012 at 1:53 pm
Categories: Events, Foundries, GlobalFoundries

Please join IBM, Samsung Electronics, Co., Ltd., and GLOBALFOUNDRIES at the 2012 Common Platform Technology Forum. The forum will showcase the alliance’s technological progress and how joint collaboration and innovation is setting the direction for industry-leading solutions to enable next-generation products.

Continue reading “Semiconductors: A Decade of Invention… A World of Solutions”

Posted on

Multicore SoC Architecture Optimization

Multicore SoC Architecture Optimization
by Eric Esteve on 02-16-2012 at 5:36 am
Categories: Arteris, EDA, IP, Synopsys

Once again with Synopsys and Arteris, the innovation is coming to solve an issue, faced by their potential customers: “In our research, we’ve found that almost half of project delays are caused by problems with the system architecture design and specification,” said Chris Rommel, vice president, embedded software and hardware, VDC Research. “Many of these architecture problems are related to escalating SoC complexity, including multicore requirements. Therefore, solutions like the one developed by Synopsys and Arteris to efficiently analyze multicore SoC architectures early in the design flow should become increasingly valuable as engineering teams look for ways to help improve project schedules and performance results.”

From a pure business point of view, Arteris and Synopsys teaming up to solve problems related to SoC complexity, including (ARM based ?) multicore requirements makes a lot of sense: both ARM and Synopsys have invested into Arteris, along with Qualcomm, the others being VC. When building a partnership, this is a very good sign of success when the two companies also have common business goals! And that’s good for the future customers, as they know that they will invest money, and also large engineering resources, into a solution which has a real future – which is not only a good way to make market communication! You can see the PR here.

Let’s have a look at what is behind this communication. The SoC development platform from Synopsys, Platform Architect environment with Multicore Optimization Technology (MCO), has been enhanced with transactors and analysis monitor support for Arteris’ FlexNoC interconnect models. The new MCO offers system architects three distinct advantages for early performance analysis and optimization of complex designs:
1.obtaining fully-instrumented performance models before software and RTL availability,
2.clearly measuring and visualizing the dynamic behavior and performance bottlenecks of multicore designs, and
3.automating the design flow to enable developers to explore hundreds of architecture alternatives in days versus weeks or months with paper specifications and RTL methods

The benefit of this faster turnaround time is that architects using FlexNoC interconnect IP can more fully explore and optimize their multicore architectures and then avoid to over- or under-design their SoC. Both can have a dramatic cost impact: if you over-design the SoC, you will spend endless time to complete the design and release it to production, loosing precious Time-To-Market, which can easily turn into much more money than the already large SoC development cost. If you under-design the SoC, you will probably hit the market window, but with a product comparing poorly with the competition, then lose market share.

“Our goal is to help system designers and architects avoid late discovery of system performance problems that can be extremely costly for both project schedules and budgets,” said John Koeter, vice president of marketing for IP and systems at Synopsys. “By starting architecture analysis and optimization at the transaction-level with Arteris’ FlexNoC interconnect models in Synopsys’ Platform Architect MCO, we offer SoC architects the ability to perform accurate simulation of the multicore system and its most critical application use-cases earlier. With this combination they can achieve the best balance of performance, power and cost at a time in the development process where they have the greatest impact.”

“Arteris FlexNoC’s integration with Synopsys’ Platform Architect MCO environment allows our customers to create better SoCs in less time,” said K. Charles Janac, president and CEO of Arteris. “Integration of the two technologies allows SoC designers to have the same quick turn-around simulation times they experience today with FlexNoC, while gaining critical benefits from the more realistic simulation and earlier analysis of their application scenarios.”

I have blogged in previous post about Arteris FlexNoC’s silicon-proven commercial network-on-chip interconnect IP offering the ability to reduce the number of interconnect wires and logic required for multicore SoC design. Reducing the interconnect wires and logic gates resolves routing congestion and timing closure issues at the back-end place-and-route stage, resulting in shorter development cycle time, faster SoC frequencies, smaller SoC area and less SoC power.

I have also blogged about Sonics vs Arterislegal battle(s), but I honestly prefer to discuss about such a partnership, as it clearly demonstrate who is bringing real innovation on this IP market!

Availability
Arteris and Synopsys’ integration is available today for users of Arteris FlexNoC version 2.6 or later, and Synopsys’ Platform Architect MCO tool version G-2011.06-SP2 or later. For more information on Arteris’ FlexNoC interconnect IP, please visit: www.arteris.com/flexnoc. For information on Synopsys’ Platform Architect MCO tool environment, please visit: http://www.synopsys.com/platformarchitect.

By Eric Estevefrom IPNEST

Posted on

DARPA looking for new base stations in new BYOD game

DARPA looking for new base stations in new BYOD game
by Don Dingee on 02-15-2012 at 1:20 pm
Categories: General

BYOD – bring your own device – has swept enterprises like a firestorm as CEOs wonder why they can’t use their shiny new iPad on the corporate network, and send their IT guys and gals off to make it happen. Under the right conditions and informed use, BYOD can be a productivity boom and not mess security and privacy up too badly for many apps.
[COMMENT] Continue reading “DARPA looking for new base stations in new BYOD game”

Posted on

Words of AMS Wisdom from the Developer of Spectre, Spectre RF, Verilog-A, Verilog-AMS

Words of AMS Wisdom from the Developer of Spectre, Spectre RF, Verilog-A, Verilog-AMS
by Daniel Payne on 02-15-2012 at 10:27 am
Categories: Cadence, EDA

Ken Kundert while at Cadence developed: Spectre, Spectre RF, Verilog-A and Verilog-AMS. About 6 years ago he and Henry Chang left Cadence and created a consulting company called The Designers Guide.

Continue reading “Words of AMS Wisdom from the Developer of Spectre, Spectre RF, Verilog-A, Verilog-AMS”

Posted on

Power to the Drones

Power to the Drones
by Paul McLellan on 02-14-2012 at 6:01 pm
Categories: Ansys, Inc., EDA

Unmanned systems are becoming indispensable to military forces and are used across all of land, sea and air. The generic name for such unmanned systems is UXS, usually UAS (air), UGS (ground) or UUS (underwater). The UAS is the most visible, both due to military strikes and the views of Japan after the Tsunami when areas were unreachable by other means.

As the value of UXS continues to be proven in the field, there is a drive towards lower-cost and lower-risk platforms. But as the systems get smaller but require greater capability (smart weapons, electronic counter-measures, embedded intelligence) the demand for power is potentially insatiable. Especially for airborne vehicles, there is an obvious balance between the amount of sustained power and the weight of power generation and storage systems (this doesn’t sound all that different from the same types of tradeoffs that smartphone designers need to make).

One of the promises of the ANSYS acquisition of Apache is that it become possible to combine the physics-based simulation tools with electronic system modeling to create virtual representations of vehicles and payloads and analyze space, power, thermal prior to physical testing (prior to even building the vehicle).

Power management must be addressed early in the design phase, at the architectural level, to ensure a long-enduring unit. Two of the smallest unmanned air systems currently in operation rely solely on batteries to power their motors and on-board electronic systems. Both the WASP III and Raven micro air vehicles (MAVS) can fly for approximately 45 minutes to 1 hour before they need to land and recharge their batteries. Reducing power consumption in these designs, therefore, is critical to the ability to deliver real-time surveillance information.

But these MAVs carry the same amount of on-board cameras and surveillance capabilities as larger, high-end UASs. Unnecessary power consumption of UAS chips will lead not only to early depletion of their battery power sources, but to electrical and thermal reliability issues, which can shorten the UAS’s expected lifetime and render it unreliable in the field. Military equipment operates, almost by definition, in a hostile environment and reliability in extreme environmental conditions, especially electromagnetic interference, is obviously of paramount importance.

Next-generation unmanned systems are being developed to meet growing requirements of field reconnaissance, strike capability and longer mission duration, as well as new fields of operation in land, sea and air. As the military seeks to expand the role of unmanned systems, industry must rise to the urgent challenge of ensuring that power supply requirements of these systems are met within their allotted power and thermal envelope. Only a multiphysics approach, initiated early in the design phase, can simulate the power consumption and thermal dissipation of these complex systems, enabling successful power reduction and thermal cooling solutions for onboard electronics. The power integrity of these systems and their ability to conform to reliability and emissions standards can be validated through ANSYS and Apache simulation solutions for the individual components as well as for comprehensive onboard electronic systems.

Read the white-paper by Robert Harwood of ANSYS and Margaret Schmitt of Apache here.