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Crushed Blackberry

Crushed Blackberry
by Paul McLellan on 07-02-2012 at 12:00 am
Categories: General
1 Comment

I wasn’t going to write about the cell phone business again for some time. After all, this is a site about semiconductor and EDA primarily. But the cell-phone business in all its facets is a huge semiconductor consumer and continues to grow fast (despite my morbid focus on those companies that do anything but).

But Research in Motion (RIM) announced their results last week. RIM is more famous by the name of its product, Blackberry. Crackberry as it used to be called. Now, not so much, it’s lost its addiction.

They lost 30% of their market share. In one quarter. A couple of years ago they had 20% market share. Now they have 5%. And the market grew four-fold, so in unit terms they are not off as much as it might seem. But if you stay static in a market that is growing explosively then you are not going to survive. And RIM is not going to survive. They have engaged bankers to explore strategic options (most of which probably involve dismembering the company since it is hard to see it as a going concern in its current form).

They announced two other big things. They are going to lay off 5,000 people. Since they have 15,000 employees that is a third of the company. Any company can lay of 5-10% of their people with minimal effect: people who don’t contribute, marginal products and so on. But nobody can lay of 30% of the company and “cut to success”. I don’t know anyone who ever did it.

Perhaps worse is that the new Blackberry operating system 10, which was meant to come out in 3Q and is now delayed until 2013 (and, as some commentators say, will probably never come out since RIM’s realistic runway isn’t that long). RIM had decided to focus on the business market (their core strength but also the slowest growing segment, especially in the new world of BYOD, Bring Your Own Device) so that might not matter that much since business is less affected by Christmas than consumer. But it’s a disaster by any measure. As a software manager in past lives I know how hard it is to forecast product delivery dates, especially when the world is changing around you (and management is changing your priorities on a daily basis) but a 6 month slip now is likely to be fatal. That poor software manager is also probably being told to do without 25% of his engineers too. Doesn’t add up.

Anecdotally, what is killing RIM is Android. I have 3 friends who had Blackberries a couple of years ago. All three have Android phones now. Obviously iPhone is in the picture too. If it weren’t for Nokia, this would be the worst track record ever. And I don’t just mean in cell-phones, no companies have ever collapsed so fast as RIM and Nokia. Moreover, they play in a trillion dollar industry (of which there are only a handful: mobile, automotive, finance, medicine…) so a percentage point is tens of millions of dollars.

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Synopsys IP Strategy 2012

Synopsys IP Strategy 2012
by Daniel Nenni on 07-01-2012 at 7:30 pm
Categories: IP, Synopsys
1 Comment

Synopsys is the dominant player in the commercial EDA and semiconductor IP markets so it is always interesting to hear what John Koeter, Vice President of Marketing for IP, Services and System Level Solutions, has to say. John presented “The Role of IP in a Changing Landscape” at the SemiCO IMPACT Conference and I talked to him again at DAC 2012.

John and I are science fiction fans and agree that fiction sometimes becomes fact. John and I both are currently reading a new David Brin book called Existence. Too early to tell if it will finish strongly but it certainly opens with some interesting ideas including people in the near future who wear VR glasses to see virtual advertisements (real advertisements are banned — bad for the environment). Deals are concluded with a handshake duly witnessed by the goggles and immediately backed up to a secure site creating a legally binding contract. The glasses can also tap into other people POV (if unencrypted). If you want to be really narcissistic, you can enter “tsoosu” mode “to see ourselves as others see us” and compile multiple POVs of yourself. And this is all covered in just two short pages at the beginning of the book.

John said he is looking forward to working with semiconductor designers to make amazing technology like this a reality:

“It is truly an exciting, dynamic, and challenging time in technology. Complex devices will require sophisticated SoCs which will require IP and EDA vendors to continue to provide increasingly sophisticated, well-integrated IP and EDA solutions.”

Well integrated EDA and IP solutions……… Interesting!

Notes from the Presentation:

  • Smart everything
  • Internet of things
  • Everything connected
  • Cloud Mobile

Interesting facts from Cisco Visual Networking Index: Global Mobile Data Traffic Forecast Feb 14, 2012:

  • Last year’s mobile data traffic eight timesthe size of the entire global Internet in 2000
  • Global mobile data traffic grew 2.3-foldin 2011, more than doubling for 4[SUP]th[/SUP] year in a row
  • Mobile video traffic exceeded 50%for the first time in 2011
  • Average smartphone usage nearly tripledin 2011
  • In 2011, a 4[SUP]th[/SUP] generation (4G) connection generated 28x more traffic on average than non-4G connection

Tomorrow’s World:

  • Reality -> Augmented Reality -> Blended Reality
  • Search ->Agents -> Info that finds you and networks that know you
  • 2D ->3D -> Immersed Video -> Holographic
  • Medical -> Mobile Medical -> Personal Medical
  • Person to person -> Machine to Machine -> Human Machines

How Does This Affect Semiconductor Design:

  • Computing -> Connectivity
  • Creating Info -> Consuming Info
  • Compute Power -> Battery Power
  • Business -> Consumer
  • At Your Desk -> Anywhere, Anytime
  • Work -> Entertainment

Trends drive semiconductor process migration, increasing gate count and faster designs while requiring aggressive power management. IE: Design challenges are multiplying.

SoC = System on Chip = Software on Chip. Software development is half the time to market for a typical SoC and half the cost.

Software guys are pessimists:
Page’s Law = Software gets twice as slow every 18 months.
Wirth’s Law = Software gets slower more rapidly than hardware gets faster.

Economics of Scaling are tough but can be addressed:

  • Process technology advances (20nm, 16nm, 14nm…)
  • New transistor technology (FinFET)
  • Innovative circuit design
  • New layout techniques
  • New transistor biasing techniques

IP Vendors need to provide more function and functionality!

IP Subsystems are the next evolution in the IP market. What is an IP Subsystem?

Complete solution: HW, SW, Prototype, pre-integrated and verified
SoC Ready: Seamlessly drop in and go

Ultimate SoC example: The human brain is capable of exaflop processing speeds, petabyte of storage, full 3D image processing, fully capable of augmented reality, and runs on 12 watts of power. Semiconductor technology has a ways to go but we can get there.

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Dragon Boats and TSMC 20nm Update!

Dragon Boats and TSMC 20nm Update!
by Daniel Nenni on 07-01-2012 at 6:30 pm
Categories: Foundries, TSMC
2 Comments


My luck continues as I missed last week’s typhoon. Fortunately it did not disrupt the annual Dragon Boat Festival. More than just a Chinese tradition, dragon boat racing is an international sports event with teams from around the world coming to Taiwan every year. It is very exciting with the colorful dragon boats and the wild beating of the drums to spur the rowers on. It is an early version of crew (rowing), which is one of the oldest Olympic sports I’m told.

Even more exciting, TSMC has 20nm up on the TSMC website now! Exciting for me at least! This is really cool stuff and it is right around the corner. I also like the new TSMC website and banner ads. It really does show a much more progressive communication style for a foundry.

TSMC provides the broadest range of technologies and services in the Dedicated IC Foundry segment. In addition to general-purpose logic process technology, TSMC’s More-Than-Moore technologies support customers’ wide-ranging needs for devices that integrate specialty features with CMOS logic ICs. TSMC’s More-Than-Moore technologes offer the segment’s richest technology mix, and unmatched manufacturing excellence. Through TSMC Open Innovation Platform™, we provide a robust portfolio of time-to-volume foundry and design services, including front-end design, mask and prototyping services, backend packaging and test services, and front to back-logistics, to speed up More-Than-Moore innovations.


Applications driving 20nm anytime, anywhere, any device

20nm technology is under development to provide best speed/power value for both performance driven products like CPU (Central Processing Unit), GPU (Graphics Processing Unit), APU (Accelerated Processing Unit), FPGA (Field-Programmable Gate Array) and mobile computing applications including smartphones, tablets and high-end SoC (System-on-a-Chip).

In regards to the constant 20nm scaling questions, TSMC 20nm is said to offer a 30%+ performance gain and 25%+ power savings versus 28nm. Has anybody heard what other foundries are claiming lately? It will be interesting to see what the fabless companies can do with 20nm silicon. The success of 28nm will certainly be hard to beat but I can tell you one thing, the fabless guys are spending a lot of time in Hschinsu, EDA and IP vendors are camping out there as well. You will be hard pressed to tell the difference between the old guard IDMs and the leading edge fabless company’s process technology groups, except of course their CAPEX! Expect 20nm risk production to start in Q4 2013, two years to the quarter after 28nm.



TSMC is the world’s largest dedicated semiconductor foundry, providing the industry’s leading process technology and the foundry segment’s largest portfolio of process-proven libraries, IPs, design tools and reference flows. The Company’s managed capacity in 2011 totaled 13.22 million (8-inch equivalent) wafers and is the first foundry to provide 28nm production capabilities.

TSMC’s mission is to be the trusted technology and capacity provider for the global logic IC industry for years to come.

Notice it says “capacity” now. Company mission statements are also reminders for employees so you can bet capacity will be on everyone’s mind for process nodes to come, believe it.



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The Scariest Graph I’ve Seen Recently

The Scariest Graph I’ve Seen Recently
by Paul McLellan on 07-01-2012 at 4:00 pm
Categories: Foundries, General
15 Comments

Everyone knows Moore’s Law: the number of transistors on a chip doubles every couple of years. We can take the process roadmap for Intel, TSMC or GF and pretty much see what the densities we will get will be when 20/22nm, 14nm and 10nm arrive. Yes the numbers are on track.

But I have always pointed out that this is not what drives the semiconductor industry. It is much better to look at Moore’s Law the other way around, namely that the cost of any given functionality implemented in semiconductors halves every couple of years. It is this which has meant that you can buy (or even your kid can buy) a 3D graphics console that contains graphics way beyond what would have cost you millions of dollars 20 years ago in a state of the art flight simulator.

But look at this graph:


This shows the cost for a given piece of functionality (namely a million gates) in the current process generation and looking out to 20nm and 14nm. It is flat (actually perhaps getting worse). This might not matter too much for Intel’s server business since those have such high margins that they can probably live with a price that doesn’t come down as much as it has done historically. And they can make real money by putting more and more onto a chip. But it is terrible for businesses like mobile computing that don’t live on the bleeding edge of the maximum number of transistors on a chip. If you are not filling up your 28nm die and a 20nm die costs just the same (and is much harder to design) why bother? Just design a bigger 28nm die (there may be some power savings but even that is dubious since leakage is typically an increasing challenge).

If this graph remains the case, then Moore’s Law carries on in the technical sense that you can put twice as many transistors on your chip if you can think of something clever to do with them and can find a way to keep enough of them powered on. But it means there is no longer an economic driver to move to a new process unless you have run out of space on the old one.

Since EDA mostly makes money on designs in new processes (because they need new tools which can be sold at a premium) this is bad for EDA. It actually doesn’t make money on the first few designs coming through a new process because there is so much corresponding engineering to be done. But if the mainstream never moves, the cash-cow aspect of selling EDA tools to the mainstream won’t happen. And just like there is no business selling “microprocessor design tools” since there are too few groups who would buy them and their needs are too different, there might never be a big enough market for “14nm design tools” to justify the investment.

So that’s why this is the scariest graph in EDA.

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Chip Synthesis at DAC

Chip Synthesis at DAC
by Paul McLellan on 06-27-2012 at 8:30 pm
Categories: EDA

I visited Oasys Design Systems and talked to Craig Robbins, their VP sales. For the first time this year, Oasys has a theater presentations and demos of RealTime Designer which are open to anyone attending the show. In previous years, they have had suite demos for appropriately qualified potential customers but outside they have just had videos. Funny videos, but you don’t really get to look under the hood in them.

The theme of the theater presentation was “right here, right now” to reflect the fact that RealTime Designer is…err…real. As is Oasys themselves, having just had a cash injection from the #1 semiconductor company and the #1 FPGA company. That would be Intel Capital and Xilinx.

Oasys are proud of their customer list too. Qualcomm, Netlogic (now part of Broadcom), Texas Instruments. With Xilinx and Intel Capital they have relationships with the top US semiconductor companies. After all if companies like these are doing their most challenging designs with Oasys then that is a true vote of confidence in the technology. It is really hard to tell if an engine is any good just by taking the cylinder-head off, much easer to see who is confident enough to put the engine in their cars.

RealTime Designer’s big claim to fame is that it is blazingly fast and has huge capacity. Traditional synthesis takes in RTL and converts it to a rough-and-ready netlist and then optimizes that netlist. This requires the whole netlist to be in memory (so needs a lot of it) and means that only small incremental improvements are possible. Thus to get anywhere, it needs to make millions of these little changes which takes a long time. RealTime Designer operates by partitioning the RTL into small regions and each reducing each of those to a fully-placed netlist. If the design doesn’t make its constraints (paths with negative slack, meaning the netlist is too slow) then it returns to the RTL level, repartitions (if appropriate), resynthesizes and re-places just that small regions and perhaps its neighbors. This turns out to converge must faster on a solution with good quality of results (QoR) requiring only thousands of adjustments.

As a result RealTime Designer has a capacity of over 100M gates and runs 5-40 times faster than traditional synthesis tools.

The demo on the show floor didn’t actually run RealTime Designer live (most of the time) since most people don’t even have the patience to watch a 15 minute demo and presentation. But when they did that’s all that the design they used for the demo took to synthesize. How big was it? It was a full-chip 6 million gate quad-core SPARC T1, 421 macros, 261 I/O pads, 1.2GHz clock in 65nm.

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TSMC Threater Presentation: Lorentz Solution!

TSMC Threater Presentation: Lorentz Solution!
by Daniel Nenni on 06-26-2012 at 8:30 pm
Categories: EDA, Foundries, TSMC

Lorentz Solution presented at TSMC’s DAC 2012 Open Innovation Platform Theater. The presenter was Lorentz Sales Director, Tom Simon. He presented what Lorentz calls its Electromagnetic Design and Analysis Platform. One of the main points of the talk was the cooperative work that Lorentz does with TSMC.

TSMC and Lorentz work together in several ways. TSMC uses Lorentz’s PeakView for designing their RF IP. In addition to working to support mutual customers, there is collaboration on RDK’s and ongoing correlation projects. These projects ensure accurate results on a wide range of structures and devices. Special focus on capacitor structures, and proper handling of metal fills, guard rings, and pattern ground shields yields excellent correlation up through millimeter wavelength frequencies.

Lorentz says that PeakView is suitable for both design use and sign-off, avoiding the “two-tool” solution that many customers live with.

For design PeakView fits in the flow for new device creation with its PCircuit synthesis. Complex devices can be ‘what-if’ed to arrive at optimal tcoil, transformer, balun, tline and cap configurations that best suit the designer’s needs. Multiple devices can be compared side by side in the Device Editor.

Lorentz emphasized that synthesis with PCircuits does not require costly and time consuming EDA vendor set up: no scalable models are needed. As soon as a new layer stack-up is created in PeakView, the full power of PCircuits is available. They say that new and complex devices with high port counts are easily synthesized. There is no dependency on pre-characterization of the process or the cell. Apparently this opens a much larger design space for customers.

PeakView has a new circuit level capacities to electromagnetically model critical interconnections for RC and especially L in the LPE/PEX flow. Complex critical nets are easily and properly analyzed during design iterations, without manual intervention. Simon said the resulting circuit simulation accuracy improves silicon predictability.

PeakView is now also tightly linked to Laker, as well as to Virtuoso. PeakView’s PCircuits, used to create passive device designs, work equally well in both layout editors. PCircuits are process independent and can easily be created to handle new devices. Unlike Pcells, they are compact, object oriented and PDK driven.

Complex hand drawn or PCircuit generated structures can be electromagnetically simulated by PeakView with its fast full wave 3D field solver. Simon added that PeakView allows for accurate and efficient analysis of metal fills, via arrays and other complex structures.

After electromagnetic simulation, compact convergent DC accurate Physics Based Models (PBM) are generated as RLC sub-circuits, in addition to s-parameter output. Process variation and temperature coefficients are supported.

PeakView has built in visualization for viewing voltage, current and meshing. It also features a built in chart window. Its GUI based operation is perfect for increased designer and modeling team productivity.

Bottom line: Lorentz has built a platform for designers and modeling teams that increases creativity and productivity by letting designers create their own geometry and models, and at the same time improving the efficiency of the EM experts with a faster highly accurate solution for sign off model creation. Lorentz’s new capabilities at the circuit level add significant accuracy to high speed analog design.

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Robustness, Reliability and Yield at DAC

Robustness, Reliability and Yield at DAC
by Daniel Payne on 06-26-2012 at 8:15 pm
Categories: EDA, Events

On Wednesday at DAC I met with Bob Slee, distributor and Michael Siu, AE for MunEDA to get an update on what’s new. MunEDA has EDA software for:

  • Schematic porting
  • Nominal circuit analysis
  • Nominal circuit optimization
  • Statistical circuit analysis
  • Statistical circuit optimization
  • IP porting
  • Circuit model generation

Continue reading “Robustness, Reliability and Yield at DAC”