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ESD – Key issue for IC reliability, how to prevent?

ESD – Key issue for IC reliability, how to prevent?
by Pawan Fangaria on 04-23-2013 at 8:30 pm
Categories: EDA, Siemens EDA

It’s a common electrical rule that when large amount of charge gets accumulated, it tries to break any of its surrounding isolation. Although it wouldn’t have been prominent in 1980s or 90s, protection for ICs from such damaging effects is a must, specifically in large mixed-signal designs of today, working at different voltages and at lower process nodes where gate oxide can become extremely thin and breakdown voltage can become very low.

ESD(Electrostatic Discharge) failure in CMOS ICs can be caused due to thermal breakdown on high transient current or dielectric breakdown in gate oxide due to high voltage. If the IC does not fail immediately, it will gradually degrade in performance. In order to protect ICs from ESD, protection circuitry must be applied across IOs and power lines.

ESDA (ESD Association) puts the verification guidelines in three main steps- identifying the ESD vulnerable devices, verifying the implementation for ESD protection and checking completeness of each such device for its protection. SI2 also recommends a standard ESD protection design flow methodology at –
http://www.si2.org/openeda.si2.org/project/showfiles.php?group_id=82&release_id=558

The burgeoning complexity and size of nanometer designs have made it utmost important that a full proof automated system must be implemented for checking ESD conditions being created during manufacturing and making sure that protection is built around IO pads such that any large voltage spikes are dissipated before they reach thin oxide devices and any internal circuitry of the IC. Mentor has developed a novel solution for this important problem. Its tool, Calibre PERC checks the topology of the design for appropriate implementation of ESD structures and their placement with respect to devices to be protected and the core of the IC. Calibre PERC implements all 39 ESD checks,recommended by ESDA, such as layout checks, netlist checks, current density checks etc. to name a few important ones. The current density check ensures interconnect robustness.

[ESD in metal interconnects]

The ESD verification is done at multiple levels from Cell to Package, intra-power and inter- power domains. Calibre PERC identifies external device configurations as ESD protection structures.

[Some commonly used ESD protection configurations]

Calibre PERC can be programmed to perform other tasks such as parasitic extraction of metal interconnects, design rule checks, current density calculation, electrical compliance etc. A very important aspect of Calibre PERC is that it performs AERC (Advanced Electrical Rule Checks) which can identify signal lines between power domains which work at different voltages in a mixed-signal design and ask for additional ERC configurations between these domains.

[P2P extraction, current density analysis and design rule checks on identified topologies]

A nice description of ESD and its protection application in Calibre PERC is given in Mentor’s whitepaper at –
Solving Electrostatic Discharge Design Issues with Calibre® PERC™

Calibre PERC provides a comprehensive, integral and complete, automated, error free solution for checking and correcting ESD conditions resulting into increased yield, performance and reliability of ICs.

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Gigahertz FFT rates on a 500MHz budget

Gigahertz FFT rates on a 500MHz budget
by Don Dingee on 04-23-2013 at 8:30 pm
Categories: EDA, Synopsys

A basic building block of any communication system today is the fast Fourier transform, or FFT. A big advantage of FPGA implementations of FFTs is they can be scaled and tuned for the task at hand, optimizing data flow, resource use, and power consumption. Scaled, that is, up to the clock speed of the FPGA – or so it would seem.

Today’s systems often present a massive amount of very fast data at the front end that needs to be sampled and decimated quickly, typical of a system with a lot of data channels in play like satellite radio or cable head-end systems. Sample rates run into the gigahertz range, putting them outside the range of FPGA clock speeds if the constraint is one sample per clock.

Parallelism comes to the rescue in a Synopsys FFT IP implementation. In state-of-the-art FPGAs, there is plenty of room to create parallel computational blocks, coordinating operations across multiple inputs. Instead of forcing a single block to run faster to keep up with data, a parallel approach allows data to be sampled and processed faster.

The key to this is the Radix2 multipath delay commutator, a modular architecture which keeps the pipeline in sync between data elements. Flow control is implemented without a big timing penalty and reduction in throughput.

The following chart illustrates a simple case of what parallelism can achieve on a relatively small FFT. When I asked him what the architecture is capable of, Chris Eddington mentioned this IP can do a 16k point FFT operating on 32 parallel inputs, but keep in mind there is some reduction in system clock frequency as more parallel channels are stitched together with flow control.

Besides sampling faster, parallelism also decreases computational latency. The cost of this approach is of course area and multiplier utilization, but with 1120 to 3600 DSP slices in a Xilinx Virtex-7, this still fits very comfortably.

Of course, both Altera and Xilinx have capable FFT IP blocks, but there are a few key differences in the Synopsys implementation beyond the parallelism features. The Synphony MC tools are vendor independent and can target various FPGAs. The flow integrates with MATLAB Simulink for designers who prefer to work in high level architecture. Not every designer is an FFT expert, so being able to operate in high level tools is a plus.

The flow also instantiates RTL and System C, giving designers the flexibility and visibility needed to integrate the code into their system and tune things if necessary. Rather than being a “black box” implementation, this allows designers to simulate performance and power using other tools.

Speaking of tuning and power, one other way to use a parallel approach would be to consume reasonably fast data in lower power. Instead of going for the peak sample rates possible, parallel channels would allow a good sample rate at a lower FPGA clock speed.

You can read more insights on this FFT architecture from Chris and the Synopsys team in their article:
“Multi-Gigahertz FPGA Signal Processing”.

lang: en_US

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CDN Live 2013 in Munich: what’s the next acquisition?

CDN Live 2013 in Munich: what’s the next acquisition?
by Eric Esteve on 04-23-2013 at 8:10 pm
Categories: Cadence, IP

Going to Munich in May could be a very good idea, as it will give you the opportunity to listen to the keynote talk from Lip-Bu Tan. Who knows if you will learn in direct live the name of the next acquisition from Cadence in 2013, after Tensilica and Cosmic Circuits? In fact, there may not be new acquisition announcement, then this keynote talk should help understanding current Cadence’ strategy for developing IP business. Looking at the other keynotes talks gives some direction:

  • Industry keynote: Keith Klarke, VP Embedded Processor, ARM
  • Industry keynote: Rudi de Winter, CEO X-FAB

Extracted from their web site: “X-FAB manufactures wafers for automotive, industrial, consumer, medical, and other applications on modular CMOS and BiCMOS processes in geometries ranging from 1.0 to 0.18 µm, and special BCD, SOI and MEMS long-lifetime processes.” X-FAB market positioning is not to compete head on with TSMC or GlobalFoundries on 28 nm technologies, but to serve growing market segments like automotive and industrial, requiring mature technology nodes supporting high voltage or/and high current.

Keith Klarke, from ARM, will deliver the second keynote talk after Lip-Bu Tan. This is a good indication about the IP strategy that Cadence is building: Tensilica IP will not be used to compete with CPU or GPU IP cores from ARM, but rather could be integrated within ARM based architecture. We can imagine, for example, an integrated AP/BB chip implementing ARM Cortex big.LITTLE CPU architecture and LTE modem based on Dataplane customizable processor from Cadence/Tensilica imtegrated together. As Tensilica Dataplane also supports many other application like audio, voice and speech or image/video processing, to name a very few, there will be room for cooperation… and also for competition. By having ARM VP giving a “Industry Keynote” talk right after Cadence CEO is certainly a sign that Cadence prefers cooperation with ARM, which is by far the most realistic approach: the MIPS recent history has shown that the market don’t really need “another RISC CPU core family”, but rather a complementary offer. L

ike I write in Semiwiki a couple of years ago, ARM ubiquity has been built on the long term, is now based on a 1000 partners Ecosystem and an essential customer installed base. Will such a status change in the near, or even far, future? Competing head on with ARM would require such an amount of energy, time and resource, that I don’t see Cadence (or Synopsys) to initiate such a battle. Staying partners is certainly the wiser solution!

CDN-Live is a three day event, with an equivalent two days agenda, and covers from mixed-signal full custom, to digital, IP and Verification based design, up to PCB, signal integrity or power aware design. On May 8, Hardware/Software, as well as chip/package co-design and system-level design will be covered. That day will also include presentations made by users from Freescale, Renesas, ST-Microelectronics, ZMD, Infineon or Amkor. During the event there will be tutorials made by cadence and Academic presentations from various Universities in Europe. This should be a dense event!

To Register to CDN-Live, just go here

On my side I will focus on the Design and Verification IP tracks, with a special attention about Interface IP: PCIe and M-PHY, USB 3.0 PHY IP, Memory Models for Verification and DDR SDRAM Memory Controller and PHY IP. It will also be a good opportunity to learn about Tensilica Dataplane CPU and I am sure not to miss that track, as I will make the presentation just before, named “Interface IP protocols: the winners, the losers in 2012”. It will be strongly updated from the presentation made during IP-SoC last December in Grenoble, as many changes have occurred during Q1 2013! Because
we can now take into account the 2012 actual IP sales results for the various protocols (DDRn, USB, PCIe, SATA, MIPI, Ethernet, Thunderbolt, HDMI, DP), it will be fresh information, in advance from the launch of the “Interface IP Survey”…

Eric Esteve from IPNEST

lang: en_US

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Mary Meeker’s Annual Internet Trends is Out

Mary Meeker’s Annual Internet Trends is Out
by Paul McLellan on 04-23-2013 at 8:05 pm
Categories: General

Every year, analyst Mary Meeker produces a large presentation (88 slides this year) about internet trends. This year’s oneis just out. So much of the semiconductor industry is driven by trends in mobile and PCs. Increasingly, just by mobile since it has already overtaken PCs in terms of units and will soon overtake in terms of semiconductor content. I covered last year’s presentation here.


In the graph below, the orange and blue bars are the PC (desktop and notebook) and the green and yellow bars are smartphones and tablets. Q4 2010 was the inflection point when mobile device shipments surpassed PC shipments and you can see the enormous growth out into the future.

The middle part of the presentation is about how the internet is disrupting various businesses from the obvious ones (payment: square, paypal; hotels: airbnb, couchsurfing; taxis: uber etc) to many I haven’t heard of.

She ends with some cautionary notes. “Lots to be excited in tech, lots to be worried about in other areas.”

Two big ones. First student loans:

Second, general US government spending, which is at the biggest gap above revenue since the middle of the first and second world wars.

Mary Meeker is a general partner at Kleiner Perkins Caufield & Byers and joined the firm in January 2011. She focuses on investments in the firm’s digital practice and helps lead KPCB’s Digital Growth Fund, targeting high-growth Internet companies that have achieved rapid adoption and scale. Mary serves on the boards of Square, Lending Club, DocuSign and Quirky and is also actively involved in KPCB’s investments in Twitter, LegalZoom, Spotify, 360buy.com, Waze, Jawbone, SoundCloud and Affectiva.

A prolific writer, Mary is the co-author of the industry-defining books The Internet Report (1995) and The Internet Advertising Report (1996). She is also the co-author of The Internet Retailing Report (1997), The Online Classified Advertising Report: It’s About Search/Find/Obtain (SFO) (2002), The China Internet Report (2004), The Mobile Internet Report (2009), and The Technology IPO Yearbooks. Beyond technology, Mary (and Liang Wu) created USA, Inc. (2011), an award winning, non-partisan report / video that looks at the U.S. government (and its financials) from a business perspective. Mary’s reports (including her annual Internet Trends presentations) are widely read around the world.

Once again, this year’s presentation is here.

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Mentor Graphics’ Best User2User Ever

Mentor Graphics’ Best User2User Ever
by Beth Martin on 04-23-2013 at 5:45 pm
Categories: EDA, Siemens EDA

Calling all Mentor users! Don’t forget to register for the U2U in San Jose on Thursday, April 25.

In addition to three worthy keynotes, you will find a more interactive and solution-focused day than in the past. There are sessions on place & route, custom/AMS, emulation, test and yield analysis, functional verification, Calibre signoff, and PCB. You will have time enough between sessions to ask questions and get answers from the veritable army of Mentor technical experts who will be available. These technical experts will be armed with lots of product demos. If you’d like a preview of some very useful ‘how-to’ demos, check out this collection of short videosthat show how to do specific tasks in several Calibre tools.

The first presentations after the morning keynotes are product roadmap updates from Mentor. After the lunchtime keynote by Dr. Chenming Hu, father of FinFETs, the sessions are mostly case studies from other Mentor users. The whole schedule is available here.

As always, the event is free and includes lunch and a happy hour. I’ll be there, learning and mingling. If you see me, tell me what you found useful, surprising, or interesting!

Register for the Mentor User2User meeting here.

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Forte Rises

Forte Rises
by Randy Smith on 04-23-2013 at 3:00 am
Categories: EDA

Over the past few months there has been a bit of back-and-forth concerning the 2012 market data indicating that Forte Designs Systems had taken over the top spot (by revenue) in the high-level synthesis (HLS) market (see stories hereand here). Having worked in this segment for Synfora as VP of Marketing, and as a consultant to AutoESL, I feel I know this segment well enough to take a deeper dive.

If we go back only five years, Mentor’s Catapult-C was the clear market leader in the high-level synthesis market. My own market research (a privately sold report sent to two vendors in 2009) had them at nearly half the market (by revenue) at that time. What was less clear, was the split of revenue for Mentor between ASIC and FPGA designers in this market. At that time other market participants included Forte, Synfora, Bluespec, Impulse C, Cadence, and AutoESL. A crowded market indeed, and my projected growth rate at that time for the segment was a healthy 19% per year.

My how that market segment has changed! In August 2011, Mentor sold Catapult C to Calypto, reportedly in exchange for a large piece of equity of Calypto (perhaps controlling interest, per multiple sources). If Mentor was so committed to ESL did this make sense? Others pointed to a perceived need for Mentor to somewhat exit the HLS market in order to be more vendor-neutral in adjacent markets. That is not a move Synopsys or Cadence would ever make, but Mentor does play more product-centric than the other major vendors who are more interested in a complete front-to-back flow. In any event, it created an opportunity for others.

AutoESL was a fast rising star in the HLS segment, at least at the technology level. Xilinx snapped themup at a hefty premium a bit more than 2 years ago. This was a smart move for Xilinx, but it also effectively diverted the AutoPilot product team to focus on the FPGA market rather than the ASIC market. It was a very different scenario when Synopsys acquired the assets of Synfora in June of 2010. Synfora had been struggling for a long time and Synopsys acquired the assets for very little. In fact, the Synfora CTO/Founder, Vinod Kathail, whom I have a tremendous amount of respect for, ended up at Xilinx, not at Synopsys.

Now, fast forward to 2013 and we have a new HLS market leader, Forte Design Systems. Forte’s HLS revenue now exceeds Mentor/Calypto’s. Synopsys, as expected, has earned little revenue from its Synfora acquisition. Cadence’s internally developed HLS tool has received little market traction, just like most tools developed rather than acquired by the major EDA companies. However, it appears that Cadence was doing better than first thought as they have recently indicated that they mistakenly had failed to report HLS revenues to analysts. One thing is abundantly clear, no one is growing as quickly in the ASIC HLS segment as Forte.

Forte has been focused on HLS for ASIC design since its inception. This focus has contributed to seven consecutive years of increasing revenue. Significantly, Forte has had several close Japanese customers for many years. In its most explosive growth years, Cadence had paid partnerships with as many as five Japanese semiconductor companies at a time. The management style of Japanese companies leads to iterative improvement in their suppliers offerings. But this benefit is only gained if the relationships are effectively managed, and Forte has clearly done that. Forte KK will celebrate its tenth anniversary next year, a strong testament of its commitment to its Japanese customers. Forte continues to add new customers worldwide as well.

Is it possible that Calpyto’s figures are understated due to the way it recognizes revenue compared to how Mentor recognized revenue? Perhaps. We simply will not know until 2013, or maybe even 2014, figures are reported. I would not expect Mentor to open its books for this type of analysis. I also have not seen the details of the transaction between Mentor and Calypto. Did Mentor really take all the revenue and cash for multiyear deals for itself and dump the support costs of that on Calypto without paying for it? If they would have paid for it, then wouldn’t that be in Calypto’s revenue now already? There are many factors to this and we are just not going to get to see them all to analyze this thoroughly.

Two conclusions are clear: (1) Based on reported 2012 revenue, Forte is the current market leader in High-Level Synthesis; and (2) Forte is the fastest growing company in this segment as well. The second part of this bears repeating. Forte grew faster than Calypto in this segment in 2012, after having done so in 2011 as well. Forte has a mature product offering, and it is building strong momentum. HLS will become more mainstream as we inevitably create designs with more content. Forte is beginning to emerge as one of the most prominent private EDA companies, and the leader in their market segment. The stage is set for a fun year to watch the High-Level Synthesis market.

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FinFET Day Presentations at EDPS Monterey!

FinFET Day Presentations at EDPS Monterey!
by Daniel Nenni on 04-22-2013 at 10:00 am
Categories: EDA, Events

If you are ever asked to organize a conference session do not hesitate, accept immediately and jump right in. When John Swan, EDPS General Chair, asked me to organize a day I hesitated. Fortunately he is not one to take no for an answer. It was an unforgettable experience on many levels and I hope to be involved with EDPS again next year. Yes it was that good.

First the location, Monetery is absolutely the best place for a conference. The hotel was right on the beach with the most amazing views. The weather was excellent, the hotel food was excellent, it was one of the most relaxing and informative weekends I have had in a long time. I have always pushed for more convenient conference locations to get the highest attendance but I was wrong. Quality over quantity, location, location, location and Monterey is a great place.

Picking the topic and presenters for a conference should probably be a stressful thing but it was what I enjoyed the most. FinFET was the most written about subject and top trending search term on SemiWiki in 2012 so that was easy. The presenters were people I know and respect so that was also easy. Organizing and coordinating the day took much more time than I had imagined but it was well worth the effort.

Here’s how the day played out:

I did a quick 15 minute keynote to set the day up with my FinFET experiences and SemiWiki analytics. My good friend Tom Dillinger finished the keynote with a Primer on FinFETswhich was a perfect set-up for the rest of the day. Tom has been a great technical back-up on FinFETs including the FinFET Wikion SemiWiki. Tom is also a great speaker, the author of VSLI Engineering circa 1987, and an expert in this field.

After the break Tom did his presentation on FinFET parasitics, which as it turns out, is one of the biggest challenges facing FinFET designers today and tomorrow. Thank you Tom, you hit this one out of the park.

Next up was Rob Aitken. I first met Rob at Artisan many years ago and he is now an R&D Fellow at ARM. Rob presented FinFET SoC Design Challenges which included a Silicon Device Roadmap down to .35nm which may not have any actual silicon content. What!?!?!?!?!

Next up was Raymond Leung. I first met Raymond when he was VP of Engineering at Virage Logic. We met up again when he was VP of Memory Development at UMC and now he is VP of Engineering at Synopsys. Raymond presented on FinFETs and SRAM Design. Since SRAMs are the pipe cleaners for new semiconductor processes and Synopsys is the top SRAM provider, Raymond has seen the most 16/14nm silicon thus far. He presented FinFET design challenges in great detail and who would know better than Raymond.

Tom Quan finished the session with FinFET Design Ecosystem Challenges and Solutions. Tom is a great presenter and clearly distinguishes between marketing and silicon correlated data. According to Tom the value proposition of FinFETs versus Planar at 20nm is up to 20% performance at the same power consumption, 35% savings in power at the same speed, and 1.1X density. Those my friends are great numbers!

As I mentioned before, FinFETs are the most interesting technology we will see this decade so it was a day well spent. My wife and I stayed on an extra day to enjoy Monterey, which was where we spent our second wedding anniversary many years ago.

Please post your EDPS 2013 Monterey questions, comments, and trip reports HERE!

EVENT PRESENTATIONS

EVENT PICTURES

lang: en_US

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Happy Birthday to Synopsys VIP

Happy Birthday to Synopsys VIP
by Paul McLellan on 04-22-2013 at 3:25 am
Categories: IP, Synopsys

I met Mike Sanie around DVCon time and planned to write a blog about the one year anniversary of Synopsys Discovery VIP which was announced during Aart’s keynote at DVCon in 2012. Eric covered it for SemiWiki here. But Synopsys had other stuff they wanted me to blog about and so it is a couple of months late. The 14th month anniversary isn’t quite so compelling and anniversary.

At DVCon this year they actually had a VIP anniversary party, with Don McMillan (who I knew back when used to be a designer at VLSI Technology back before he became a full-time comedian) and Scott Meltzer and Katrine (and my claim to fame there is that I was the first person to hire Scott for DAC when I was at VaST; he has a degree in computer science from Berkeley before/during he became a full-time performer, so he could actually run the demos himself).

Synopsys created their VIP portfolio since their previous generation was running out of steam and wasn’t written to any sort of uniform standards and so had challenges with performance, debug and coverage. The new generation was all written in SystemVerilog with native-compiled (no wrappers) UVM/VMM/OVM and is much higher performance, 3-6X faster than the old stuff.

There was additional innovation in protocol-aware debug and coverage which I wrote about last year here when it was integrated with SpringSoft’s Verdi. Of course since then, Synopsys acquired SpringSoft.


The release was generally received by both the press (Eric’s blog is very positive, for example) and the verification experts in customer companies. This has resulted in several technical wins at major accounts against entrenched competition. There are lots of press releases announcing some of these on the Synopsys website if you are into that sort of thing. Personally, I’m not. I’ve been in marketing and know how to turn the meat-grinder handle to get quotes to come out the other end and so I pretty much ignore most of any press release other than the basic facts of the announcement. But AMD, Cavium, Freescale, Qualcomm, Broadcom and more are using it.

It is now 14 months later and with a broad portfolio of verification IP this is one of the (if not ‘the’) fastest growing product lines in Synopsys.

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Mentor’s New Embedded Strategy

Mentor’s New Embedded Strategy
by Paul McLellan on 04-22-2013 at 2:01 am
Categories: EDA, Siemens EDA

If there is a trend I can detect in verification in 2013, it is taking verification environments and making the user interface, scripts, and tools work uniformly across the whole spectrum of possible verification “substrates” from virtual platforms, FPGA boards, emulation, actual chips, RTL simulation and so on. Mentor is taking this basic idea up another level to the embedded software developer. Today they have announced the Mentor Embedded Sourcery CodeBench Virtual Edition (try saying that 3 times after a few beers).

Mentor acquired Code Sourcery in 2010, a major player in open-source software development and supplier of the most popular software development environment (or IDE, the I stands for ‘integrated’) used inside major semiconductor companies by their software engineers. It is downloaded 15,000 times a month. It is free, so Mentor doesn’t make any money directly from that.


What Mentor have done is made it so that software engineers can use the CodeBench that they are used to using. But under the hood, they can actually be running on a QEMU-based virtual platform, or on one of Mentors Veloce emulators, or on an FPGA prototype, or on the real silicon, or on a reference design board. RTL is far too slow for software development, but for all I know that might work too.

From the software engineers point of view, all the details of the hardware such as RTL or signal traces, are hidden and he or she only needs to worry about software-like stuff. If a problem is detected that might be a hardware issue, the design engineer can pick up signal traces and dig down into the details without requiring understanding all the software or how to work inside CodeBench.

The basic idea is to give the software engineer just enough information from the hardware that they can get their job done and not have to worry about the hardware or learn lots of alien stuff. And similarly, for the hardware engineer, to let them work in their environments without needing to become an expert on the embedded software environment or code.

I worked for VLSI Technology for years and I like to say that I have silicon in my veins, although by background I’m a programmer. But when I worked at VaST and Virtutech I started to see things from the embedded software developers point of view. For instance, I was at a Cisco supplier conference and the CTO spoke at a keynote. IOS, Cisco’s router operating system, is 25M lines of code and another 30M lines of code to test it (I suppose what we’d call VIP in EDA). The developers of that code neither know nor care what SystemC is, or how you synthesize a chip. It is just a big register map to them. When I did a computer science degree in a galaxy far far away I actually learned some hardware design. Nowadays, I don’t think they teach that stuff. They probably don’t even teach assembly code. If you can do C++, Java and Python you are good. The point I’m making is that the abstraction level the software people work on is so far removed from what the hardware people are doing that it is hard to communicate.


This looks very good to me. Not in the sense that it is rocket science breakthrough technology. But it addresses the social aspects of software/hardware co-design and doesn’t take as a fundamental assumption that the software developers and the hardware developers are in adjacent cubes and speak a common language. Especially, it doesn’t assume that taking hardware design tools and interfacing them to some software environment with a “software engineer” skin is going to work.

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A Brief History of Methodics

A Brief History of Methodics
by Daniel Nenni on 04-21-2013 at 8:15 pm
Categories: EDA, Perforce

Methodics was founded in 2006 by 2 ex-Cadence experts in the Custom IC design tools space, Simon Butler and Fergus Slorach. They had a consulting company called IC Methods, active in Silicon Valley from 2000-2006, and when they needed to create a new company to service a consulting engagement that had turned into a product, they inverted the name and Methodics was born!


Simon Butler, CEO…..Fergus Slorach, CTO

Goals
The original goal was to provide DM interfaces to the Cadence design tools suite to allow the more liberal use of software methodologies in a hardware design environment. Software developers have traditionally been more sophisticated in areas like data management. There are orders of magnitude more users on tools like Subversion, Perforce, Git and others. By building on top of these industry standard solutions Methodics can leverage the much larger software developer space with all the associated benefits of scalability and an extended ecosystem.

First Customer
The first customer was Netlogic Microsystems. Methodics provided Perforce/Cadence data management for 6 design centers across the US and India.

Markets
The markets for IC data management tools are growing – Custom IC design is seeing some major growth with the popularity of smart phones. SoC’s in general are becoming more complex and require better management processes to scale.

The alternative to using data management tools are making manual design copies and manually assembling SoC’s, however these approaches don’t really scale and are not practical with todays designs

Products
Today Methodics has 3 main areas of development. Design data management tools for layout and schematic designers, SoC IP management and IP reuse/integration, and RTL design data management, test/regression and release management

VersIC™ – Design Data Management for layout/schematic designers. VersIC was the first Methodics product and integrates Subversion or Perforce in the Cadence Virtuoso and Synopsys Custom Designer tools-suites. VersIC allows a user to version control their data from within the design environment without any required knowledge of the underlying DM tools. Multi-site teams are supported using the underlying proxy mechanisms available in Subversion/Perforce which yield fast, scaleable data distribution for large IC project data-sets.


Fig.1 VersIC overview

ProjectIC™ – SoC/IP management for designers and integrators. ProjectIC is an enterprise solution for releasing IP’s and cataloging them for reuse, SoC integration, tracking bugs across IP’s and managing permissions. ProjectIC also allows comprehensive auditing of IP usage and user workspaces. With ProjectIC managers can assemble configurations of qualified releases as part of the larger SoC and make this available for designers to build their workspaces. Workspace management is a key technology within ProjectIC and data is populated in minimal time using IP caching and parallel syncs.

Fig.2 ProjectIC Overview

Evolve™ – RTL test, regression and release management. In 2012 Methodics acquired Missing Link Tools, the developers of Evolve – a test/regressions and release management tool focused on the digital space. Evolve supports Subversion, Perforce and CVS DM systems with a Evolve tracks the entire design test history and provides audit capabilities on what tests were run, when and by whom. These are associated with DM releases and provide a way to gate releases based on the required quality for that point in the designs schedule.

Fig.3 Evolve Overview


With these 3 established areas of technology Methodics is uniquely placed to deliver the industries first complete solution for analog/digital design.

Tool Users

IC layout and schematic designers can use the standalone VersIC tool. IP designers, SoC integrators and project managers would use ProjectIC, finally digital designers would use Evolve.