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The Capital Lite Semiconductor Model

The Capital Lite Semiconductor Model
by Paul McLellan on 05-07-2013 at 8:05 pm

For a couple of years the GSA has had working group looking at funding of semiconductor investment. There is a general feeling, which I share, that it is hard to get a fabless semiconductor company off the ground (nobody would dream of trying to create one with a fab these days) due to the size of the investment and the relatively long time to return the investment. In an era when software companies can be created and ramped and sold in a year or so, the time and cost to build a chip and ramp it to volume makes the whole deal unattractive to conventional venture capitalists.

Some of this is driven by what is sometimes called Moore’s Second Law, that as we go down through process generations, the capital required to develop new products increases by 27% from one generation to the next. So in 2000 a semiconductor company could bring a product to market for $10M but now it takes $30M just to get to samples. To make things worse, as ASPs have come down (for the same functionality) that puts pressure on shipping in very high volume, meaning designing complex SoCs that serve multiple markets and contain a lot of semiconductor IP (SIP).

The Capital Lite Working Group has produced a discussion paper called The Capital Lite Semiconductor Model: Revitalizing Semiconductor Startup Investment which looks at this problem and proposes a solution.

One of the largest costs in a chip design is adding non-differentiated IP, the cost of which can exceed pretty much everything else put together. So one challenge is to get this cost down by partnering a large semiconductor company ($100Ms) with the smaller company to both allow undifferentiated IP to be shared and to create a possible new product line for the larger company.


Part 1 of the capital-lite deal structure is Equity for IP (EFI). The largeCo gets the opportunity to further monetize its IP and the StartupCo avoids the cost of all that design. Part 2 is Triggered Royalty License (TRL) which gives LargeCo more opportunity for revenue and for StartupCo balances independence wth capital efficiency. The royalty payments are deferred compared to paying up front for IP, so they only become due once there is revenue available to pay. Finally Equity Finance With Extra Preference (EFEP) creates a spin-in opportunity for LargeCo to absorb StartupCo once it is successful without, in some sense, paying to buy back all its own IP and money.

There are a a lot of details to make this work correctly so that StartupCo’s R&D expenses do not get consolidated into LargeCo’s financial, for example. An example is EzChip which is a publicly traded capital-lite semiconductor company that has partnered with Marvell Technology to reduce its capital intensity by sourcing IP and supply chain operations.

An example of a company creating a whole capital-lite ecosystem is SK Telecom. They have created an Innovation Center by Innopartners. It is a cross between the capital-lite model described above (which is largely driven by StartupCo’s needs) and something more directed by LargeCo. Selected entrepreneurs will be given access and routine collaboration with the top researchers at strategic partner, initial funding and guidance through the early stages, and office and lab space at the partner.

The strategic partner has the opportunity to acquire a tailor-made startup. The strategic partner describes the product required and Innopartners seeks out qualified entrepreneurs to create the startup and deliver the product. Or alternatively, entrepreneurs with an idea can present it to Innopartners in a more traditional manner, who will then seek a strategic partner to make the program viable.


There are various different financial models ranging from a spin-in path where the milestones and price are more or less negotiated up front, to traditional VC model with no exit valuation predetermined, to a standalone path where the startup never really gets completely independent nor is it absorbed.

For more information see the GSA Capital-Lite Working Group Discussion document here. See the SK Telecom White Paper here.


Cell-Aware Test Seminar

Cell-Aware Test Seminar
by Beth Martin on 05-07-2013 at 8:05 pm

You may have heard about cell-aware testing. It’s a transistor-level test (ATPG) methodology that is quickly becoming a hot topic. If you are involved in DFT and are looking for better quality and reliability, you should definitely know about cell-aware testing.


And lucky you, on May 16, 2013, you can attend a free seminar on cell-aware test at Mentor Graphics. It runs from 10:30am to 1:30pm, which means lunch is free too. Go here for details and registration.

Basically, cell-aware test lets you detect faults that occur within standard cells that are often missed with the current models. Mentor and AMD published cell-aware production test results from a 32nm processor last fall, which offers a compelling value proposition (spoiler alert: 885 DPM reduction. Yowza.)

Do you plan to use FinFETs any time soon? I hear that cell-aware testing will likely be a normal part of the DFT flow. Thisrecent article talks about FinFet defect coverage with the cell-aware methodology.

So, read the technical paper and the article, Google it, then sign up for the seminar and bring your questions.


Global Foundries Does DAC

Global Foundries Does DAC
by Paul McLellan on 05-07-2013 at 8:05 pm

Global Foundries will be at DAC in booth 1314. There will be 6 pods there demonstrating:

  • Advanced Technology: 28nm ready and ramping, and next is 20LPM and 14XM.
  • PDKs: For 28nm, 20nm and 14nm. 14nm handles FinFET enablement complexity. Robust, easy to use and high quality, supports pretty much the full range of EDA tools.
  • Design Methodology: all that 20nm stuff like double patterning. And FinFET extraction.
  • Foundry Services: GlobalShuttle advanced multi-project wafer (MPW) for flexible prototyping. Advanced interconnect 2.5D and 3D solutions.
  • ARM/SoC solutions (2 pods) industry leading performance and energy efficient ARM processor-based SoCs accompanied by energy efficient accelerator co-processors for heterogeneous computing.

There will aso be numerous presentations every day on the booth. Some may require pre-registration but there will be an open theater where partners give short presentations on their collaboration with GF. Details will soon be available on the GF DAC microsite.

Throughout DAC there will be presentations by GF employees in various places during the week:

  • Tuesday, June 4, Pavilion Panel, Dave McCann Is This the Right Time to Create Standards for 2.5D/3D-IC Designs?
  • Tuesday, June 4, Synopsys Breakfast, Subi Kengeri and Kelvin Low Two-way collaboration on FinFETs and 14XM
  • Tuesday, June 4, Management Day, Bob Madge Decision-making for complex ICs
  • Tuesday, June 4, Cadence IP Talks, Subi Kengeri Topic TBD
  • Wednesday, June 5, Mentor Panel, Richard Trihy No fear of FinFET
  • Wednesday, June 5, Pavilion Panel, Luigi Capodieci Learn the secrets of Design for Yield

GLOBALFOUNDRIES is the world’s first full-service semiconductor foundry with a truly global footprint. Launched in March 2009, the company has quickly achieved scale as the second largest foundry in the world, providing a unique combination of advanced technology and manufacturing to more than 150 customers. With operations in Singapore, Germany and the United States, GLOBALFOUNDRIES is the only foundry that offers the flexibility and security of manufacturing centers spanning three continents. The company’s three 300mm fabs and five 200mm fabs provide the full range of process technologies from mainstream to the leading edge. This global manufacturing footprint is supported by major facilities for research, development and design enablement located near hubs of semiconductor activity in the United States, Europe and Asia. GLOBALFOUNDRIES is owned by the Advanced Technology Investment Company (ATIC). For more information, visit http://www.globalfoundries.com.


A Brief History of Dassault Systèmes

A Brief History of Dassault Systèmes
by Paul McLellan on 05-07-2013 at 8:05 pm

Dassault Systèmes (DS) was created in 1981 when a small team of engineers were spun out of Dassault Aviation. They were developing software to design wind-tunnel models and so reduce the cycle time for wind-tunnel testing, using surface modeling in 3D instead. The company entered into a distribution agreement with IBM that same year and started to sell its software under the CATIA brand.

Working with large industrial customers they learned how important it was to have design support for the whole range of parts in 3D. The growing adoption of computer approaches to design, especially in automobile and aviation, triggered the vision for transforming 3D part desing into an integrated virtual product design. By 1994 V4 was released, enabling customers to reduce the physical prototypes and have a complete virtual understanding of the product. They also expanded into new verticals, adding fabrication and assembly, consumer good, high-tech, shipbuilding and energy.

In 1996 there was an IPO in Paris also listed on Nasdaq (in 2008 DS voluntarily delisted from Nasdaq).

By 1997 DS was organized into two parts to support the entire product life-cycle. Product Lifecycle Management (PLM) and design-centric for customers seeking to design products in 3D. They also acquired IBM’s Product Manager Software, and created the ENOVIA brand.

In 1999 was the initial launch of version 5, a new architecture software platform for PLM designed for both Windows NT and Unix environments. They also expanded the ENOVIA product line with the acquisition of Smarteam for small and medium sized businesses.

In 2000 DS created the DELMIA brand addressing digital manufacturing (digital process planning, robotic simulation and human modeling) and in 2005 the SIMULIA brand addressing realistic simulation.

In 2006 DS acquired MatrixOne, a global provider of collaborative PLM software and services to medium to large organizations. Prior to acquisition by DS, MatrixOne had acquired Synchronicity in 2004 which was focused on managing the value chain for electronics products, especially semiconductor.

In 2007 DS started to take control of their own distribution (at this point IBM was distributing around 50% of their product) which ended in 2010 by them acquiring IBM PLM, the business unit exclusively dedicated to sale and support of DS’s PLM software, although they also signed a global alliance agreement with IBM extending their cooperating in professional services, cloud computing, middleware, flexible financing had hardware.

Various other acquisitions took place, including Netvibes in early 2012 and Tuscany Design Automation in late 2012. Netvibes had intelligent dasboarding and Tuscany’s PinPoint product added dashboarding and design lifecycle management for SoCs. Several large semiconductor companies are using PinPoint for leading edge designs.

The combination of MatrixOne (with Synchronicity) along with Netvibes and PinPoint should lead to powerful tools for making the design process more comprehensible and efficient.

Dassault Systèmes corporate mission is to provide Businesses and People with 3DExperience universes to imagine sustainable innovations capable of harmonizing products, nature and life. A growing number of companies in all industry verticals are evolving their innovation processes to imagine the future both with, and for, their end-consumers.


Sage Design Automation iDRM Launch

Sage Design Automation iDRM Launch
by Daniel Nenni on 05-07-2013 at 7:00 pm

This is an example of what I do during the day. I work with emerging companies on disruptive technologies and help launch them into the fabless semiconductor ecosystem. This product, iDRM, is the result of three years of joint development work amongst three semiconductor foundries and some of their top customers:

Continue reading “Sage Design Automation iDRM Launch”


Sandisk and NetworkComputer

Sandisk and NetworkComputer
by Paul McLellan on 05-07-2013 at 12:33 pm

Robert Veltman and Vikash Tyagi of SanDisk Corporation presented at SNUG a few weeks ago on their selection and use of RTDA’s NetworkComputer to manage their workflows.

Like everyone else, SanDisk has a high-performance computing farm (and like everyone else they are coy about how big it is) and lots of licenses for EDA tools, simulation in particular. You probably know that EDA tools use FlexLM to keep track of license use. A load balancer has to direct the workload to suitable execution hosts based on both hardware resource availability and license availability.

There are a number of problems that can occur. First is license under-utilization. If there are per-user limits but the number of users goes down then licenses can go unused. Users will also bypass the load balancer if the submit-to-execute time is too long, such as longer than the job runtime. And licenses cannot be shared among remote sites.


SanDisk’s requirements for a load balancer were:

  • can manage the hardware and software resources
  • pre-emption capability (stop a current job and run another)
  • high-performance job scheduling (very short submit to execute delay when resources are available)
  • flexible in adapting to different organization and business models
  • global deployment with central software resource management

The two well-known load balancer tools are SGE (from Oracle) and LSF (these days owned by IBM) but they both failed to meet the high performance job scheduling needs, were not integrated with the FlexLM license manager, and hard to deploy globally. SanDisk evaluated and decided to use RTDA’s NetworkComputer (NC) which met all requirements.

So what has been their experience with NC?

Pre-emption is the ability to suspend a workload in order to free up hardware and software resources for another workload. In particular, the licenses are taken back from the pre-empted workload and then, when eventually it is resumed, it needs to re-acquire them and carry on as if the whole pre-emption had never happened.

Fairshare is used for license sharing among users when there is contention. Fast-fairshare uses pre-emption to balance loads immediately, even up to allowing a single user to consume all available licenses but balancing the load among multiple users required. With no user limit this promotes submitting workloads sooner rather than later so they get to benefit from any slack periods.


Fast-fairshare is implemented to allocate any excess licenses to sites where it is day (so the users are presumably around) rather than night (where presumably the workload is all queued up and new jobs are unlikely to arrive before morning).

Global license sharing is supported by NC. Each site gets a minimum license allocation and unused licenses go to the site with the highest demand. Pre-emption forces minimum allocation when required. There are some minor gotchas: sites with insufficient hardware can’t benefit from surplus licenses, there is a limit on the number of sites, and so on.

The results have been good. License utilization has increased since deploying NC. The scheduling is very fast and eliminates the need for out-of-queue jobs. There is an efficent way to share licenses among different sites. Workloads can be balanced instantly.

Bottom line: using NC’s built-in functions with some in-house developed software automation delivers corporate-wide advanced load balancing.

The SanDisk SNUG presentation and the accompanying white paper, both of which contain a lot more technical details, are here.


Training Day at DAC

Training Day at DAC
by Paul McLellan on 05-07-2013 at 12:15 pm

This year for the first time the Thursday of DAC is tranining day. So that would be June 6th in Austin, of course. There are four tracks of training focused on SystemC, ARM Cortex and two on SystemVerilog, all areas of increasing use in SoC design, especially in mobile.

Each track of training is divided into two parts, one held from 9am to 12.30pm, and then a second part from 2pm to 5.30pm. All sessions are taught by a professional educator from Doulos (along with an engineer from ARM for the ARM track) who is the global leader in the development and delivery of training solutions for engineers creating electronic products.

The four tracks are:

  • Track 1: SystemVerilog

    • Part 1: Synthesis-Friendly System Verilog.
    • Part 2: A Hardware Designers Guide to SystemVerilog Verification
  • Track 2: SystemVerilog Verification

    • Part 1: Hardcore SystemVerilog for Class-based Verification
    • Part 2: Getting Started with UVM, the Universal Verification Methodology
  • Track 3: ARM Accredited Engineer Program

    • Part 1: Kick Start to the ARM Cortex Processor Family
    • Part 2: Software Development for the ARM Cortex Processor Family
  • Track 4: ESL and SystemC, the Definitive Guide to SystemC

    • Part 1: The SystemC Language
    • Part 2: TLM 2.0 and the IEEE 1666.2011 Standard

Details of all the training courses, including summaries and presenter biographies and room numbers, are all on the DAC website here. You can sign up for one of the training courses when you register for DAC.

Doulos also produce Golden Reference Guides to these sorts of topics:

  • UVM – Full Edition, supporting version 1.1.
  • VMM fully supporting version 1.2.
  • OVM fully supporting OVM 2.0
  • SystemC IEEE 1666™-2006 compliant, supporting version 2.2
  • SystemVerilog supporting SystemVerilog IEEE Std 1800™-2009
  • PSL supporting v1.1
  • VHDL
  • Verilog

Details of the guides are available here. They are $50 each.


Agilent ADS Integrated with ClioSoft

Agilent ADS Integrated with ClioSoft
by Paul McLellan on 05-07-2013 at 4:00 am

I talked to Greg Peterschmidt of Agilent today about their integration of Advanced Design System (ADS) with ClioSoft’s SOS Design Data Management that was announced today. The integrated product is known as SOS viaADS. Greg is the ADS Product Planning Manager.

ADS is the market leader for design of very high frequency stuff such as RF and Microwave and the fastest digital. It is not just IC design since at those frequencies everything interacts with everything else and so a design may consist of a circuit board with a module containing several chips in different technologies, all of which needs to be analyzed together. Ten years ago designs were a few transistors and some matching networks and data management wasn’t a challenge. Now designs are much more complex, groups are globally distributed and so data management needs to be tightly integrated into the design system itself, which is what Agilent and ClioSoft have done.

It turns out that like me, Greg actually worked in this area himself in a past life. He was at EDA Systems that tried to do universal data management but without being integrated into all the design systems it was an uphill struggle and eventually the company was folded into Digital Equipment. They were one of the people who pushed the CAD Framework Initiative (CFI) to try and get some standardization into the way tools accessed data. At the time it didn’t really go anywhere much and CFI eventually morphed into SI2.

There is a perception that this sort of data management is just for large teams but in fact, since engineering is an experimental discipline, even small teams (or just an individual) need to be able to keep track of different versions and roll back designs to something that was working.

ClioSoft’s SOS viaADS product provides users of ADS 2012.08 or later with seamlessly integrated design management. Users have easy right-click menu access to version control capabilities within the standard ADS user interface. Design management features include:

  • Version control of libraries, cells and views
  • Auto check-out and check-in when a view is edited
  • Check-out locks to prevent concurrent changes
  • Easy rollback to previous revisions
  • Data management operations for an entire design hierarchy
  • Release and derivative management
  • External reference and reuse
  • Multi-site global collaboration

The product page for the integration is here.

Also Read

Data Management for Designers

Modern Data Management

Cadence ♥ ClioSoft!


CDN Live 2013 in Munich: what’s the next acquisition? Evatronix!

CDN Live 2013 in Munich: what’s the next acquisition? Evatronix!
by Eric Esteve on 05-07-2013 at 2:44 am

It was definitely a good idea to go to Munich to listen to the keynote talk from Lip-Bu Tan. Did I learned in direct live the name of the next acquisition from Cadence in 2013, after Tensilica and Cosmic Circuits? Yes and the winner is… Evatronix! And cadence as well as Evatronix is enjoying more than 600 customers worldwide, thanks to a wide port-folio ranging from 8051 IP core to SuperSpeed USB Controller, or Flash Memory controller IP.


Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced its intent to acquire the IP business of Evatronix SA SKA, adding to its rapidly expanding IP offering. Based in Poland, Evatronix delivers a silicon-proven IP portfolio, which includes certified USB 2.0/3.0, Display, MIPI, and storage controllers, which are highly complementary to Cadence’s IP offering.

HIGHLIGHTS:

  • Evatronix is an established provider of USB, MIPI, display and storage controller IP with a broad customer base of approximately 600 customers.
  • Nearly 200 USB controllers licensed to customers, including several top-tier semiconductor companies.
  • Evatronix’s controllers, combined with PHYs from Cadence, will enable a complete interface IP solution that combines controller, PHY, verification IP and integration kits.

“The rapid innovations in the mobile, connectivity and cloud markets are driving today’s IP marketplace,” said Martin Lund, senior vice president of research and development, SoC Realization Group. “Evatronix’s IP products will boost Cadence’s offering for these segments, with high quality leading-edge IP that is production-proven.”

Evatronix co-founder and president Wojciech Sakowski said, “Evatronix’s IP cores and services are designed for ease-of-integration, quality and time-to-market. As part of Cadence, we will be able to reach more customers globally and to accelerate our IP roadmaps. The integration with Cadence will allow our customers to get to market faster with less effort.”

The acquisition is expected to close in the second quarter of 2013, and is not expected to have a material impact on Cadence’s balance sheet or second quarter or fiscal 2013 results of operations. Terms of the transaction were not disclosed.

More to see on:http://www.evatronix-ip.com/

On my side I am polishing the presentation I will make in the Design and Verification IP tracks. This year is the first with a special attention about IP and Verification IP: PCIe and M-PHY, USB 3.0 PHY IP, Memory Models for Verification and DDR SDRAM Memory Controller and PHY IP, and the related Verification IP with a presentation from Susan Peterson from Cadence. It will also be a good opportunity to learn about Tensilica Dataplane CPU and I am sure not to miss that track, as I will make the presentation just before, named “Interface IP protocols: the winners, the losers in 2012”. It will be strongly updated from the presentation made during IP-SoC last December in Grenoble, as many changes have occurred during Q1 2013! Because we can now take into account the 2012 actual IP sales results for the various protocols (DDRn, USB, PCIe, SATA, MIPI, Ethernet, Thunderbolt, HDMI, DP), it will be fresh information, in advance from the launch of the “Interface IP Survey”…

Eric Esteve from IPNEST

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DAC 2013 Pavilion Panel: Affiliation Avenue – The Road to Success!

DAC 2013 Pavilion Panel: Affiliation Avenue – The Road to Success!
by Holly Stump on 05-06-2013 at 7:00 pm

Join us for a free career-building panel at DAC 2013, sponsored by Women in Electronic Design.
· Don’t go it alone! How many times have you heard it?


A lively panel of luminaries discuss how alliances are critical to our success, and cover networking and negotiating skills for achieving personal satisfaction and professional visibility. Also hear various perspectives on the importance of nonsense, and how to consciously incorporate humor and joy into your work life.

An informative and inspiring event for both women and men, in electronics and EDA, at any stage in your career.

Moderator:
·Sashi Oblisetty, Director, R&D, Synopsys. Previously, Sashi was President and CEO of VeriEZ Solutions, Inc.; VP & GMat TransEDA New England Design Center; and Founder, President & CEO DualSoft LLC. Education: B.Tech Electronics and Communication Engineering, Birla Institute of Technology, and MS Electrical and Computer Engineering, University of Massachusetts

Panelists:
· Soha Hassoun, Associate Professor, Dept of Computer Science, at Tufts University. Soha’s research interests lie in EDA and applying EDA techniques to Systems Biology. Soha has been a consultant at Carbon Design Systems; visiting researcher at IBM Research Labs; consultant at IKOS (now Mentor); Senior Design Engineer at Digital Equipment Corp.; Soha is an NSF CAREER award recipient. She hasserved in many technical and executive leadership positions within EDA. Education: PhD Computer Science and Engineering, University of Washington,MSEE, Massachusetts Institute of Technology.

· Jan Willis, President, Calibra. Previously Jan was Sr. VP, Industry Alliances at Cadence Design Systems; Vice President, Business Development for Simplex Solutions; Director, Product Marketing and Business Development at Synopsys; and Manager, Worldwide Customer Support for Hewlett-Packard. Education: MBA from Stanford University Graduate School of Business and BSEE, Electrical and computer engineering, University of Missouri-Columbia.


· Kavita Snyder, VP, Worldwide Applications, BluePearl Software. Previously, Kavita was President & CEO at KnowFolder; Technical Account Manager at Magma Design Automation; Director of Field Operations at Jasper Design Automation; FAE Director at Atrenta; Product Marketing Manager at Synopsys; and Field Applications Manager at Synplicity. Education: BS, Computer Engineering, San Jose State University.

Affiliation Avenue will be followed by a presentation of the Marie Pistilli Award to Nanette Collins, the 2013 recipient. Women have made important contributions and strides in the EDA industry. The DAC Executive Committee presents an annual award to honor an individual who has made significant contributions in helping women advance in EDA technology. Ann Steffora Mutschler, Senior Editor at System-Level Design, will interview Nanette Collins, the 2013 Marie Pistilli Award recipient.

Attend these fascinating panels on Monday, June 3, at 1:30pm, DAC Pavilion, DAC 2013 Austin,Texas. www.dac.com

And please join the Electronic Design Women Linked In group.

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