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Semiconductor Expert Forum

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Cadence’s System-to-Silicon Verification Summit

Cadence’s System-to-Silicon Verification Summit
by Randy Smith on 10-06-2013 at 6:00 pm
Categories: Cadence, EDA

At this year’s DAC, I spoke with several friends at Cadence. I got the distinct impression that something at Cadence had changed. There was a sense of pride and accomplishment that it seems to me had drifted away over the years. Now employees were speaking with true conviction about the accomplishments of the product development teams and the results of the company’s renewed focus on R&D the past couple years. So, it was with high expectations that I attended the System-to-Silicon Verification Summit held at the auditorium in Cadence Building 10 in San Jose on September 26, 2013. I was not disappointed.

The event was led by Brian Fuller, Cadence’s new editor-in-chief. Opening remarks were provided by Charlie Huang who recently became responsible for the System & Verification Group at Cadence, in addition to his role leading Worldwide Field Operations. This was followed by presentations by keynote presentations, first by Jim Hogan and then by Brian Bailey who gave their views as to the scale and importance of verification in today’s complex system designs. Gary Smith also participated on a panel in the afternoon and there were presentations by representatives of nVidia, Broadcom, Zenverge, and Ambrella, as well as, of course, Cadence.

One trend in the discussions and presentations was the importance of verification places to include software. This is not new, but it is certainly becoming increasingly prominent. When I was VP, of Sale & Marketing at TriMedia (a Philips Semiconductor spin-off), we made it a requirement to use emulation (Cadence Palladium) of the hardware to prove we could boot the operating system. We had the further challenge of verifying the device drivers for much of the IP connected to the system bus. The diagram below from Jim Hogan’s presentation illustrates the many layers of testing and the relationship to software in the system verification process (click on the picture to zoom in).

Related to this topic, on one side of the stage was a new Cadence Palladium XP 2. This system is a remarkable engineering achievement itself. For the recent product announce, click here. Cadence claims that the new Palladium XP II platform delivers 2X increase in verification productivity, resulting in up to four months faster time to market, and the Enhanced System Development Suite delivers up to 60X speed-up for embedded OS verification and 10X performance increase in hardware/software verification. I wish we had had a box like that at in our hands at TriMedia.

The panel discussion was quite lively. I think the primary take away from the panel discussion was the increasing reliance on ‘use cases’ or ‘scenarios’. It was suggested that Apple is using approximately 50,000 scenarios in the development of its iPhones. The point is that it is impossible to test all possibilities when you consider the large amount of software content, the interactions between different modes and applications. It is important however to test the application scenarios that are most likely to occur. This is much different than the old fault coverage paradigm. Verifying without knowledge of the software application to be ran on the system is simply not adequate. This is true in the verification of functionality, performance, and power. This seems to be where the older verification strategies employed in more constrained industrial designs is diverging from the strategy needed in the high software content consumer area, ultimately leading to the coming complexities of the Internet of Things (IoT).

It is not possible to repeat in this short article all of the valuable information presented at this event. It also looks like these summits will be coming Cadence on a somewhat regular basis. Those with an interest in mixed signal design should register for the upcoming Mixed-Signal Technology Summit also to be held on Cadence’s San Jose campus on this coming Thursday, October 10.

lang: en_US

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A Big Thank You to EDA and IP

A Big Thank You to EDA and IP
by Daniel Nenni on 10-05-2013 at 10:00 pm
Categories: EDA, IP

Electronic Design Automation Software and Semiconductor Intellectual Property are not so much the tail that wags the dog, rather they are like the heart of an elephant, tiny in comparison but without which there is no elephant. There is no doubt that EDA and IP have been key enablers of the semiconductor industry for the past 50 years so what better time to celebrate our achievements!

True story: When my son invited me to career day at his elementary school he asked me what I did for a living. After I explained EDA and what I did he went silent then said, “Dad, you fly planes, right? Can you talk about that?” I talked about airplanes and we all made paper ones and tossed them around the classroom. It was a good thing that I did because the other father was a Fireman (coincidently my son is now a Fireman).

Fortunately, with smartphones, I’m a rock star now. My kids get new iPhones every two years for Christmas and I’m the only Dad around that actually knows what is inside them and what new features are coming around the corner. Thank you EDA and IP!

As Paul McLellan wrote in “Back to the Future: 50[SUP]th[/SUP] Anniversary of EDA”, EDAC is hosting an event to celebrate 50 years of EDA on October 16[SUP]th[/SUP] at the Computer History Museum:

Nearly five decades ago, a new era in electronics innovation was born: Electronic Design Automation (EDA). And the world has never been the same. Before EDA, integrated circuits were designed by hand and manually laid out. EDA changed all of that, providing ways to automate the design process and take electronics to places never dreamed possible.

Join us at this sure-to-be unforgettable party hosted by the EDA Consortium as we recognize the EDA industry and its rich history. Special guests include industryluminaries and alumni who will join with present day members of our community to celebrate the past, look to the future, connect with old friends and make new ones. Festivities include a retrospective from Bill Joyner, entertainment and anauction to raise funds for the preservation of EDA history by the Computer History Museum.

In 1989 the EDA Consortium (EDAC) was founded “To promote the health of the EDA industry, and to increase awareness of the crucial role EDA plays in today’s global economy.” Well they are certainly doing that here so let’s give them our full support. My beautiful wife Shushana and I will be there and it would be a pleasure to meet you!

lang: en_US

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Synopsys: Getting To Know EDA’s Heavyweight Champion

Synopsys: Getting To Know EDA’s Heavyweight Champion
by Ashraf Eassa on 10-05-2013 at 8:00 pm
Categories: EDA, Synopsys

From chip IP vendor ARM Holdings to semiconductor foundry Taiwan Semiconductor, there have been many winners from the mobile device revolution that was sparked by Apple’s introduction of the iPhone. However, while these big-ticket names get all the fame and glory, the electronic design automation space (“EDA” for short) is filled with winners. In short, the EDA companies provide the tools that integrated circuit designers use to actually design and verify their products. In the first part of this three part series on the EDA vendors, I’d like to talk about Synopsys – the leading EDA vendor by revenue.

An Overview
Synopsys was founded in 1986 by David Gregory and Dr. Art J. de Geus (current Chairman and CEO) and a squad of engineers from General Electric’s Microelectronics Center. Since then, through organic growth, a merger with Avanti Corporation, and a broad swath of acquisitions (too many to list!), Synopsys has become the world’s largest EDA tool vendor, with annual revenues just shy of $2B and net income well north of $200M.

So, what is Synopsys all about, exactly? Well, while I refer to it as an EDA company, a much more appropriate term for it would be an EDA andIP company. Indeed, a look at the breakdown of Synopsys’ revenue base reveals that while EDA tools are the firm’s bread and butter at 62% of revenues during fiscal 2012, the company is growing its manufacturing solution, professional services, and IP and system level solutions businesses at a rapid clip, as shown here:


(Source: Synopsys 2012 Form 10-K)

With this in mind, I’d like to dig into each of these individual product/business segments:

Core EDA
The circuit design process is incredibly sophisticated and consists of a number of rather complex steps from the definition of the architecture to the actual circuit layout. To facilitate this process, Synopsys offers two product lines: the Galaxy Design Platform and the Discovery Verification Platform.

The Galaxy Design platform is a product suite that includes the entire gamut of tools required to design an integrated circuit.

It’s a single, integrated solution that not only comes with a robust set of Synopsys-designed tools, but it also allows chip designers to integrate other third-party as well as home-grown tools. Included in this suite are:

· IC Compiler, which is a tool used for place and route. In IC design parlance, placement refers to the actual placement of the circuitry and logic in a given amount of space. Routing, on the other hand, involves actually “connecting” up all of the different elements per the specification of the manufacturing process (“design rules”).
· Design Compiler ®, a logic synthesis tool. What this does is it takes register transfer level (RTL) description of an IC and cranks out the corresponding logic gates.
· Galaxy Custom Designer, which is a physical design solution for analog/mixed signal designs
· PrimeTime/PrimeTime SI, a suite of products used for timing analysis
In addition to the design tools, Synopsys also provides what it calls the Discovery Verification platform that provides a suite of verification products.

This includes the following tools:

· VCS ®, an RTL verification solution. The term “RTL” (register transfer level) refers to a model of a given IC design in terms of the flow of data between hardware registers and the operations performed on that data
· CustomSim™ FastSPICE which is a circuit simulation/analysis tool
· CustomExplorer™ Ultra, which is a mixed signal regression/analysis tool
· Formality® which is a formal verification sign-off solution

While the percentage of revenues that these tools comprise of Synopsys’ revenue has declined (as its other businesses have ramped), make no mistake – the demand for these tools is quite robust. As the design challenges continue to mount as the industry transitions to FinFETs, the need for more sophisticated EDA tools to get designers through many of the challenges found there is insatiable.

Interestingly, at TSMC’s Open Innovation Platform Ecosystem Forum, TSMC presented a rather interesting chart that showed how far along the three major EDA tool vendors were for developing tools for TSMC’s 16nm FinFET design flow:

Synopsys, as far as TSMC’s FinFET goes, seems to be leading the pack – with Cadence Design Systems a close second and Mentor Graphics in third.

Interestingly enough, on Synopsys’ recent earnings call, CEO Aart J. de Geus notes that 90% of 20nm and below tape outs have used Synopsys, and that the company was already well engaged in 14/16nm FinFETs and even “all the way down to 10-nanometer”. While Mentor and Cadence are certainly formidable competitors that will continue to gain traction as their toolsets gear up for the next generation processes, it looks as though Synopsys continues to maintain its technology lead (no doubt helped by the fact that Synopsys tools were used extensively on Intel’s FinFET chips), as it has already taped out FinFET test chips with Samsung as well as UMC using its tools.

IP and System-Level Solutions
In addition to supplying design and verification tools, Synopsys also is a major player in the semiconductor IP market. Its DesignWare® IP portfolio is loaded to the brim with IP for everything from configurable processor cores, system-on-chip infrastructure IP, interconnect fabric, and various system interfaces such as USB, PCI Express, SATA, and Ethernet. While in the EDA tool space, Synopsys largely competes with Mentor Graphics and Cadence Design Systems, on the IP side of things the company is actually largely competing with firms’ internally designed solutions.

Keep in mind that Synopsys is actually the largest supplier of physical IP – double its nearest competitor. Further, within the top 20 semiconductor vendors, Synopsys’ IP has actually increased fivefold. As far as the overall IP space goes (not just physical IP), Synopsys enjoys a very comfortable #2 position. All told, IP is a double-digit revenue growth business for the company, as it continues to drive leadership in interface, embedded memories, and analog IP (only 50% of the IP blocks in these areas are outsourced, so there’s further room for growth there).

In addition to being a major IP provider, Synopsys also provides a significant amount of tools, models, and services in order to facilitate the system-level design. For example, the firm’s Platform Architect™ software enables designers to quickly explore various architectural trade-offs for a given system-on-chip. In addition to this, the company offers tools for algorithm design, processor design, and high level synthesis.

Manufacturing Solutions and Professional Services
Synopsys also provides products and technologies to help drive production-worthy yields at the semiconductor manufacturing companies. The products offered here include process simulation, mark data preparation, yield management tools, and optical proximity correction.

Finally, the company offers consulting and design services to its customers at any point in the system-on-chip design process. In addition, the company offers training and workshops to help customers more effectively utilize the latest tools and methodologies.

Let’s Talk Financials
While my background is technical, my work is largely on the financial side of things trying to bridge the company and the technology with the share price. Not surprisingly, Synopsys trades near all time highs, largely commensurate with the trend in Free Cash Flow (that is, operating cash flow minus capital expenses) and a generally very favorable operating environment. The demand for EDA tools and IP is still very healthy, and as the market leader, Synopsys has been a very clear beneficiary of this trend (although more bearish investors/analyst might think that this just means that there’s more to lose than to gain – I don’t necessarily subscribe to that notion).

However, while Synopsys has been a terrific investment over the last several years, how much upside is there going forward? Well, I’d actually like to look at the stock from a number of different perspectives.

So, in the investment community, you really have a couple of types of folks. First, you have individuals who care a lot about following trends in the share price and then riding that trend. Generally speaking, while the supply/demand for a particular stock is sometimes “disconnected” from what, say, a more “fundamental” valuation approach would yield, they are still usually quite related. A company with a healthy and growing business that has a good overall “story” behind it (in Synopsys’ case, it is a leader in a market that is growing very well) is usually one whose stock chart will show all of the tell-tale signs of being on an “uptrend”. Typically when a stock is in an “uptrend” this means that while the stock may gyrate based on, say, day-to-day economic news, the trend will generally be up and the stock chart itself will embed many “clues” as to how traders/investors feel about the stock (these signals are called “technicals” and there are financial professionals who primarily concern themselves with “technical analysis”). Such clues typically involve the share price tending to stay above certain moving averages, and the moving averages themselves exhibiting a nice ordering within themselves (i.e. it is a good thing when shorter term moving averages are higher than the longer term moving averages).

Shares of Synopsys are as healthy as it gets from a technical perspective:

Notice how the shorter term moving averages are cleanly higher than the longer term ones? Also note that when there was a major “drop” in early September below that 50-day moving average (a critical one for investors to watch) the shares quickly bounced right back and has traded solidly above it? This signals to me that as long as the broader macroeconomic environment is in decent shape, the stock is likely to be an excellent one to “buy on dips” (barring, of course, some “bad news” from the company).

Now, from a more fundamental perspective, I’m looking for mid-to-high single digit long-term growth in core EDA tools and double-digit growth in IP. While of course I expect that there will be the occasional spikes/troughs in the sales there, I do expect the trend to be “up” for as long as the macroeconomic environment doesn’t collapse and as long as Moore’s law doesn’t drop dead (TSMC and Intel seem to think we’ve got at least 10 years, so I’m not too worried). So, when I go ahead and run a quick discounted cash flow analysis (the idea behind this is that I estimate what sort of growth in free cash flow that I expect over the next five to ten years or so and then determine what a more “long term” growth rate will be), with the assumption of ~10% FCF growth over the next 10 years and then 8-10% long term. Depending on how aggressively you want to choose your discount rate (the idea is that future cash flows are “discounted” to get a value in today’s dollars), I can justify a fair value of between $39/share and $46.36/share. It’s clear that investors are already pricing in a pretty decent amount of long term growth.

Interestingly enough, after I finished my due diligence on the name, I took a peek at the price target ranges that the sell side analysts, and the range among the analysts who cover the stock is $40 – $45, suggesting that they’re probably thinking about the stock in a similar way to what I’ve proposed above.

The Bottom Line
Synopsys is the EDA tool leader and a leader in IP (#1 in physical, #2 in all IP), and is quite frankly just a high quality company – and it’s certainly priced like it. The company continues to post record sales, which acts as a positive feedback loop – with greater sales, more can be spent on R&D and sales representatives, which in turn drives even higher sales, especially in an environment that is highly favorable for all of the EDA tool vendors. That being said, while Synopsys is the “top dog”, this fact doesn’t make Mentor or Cadence any less interesting (these two have also been wildly successful riding this broad secular trend). In fact, stay tuned for parts 2 and 3 of this series for a look at Synopsys’ two biggest competitors.

More articles by Ashraf Eassa…

Also Read: A Brief History of Synopsys

lang: en_US

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High resolution Analog CMOS IC Design

High resolution Analog CMOS IC Design
by Daniel Payne on 10-04-2013 at 5:02 pm
Categories: EDA, Tanner EDA

My background includes transistor-level IC design, so I take delight in talking with engineers like Dr. Lanny Lewyn that are still practicing the art and science of analog IC design. Dr. Lewynis a Life Senior Member of the IEEE and has a consulting business. If you live in Santa Clara, then consider attending a live seminar on October 24th at Techmart, it’s sponsored by Tanner EDA and SemiWiki founder Daniel Nenni will also be present along with Eric Kurth, Design Manager at FLIR Systems.

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TSMC OIP 2013 Trip Report!

TSMC OIP 2013 Trip Report!
by Daniel Nenni on 10-04-2013 at 4:00 pm
Categories: Foundries, TSMC

The 5[SUP]th[/SUP] annual TSMC OIP Forum was last week and thankfully there were no surprises with the exception of how many people asked me who I think will be the next TSMC CEO. Certainly I have no idea but I would be happy to use my incredible powers of deductive reasoning to determine who it will be.

The TSMC Open Innovation Platform® (OIP) Ecosystem Forum brings TSMC’s design ecosystem member companies together to share with our customers real-case solutions for customers’ design challenges and success stories of best practice in TSMC’s design ecosystem.

First the conference, as I have written before 20nm is ramping, exceeding expectations. We will see production 20nm FPGAs and mobile devices in Q1 2014, absolutely. This comes not only from TSMC’s Jack Sun and Cliff Hou, but also from the fabless crowd: Bob Maines of Oracle, Brad Howe of Altera, VJ Janapaty of LSI Logic, Esin Torfioglu of QCOM, and Sandeep Bharathi of Xilinx. Always listen to the crowd, never listen to the press, especially EETimes.

It is very sad to see EETimes go the tabloid journalism route of late. As you can see their Alexa ratings are dropping as people chose to read articles about semiconductors written by people who actually work in the semiconductor industry:

EETimes
2012 Rank: 24,870
2013 Rank: 26,573

Bounce Rate 65.30%
Daily Pageviews per Visitor 1.82
Daily Time on Site 2:09

SemiWiki
2012 Rank: 431,594
2013 Rank: 183,805

Bounce Rate 42.20%
Daily Pageviews per Visitor 6.10
Daily Time on Site 10:28

DeepChip
2012 Rank: 1,175,172
2013 Rank: 1,736,007

Bounce Rate 70.80%
Daily Pageviews per Visitor 1.70
Daily Time on Site 2:33

As I have mentioned before, 20nm will be a short node as the mobile companies will quickly transition to FinFETs making 28nm one of the longest and most profitable nodes we will ever see. 28nm ramped much faster than 40nm and I expect 20nm to be a quick ramp as well with iProducts shipping a butt load of 20nm SoCs in Q4 2014. TSMC will own 20nm as it did 28nm, but again, it will be a short node.

Also Read: TSMC Awards Berkeley Design Automation

16nm is also on track. Cliff went into significant detail about the status of 16nm PDKs and IP leaving little doubt that we will be ready to tape-out this quarter. Cliff also gave a status of CoWos (resounding success) and 10nm was again committed for 2015 but it really is too soon to say for sure. One thing I do know is that 10nm will not involve EUV and will require triple patterning.

According to the Silicon Valley crowd, Samsung and TSMC are both getting FinFET tape-outs this quarter. TSMC is a little behind Samsung in releasing the 1.0 PDK but Samsung’s 1.0 PDK is having correlation issues so this race will be a photo finish. This type of competition is what keeps us fabless folks strong, absolutely.

One other thing I wanted to mention before I go back into the trenches; there is a TSMC article on Seeking Alpha that is definitely worth a read:

Taiwan Semiconductor Looks Undervalued Ahead Of Key Drivers

Paul McLellan and I met the author at IDF last month and had a somewhat heated discussion on the importance of the fabless semiconductor ecosystem. I provided him with an advance copy of our book “Fabless: The Transformation of the Semiconductor Industry” and after many discussions and focused research he now has a much better understanding of what we do. Expect more ecosystem related articles from him on SemiWiki in the coming weeks.

Ah, no room for my TSMC CEO transition analysis. It turned out to be quite lengthy, a blog in itself, so I will post it next weekend if you all are still interested.

lang: en_US

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Computer History Museum Party!

Computer History Museum Party!
by Daniel Nenni on 10-04-2013 at 3:00 pm
Categories: EDA

More details are now available for the EDA 50[SUP]th[/SUP] anniversary event on October 16[SUP]th[/SUP]. If you have not been to the museum lately this is a must see event as it is all new. Definitely check out the auction items! Just do not bid against me or it will get very expensive for one of us. I’m watching Storage Wars reruns so I will be ready to drop a big one on ya!

Join us at this sure-to-be unforgettable party hosted by the EDA Consortium as we recognize the EDA industry and its rich history. Special guests include industry luminaries and alumni who will join with present day members of our community to celebrate the past, look to the future, connect with old friends and make new ones. Festivities include a retrospective from Bill Joyner, entertainment and an auction to raise funds for the preservation of EDA history by the Computer History Museum.

This special black-tie optional evening will begin with a private opening of the Revolution Exhibit for guests and will follow with a reception, silent and live auctions and dinner in the Grand Hall of the Computer History Museum.

[TABLE] cellspacing=”5″ style=”width: 700px”
|-
| style=”width: 20.0%” | DATE AND TIME:
| style=”width: 30.0%” | Wednesday, October 16, 2013
| style=”width: 50.0%” |
|-
| style=”width: 20.0%” |
| style=”width: 30.0%” | Revolution Exhibit private opening
| style=”width: 50.0%” | 5:30 – 6:30 PM
|-
| style=”width: 20.0%” |
| style=”width: 30.0%” | Reception
| style=”width: 50.0%” | 6:00 – 7:30 PM
|-
| style=”width: 20.0%” |
| style=”width: 30.0%” | Dinner
| style=”width: 50.0%” | 7:30 – 8:30 PM
|-
| style=”width: 20.0%” |
| style=”width: 30.0%” | Program
| style=”width: 50.0%” | 7:50 – 8:30 PM
|-
| style=”width: 20.0%” |
| style=”width: 30.0%” | Auction
| style=”width: 50.0%” | 8:30 – 9:30 PM
|-
| style=”width: 20.0%” |
| style=”width: 30.0%” |
| style=”width: 50.0%” |
|-
| style=”width: 20.0%” | LOCATION:
| style=”width: 30.0%” | Computer History Museum
| style=”width: 50.0%” |
|-
| style=”width: 20.0%” |
| style=”width: 30.0%” | 1401 N Shoreline Blvd.
| style=”width: 50.0%” |
|-
| style=”width: 20.0%” |
| style=”width: 30.0%” | Mountain View, CA 94043
| style=”width: 50.0%” |
|-
| style=”width: 20.0%” |
| style=”width: 30.0%” |
| style=”width: 50.0%” |
|-
| style=”width: 20.0%” | COST:
| colspan=”2″ | Individual seats for the event are $200 for EDAC Members and $250 for non-members.
Group seats of 10 are offered at $1,750 for EDAC members and $2,250 for non-members. Reserve your seat today >
|-
| style=”width: 20.0%” |
| style=”width: 30.0%” |
| style=”width: 50.0%” |
|-
| style=”width: 20.0%” | ATTIRE:
| style=”width: 30.0%” | Black-tie optional
|
|-

We will hold both a live and silent auction. Current auction lots include:

  • Lunch with Aart de Geus for up to 3 people
  • Stay at Kathryn Kranen’s Pacific Grove condo time share — 2 nights plus Monterey Bay Aquarium passes (condo sleeps 2 adults plus 2 kids)
  • Jim Hogan’s top 12 Cabernets
  • Private AT&T Park tour Dinner & Cocktails with Kathryn Kranen for up to 4 people
  • Dinner for 2 at upscale Scratch Restaurant in Mountain View
  • Private golf lesson with PGA golf pro Bill Mykytka
  • Two tickets for the Center for the Performing Arts in Mountain View, CA
  • Lunch with Penny Herscher for up to 3 people
  • Two-night “get away in place” stay at Cypress Hotel in Cupertino, CA
  • Bottle of 2005 Saint-Emilion Chateau La Dominique courtesy of Jacques Benkoski
  • EDA wine from Spence Vineyards. Etched magnum bottle of 2008 Howell Mountain Cabernet plus gourmet lunch in the vineyard and tour for up to 8 people. Lunch prepared by Vintner Jacalyn Spence, whose passion for food matches her passion for wine. Finish the day with a private tasting from the Spence’s private library.
  • Grand Vin de Chataeau Latour 1998 courtesy of Raul Camposano
  • Two ViP pit crew passes for the Flying Lizard Motorsports American LeMans team race at Laguna Seca on May 4, 2014 hosted by eSilicon and Jack Harding. Get into a fire suit and headset and join Jack Harding in the pits with the Flying Lizard crew during the race at Laguna Seca.
  • 3-4 night stay at a ski cabin in Breckenridge, CO, courtesy of Pat Pistilli
  • EDA Basket: Engineers Drinking Appellations, courtesy of Betsy and Mike Noonen
  • Brandon Belt signed baseball
  • Four-hour private tour of San Francisco for up to 4 people
  • EDA wine from Kymark Cellars. Mixed case of Petit Sirah, Cabernet and Cabernet blend from Mark Williams and Kyla Dreier
  • 80-minute couple’s Swedish massage at Fairmont Hotel Spa in San Jose
  • Chili’s Bar & Grill Gift Basket
  • Scott’s Seafood dinner coupon
  • A private wine tasting for 8 at 3 Steves Winery in Livermore
  • An original oil painting from former Synopsys employee Rick Jamison
  • Surfing lesson with world-famous surfer Darryl “Flea” Virostko, three-time Mavericks competition winner
  • ARM-powered gift basket
  • Chance of a lifetime to pitch your idea to Foundation Capital (Rich Redelfs, General Partner ) including lunch with Rich at the office
  • Skippered charter cruise on San Francisco Bay with Bob Gardner for up to 6
  • Gourmet gift basket courtesy of the Santa Clara Convention Center
  • Round of golf at Shoreline Golf Course
  • Custom Jewelry from L3 Design courtesy of Linda Lavin
  • Dinner with Simon Segars for up to 3 people
  • 90-minute tour of Brassfield vineyards, wine caves, and a private wine and cheese pairing for 4 people at Brassfield Winery in Clear Lake, CA
  • 60-minute yoga class
  • San Francisco Bay Sailing and Hiking Adventure from Dave Guinther (Chrysalis employee #1)
  • Lunch with Jim Hogan for up to 3 people in Santa Cruz
  • Two tickets to Golden State Warriors vs. LA Lakers at Oracle Arena on Dec. 21 courtesy of Prakash Narain — Lower level tickets near the action
  • Little known California wine gems & something special to put them in courtesy of Mike Gianfagna and Phyllis Orlando

I tried to donate a ride up Highway 1 in a Porsche Carrera Cabriolet but it didn’t make the list. Too scary, not even my wife would go with me. I hope to see you there!

lang: en_US

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Cadence Grows VIP Business – What’s New?

Cadence Grows VIP Business – What’s New?
by Pawan Fangaria on 10-04-2013 at 10:00 am
Categories: Cadence, EDA

VIPs (Verification IPs) are really important in this complex world of SoCs which involve various IPs, interfaces and continuously evolving protocols and standards, thus making the task of verifying an overall system extremely challenging. And the verification must be done in minimum possible run-time and memory consumption. Add to it, the tremendous pressure of time-to-market. In such a situation, this concept of VIP is a boon to the semiconductor design industry. A VIP is like a plug-and-play verification component (configurable under different environments) which enables any design to be tested, quickly and easily, at block, sub-system or SoC level.

Too many standards and protocols for buses, interfaces and MIPI (Mobile Industry Processor Interface), continuously evolving into newer versions with improved capabilities (such as speed, bandwidth, encoding, decoding etc.) has frequently demanded newer VIPs. Small capital investment and large demand in this business led to the emergence of numerous players. VIP business turned into a commodity business, albeit important and essential. Naturally, there was a consolidation move some time ago and closest business adjacencies, EDA giants acquired a few of the VIP companies; notably Cadenceacquired Denali and Synopsysacquired nSys and ExpertIO.

Why is it important? It complements the SoC platform solution to large extent by easing the burgeoning verification task. Again, by conforming to certain standards, it becomes generally available to semiconductor design and consumer electronics industry. Naturally the strategy which plays a big role in this is how fast one can bring up a new VIP conforming to a new set of standards and grab the market share.

This particular business caught my attention when, about a month ago, I heard Cadence announcing semiconductor industry’s first VIP for HDMI 2.0 (High Definition Multimedia Interface), which conforms to major verification languages, logic simulators and verification methodologies including UVM (Universal Verification Methodology). I am sure, Cadence will gain significant market share in this with companies like STMicroelectronicsand Sony already using it.

The HDMI 2.0 VIP announcement prompted me to look further into what exactly is being offered. And I came across a whitepaper, jointly written by ST and Cadence, which provides great level of detail about the much improved HDMI 2.0 (earlier, or rather current version is HDMI 1.4a/b) and the challenges involved in making of that VIP. I am not going into all that detail here, but it’s worth mentioning some of the design and verification challenges which appeared due to HDMI 2.0 as compared to HDMI 1.4a/b, and how the VIP caters to those.


[Block diagram – HDMI transmitter (Source) and receiver (Sink) device]

Among design challenges are – i) Re-designing the video encoder to be synthesized at 600MHz (as compared to 300MHz with 1.4b), ii) Re-designing of several other blocks to accommodate new timing constraints and misalignment of control logic between video data and video sink, iii) Addition of a new state “scrambling_enb” in the state machine to support scrambling for EMI (Electromagnetic Interference) / RFI (Radio Frequency Interference) reduction at TMDS (Transition Minimized Differential Signalling) bit rate of lesser than or greater than 3.4Gb/s, iv) Scrambling using LFSR (Linear Feedback Shift Register) and validating the data decoded by the sink VIP, with increased complexity at 600MHz. There are many other challenges mentioned in the whitepaper.

Verification challenges have increased exponentially in HDMI 2.0 due to huge video frames, multiple streams, complex data structures with multiple layers, and scrambling, encoding and encryption of the digital data at high frequency. All supported video formats with all the possible configuration settings, such as frame rate, pixel encoding, color depth etc. and all audio formats with appropriate configurations (channel allocation, audio frequency etc.) must be verified.


[VIP configured as HDMI source for sink DUT]

A VIP to be able to thoroughly verify a DUT (Design Under Test) under such complex protocols must be robust and flexible enough to accommodate varied configurations. HDMI VIP includes static and dynamic configuration parameters, customizable frame formats, on-the-fly data-integrity and signal-integrity checks, frame boundary detection, user controllable options etc. that provide 100% coverage.

A layered and scalable architecture of HDMI VIP provides a smooth and timely migration from IP-level verification environment to SoC-level verification environment. Click on the whitepaper to know more details. It’s an interesting read!!

lang: en_US

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High-Sigma Standard Cell Optimization!

High-Sigma Standard Cell Optimization!
by Daniel Nenni on 10-03-2013 at 11:00 am
Categories: EDA, Solido

Standard cell optimization is an important problem, because the speed, power, and area of cells has a direct impact speed, power, and area of the whole chip. Typically, standard cell optimization been done with simple in-house local-optimizer scripts. However, these optimizers have had several flaws: they don’t properly capture the variation, they get stuck in local optima, and they are serial and wasteful of simulations. The result is circuits with suboptimal power, speed, and area; from a design process that took longer than necessary.

At TSMC’s recent OIP Symposium (October 1, 2013), Solido Design Automation exhibited and had a paper about a new approach to standard cell optimization, which addresses these issues and is being used in production with leading TSMC customers. There are two keys to this: a world-class global optimizer, and an appropriate design flow. We now discuss each further.


The figure below left elaborates on the issues of previous local script-based optimizers. Below right describes how Solido Cell Optimizer overcomes these issues.

To be efficient at global optimization, Solido Cell Optimizer uses nonlinear regression models to data-mine all previous simulations, and efficiently choose new simulations. Unlike many script-based approaches, the Cell Optimizer can optimize across any number of testbenches, any number of corners, and fully exploits parallel processing.

The second key is a flow that handles variation quickly and accurately. It turns out that we can actually preserve the well-known corner-based design flow. Only now, corners are better: they capture the bounds of the circuit performances rather than device performances. Given that standard cells need failure rates of 1/1M or less, then to properly capture the variation without needing millions of simulations, we use Solido High-Sigma Monte Carlo (HSMC). The steps in the flow are: (i) extract high-σ corners using Solido HSMC, (ii) optimize on those corners using Solido Cell Optimizer, and (iii) verify to high-σ using Solido HSMC. This flow accurately captures variations, while still enabling rapid iterations of sizing variables. The figure below illustrates.


The figure below shows the flow in practice, on a flip flop. The right side shows the first step, where Solido HSMC was run, returning the high-sigma tail distribution (in red), and along with it, a 5-sigma corner for setup time. Then, Solido Cell Optimizer was run, to minimize setup time. Finally, Solido HSMC was re-run, to characterize and verify the final design.


Mutual Solido and TSMC customers have been using this flow, which combines Solido Cell Optimizer and Solido HSMC, in various cases, including:

  • Efficiently optimizing a bitcell design for optimal read margin and write margin simultaneously, using a different testbench for each measurement. This is for both nominal and high-sigma variation conditions. The bitcell design is in both 20nm and 16nm.
  • Tuning, porting, retargeting, and migrating large standard cell libraries, to support a large designer base. This task is extremely time consuming and simulation intensive to do manually. Furthermore, these cells need to be optimized to work well under high-sigma conditions. Technologies used include 16nm, 20nm, and 28nm.
  • In a large library of standard cells, while all of the cells perform well under nominal conditions, identifying which cells fail under high-sigma conditions and automatically fixing them via resizing.

In summary, mutual Solido and TSMC customers have been exploiting the benefits of a new flow for high-sigma standard cell optimization. Through the combination of Solido Cell Optimizer and Solido High-Sigma Monte Carlo, the flow properly captures variation, provides globally optimal results, doing so in an extremely efficient fashion.

For more information, visit www.solidodesign.com.

lang: en_US

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A Mixed-Signal IC Summit in San Jose

A Mixed-Signal IC Summit in San Jose
by Daniel Payne on 10-03-2013 at 9:26 am
Categories: Cadence, EDA

Analog and mixed-signal ICs are tougher to design and verify compared to digital, so if you want to learn more about best practices from actual AMS engineers then consider attending a summitthat is sponsored by Cadence Design Systems next Thursday, October 10th in San Jose from 8:00AM until 6:30PM.

They’ve lined up an interesting mix of presenters from: Academia, Industry, Foundry (TSMC), Cadence R&D, Freescale, Cirrus Logic, STMicroelectronics, Microsemi, Rambus. You’ll be served breakfast, lunch and enjoy a social time after the presentations.

Agenda

  • 08:30-09:30am Registration and Breakfast
  • 09:30-09:45am Welcome and Opening Remarks by Dr. Chi-Ping Hsu, Sr. VP R&D and Chief Strategy Officer, Cadence
  • 09:45-10:30am Academic Keynote: Challenges in Emerging Mixed-Signal Systems and Applications by Prof. Terri S. Fiez, Professor & Head EECS Dept, Oregon State University
  • 10:30-11:15am Industry Keynote by Geoff Lees, Senior Vice President and General Manager Microcontrollers, Freescale
  • 11:15-11:30am Break
  • 11:30-12:00pm Mixed-Signal Trends-Foundry View by Douglas Pattullo, Technical Director, TSMC North America
  • 12:00-12:30pm Mixed-Signal Solutions Update by Koorosh Nazifi, Group Director, Initiatives R&D, Cadence
  • 12:30-01:30pm Lunch with R&D
  • 01:30-02:00pm Mixed-Signal Verification Methodology using Real Number Models by Tim Pylant(Cadence) & Bhupi Manola(Cirrus Logic)
  • 02:00-02:30pm Methodology for Verifying SerDes Bit-Error-Rate Using Real Number Modeling by Michael Hufford, Staff Design Engineer, Cadence
  • 02:30-03:00pm Cadence-Mixed-signal Implementation Update by Steven Lewis, Product Marketing Director, Analog/Custom Marketing, Cadence
  • 03:00-03:30pm Virtuoso Mixed-signal “Smart Power” Implementation Flow (case study) by Livio Fratantonio, STMicroelectronics
  • 03:30-03:45pm Break
  • 03:45-04:15pm Micro-Semi: OA Based Netlist on Top Flow(Case Study) by John M. Williams, Director of CAD Engineering, Microsemi IC Group, Microsemi
  • 04:15-04:45pm Interoperable Database for Mixed-Signal Designs Netlisting by Mark Snowden, CAD Manager, Rambus
  • 04:45-05:15pm Mixed-Signal IP Offerings by Cadence IP Team
  • 05:15-05:20pm Concluding Remarks & Raffle Drawing
  • 05:20-06:30pm Social Hour and Networking

Summary
This summit looks useful for practicing engineers because the presenters are mostly AMS engineers (only one marketing guy) or developers talking about approaches that they have used on actual chips. There is a registration process that you need to fill out for the Summit.

lang: en_US

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Floorplanning Merged With Synthesis

Floorplanning Merged With Synthesis
by Paul McLellan on 10-02-2013 at 2:45 pm
Categories: EDA

One area of iteration that is becoming more problematic is between floorplanning and synthesis. So much of timing is driven by placement that fixing timing and even power often involves not just re-synthesis and re-placement but alterations to the floorplan. The Achilles heel of existing methods is that floorplanning tools are forced to use a “fixed netlist” as a starting point, which forces them to go through a continuous iteration loop with synthesis teams to optimize their floorplan, make incrementatl physical changes then optimize with synthesis.


Oasys RealTime can plug into and complement existing flows – front end team generates an initial floorplan which they then feed forward as initial guidance to the physical design teams. The front end design team can create a floorplan directly from the RTL that is aware of the design’s dataflow and also meets all the constraints for timing, power, area and routing congestion. It only takes 2-3 days to generate and is about 90% the same as the final production floorplan and thus forms a good starting point for physical design. Compared to current methods RealTime saves about a month out of the schedule.

There are actually two different ways to use RealTime to feed a design forward into physical design, depending on whether the physical design team intends to re-synthesize the design completely using a different synthesis tool. There are many reasons for doing this, ranging from having a huge pool of licenses, training, corporate standards and so on.

If a different synthesis tool is being used, then the floorplan is fed forward from the front end team as a DEF file. The design is then synthesized with the traditional synthesis tool and then physical design and signoff occurs as normal.

The alternative is to use RealTime as “the” synthesis tool. In this case the front end team produce more than a floorplan, they produce a detailed placement DEF and a synthesized netlist. This allows the user to get the best possible starting point for the physical design team. The placement is not completely perfect since certain aspects of physical design such as detailed power routing are not taken into account. An additional benefit of this approach is that typically, in addition to synthesis being fast due to RealTime’s RTL-based approach, physical design is often faster since the design is already very close the final result (the routing and signoff still has to be done of course).


Floorplan Compiler can generate an initial floorplan automatically from the RTL, including taking into account blocks such as memories. The advanced editing tools make it easy to take that initially created floorplan, make changes and then iterate getting better versions multiple times per day. One of the most time consuming tasks, and one of the most critical, in SoC design is getting a good quality floorplan.RealTime reduces the time required for this task from a typical 4-6 weeks down to a few days, saving around a month.

More details on Floorplan Compiler are available here.