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Palladium’s Little Brother Protium

Palladium’s Little Brother Protium
by Paul McLellan on 07-17-2014 at 8:00 am
Categories: Cadence, EDA

Today, Cadence announced Protium, a new FPGA prototyping platform for software development. During development of an SoC, the most appropriate methodology changes. In the early days, developing RTL, the primary tool is simulation. Then, as the blocks get bigger or as the whole chip starts to come together, typically simulation runs out of steam. Time to switch to emulation using Palladium. Then, once the RTL is pretty much stable, it becomes attractive to use FPGA prototyping, which is where Protium comes in (I guess the name is a hybrid of prototype and palladium). Protium can then be used for software development and debugging. Protium is not really intended for hardware debugging. If a hardware issue is detected then it is best to fall back to either emulation or simulation where the debug tools are much more powerful.


One problem with FPGA prototyping is that bring up can be a challenge, typically measured in months. This severely detracts from the usefulness of the FPGA prototype since software development can’t really get going during this period. With Protium, Cadence have put a lot of effort into making this process much smoother, bringing what used to be a 3 month process down to 2 weeks. They actually use the Palladium front-end integrated compile engine (ICE). Halfway through the compilation there are then two possible routes to take the design: into Palladium to verify the FPGA functionality, or into Xilinx’s compilation flow to actually create the FPGA bitstreams to program Protium.


Protium comes in various configurations. It is based on Xilinx Virtex-7 2000T FPGAs. There are two baseboard options, either 2 or 4 FPGAs. One or two boards can be used per chassis giving the following configurations:

  • 2 FPGAs: 25M gates (single board)
  • 4 FPGAs: 50M gates (single board)
  • 6 FPGAs: 75M gates (dual board)
  • 8 FPGAs: 100M gates (dual board)

There are two 150pin daughtercard connectors per FPGA, up to 8 per board, with 1.8V signalling at speeds of up to 1.25Gbps. Bulk memory daughtercards can be added for DDRx, SRAM, flash, SD card etc, or custom memory cards. There is also SpeedBridge product interface capability, that handles the speed mismatch to buses such as PCI.

This fully automatic flow gives a prototype that runs at 3-10MHz. With manual guidance and adding memory cards (instead of implementing the memory in the FPGAs themselves) the performance is in the 10-30MHz range. And by doing a lot more manual work, guiding the FPGA partitioning and synthesis, mapping the clock directly and so on, the performance can be over 100MHz, although this is a slower and more manpower intensive process, roughly equivalent to how FPGA prototyping had to be done in the past.

So Protium is 4X faster bringup than the first generation FPGA prototype system, has 4 times the capacity and 3 times the memory. Compile times using Palladium/Xilinx flow is 5X faster.


Cadence announced a second addition to the system development suite, to address low power verification of power-shut-off domains, voltage scaling domains and so on. This allows verification to be done using either simulation or emulation using Palladium. There is full support for power policy being expressed either in Si2 CPF or IEEE 1801 (UPF). Simulation can be used with a full 0/1/X/Z signal model to check for corruption, and check isolation and retention. Palladium can be used for system validation and analysis, measuring average and peak power in the context of running a software load.


More articles by Paul McLellan…

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Intel Second Quarter Results

Intel Second Quarter Results
by Paul McLellan on 07-16-2014 at 4:03 pm
Categories: Foundries, Intel Foundry

Intel announced their quarterly results earlier this week. Their mainline microprocessor business is doing well, especially the highest performance segments for servers, datacenters and cloud computing. Broken down by segment the numbers come out like this:

  • PC Client Group revenue of $8.7 billion, up 9 percent sequentially and up 6 percent year-over-year.
  • Data Center Group revenue of $3.5 billion, up 14 percent sequentially and up 19 percent year-over-year.
  • Internet of Things Group revenue of $539 million, up 12 percent sequentially and up 24 percent year-over-year.
  • Mobile and Communications Group revenue of $51 million, down 67 percent sequentially and down 83 percent year-over-year. Ouch, that has to hurt.
  • Software and services operating segments revenue of $548 million, down 1 percent sequentially and up 3 percent year-over-year.

The PC business is being driven by a couple of things, such as the end of Microsoft’s support for Windows-XP driving a reinvestment cycle. Intel reckon that the installed base of PCs that are over 4 years old is 600 million and they are seeing clear signs of a refresh cycle in small and medium sized businesses.

In tablets, they shipped 10M devices last quarter, which puts them on track for the 40M unit goal for the year. But this is really just seeding the market since they are not making any money on them, and recognizing contra revenues against them (although they expect to get costs down enough to be breakeven by the end of the year). But they have more in the pipe:

“We qualified the first Broadwell-based Core M processors and at Computex we highlighted the form factor innovation that 14-nanometer Core M product family will enable. Systems like Llama Mountain reference design, a fanless detachable two-in-one that is razor thin at 7.2 millimeters and weighs just 24 ounces.“


Mobile is still doing horribly, down to $51M (which is down over 80% from the same quarter last year). Since Intel is investing of the order of $1B per quarter in this segment that means they have lost over $2B so far this year. On the call they said that they are on-track for having their SoFIA integrated baseband and apps processor in Q4 of this year. This is Atom-based but built by TSMC (I assume that their existing LTE modem will be incorporated too). They talked about a new LTE product too, which I assume will also be built by TSMC:“We are working towards qualification of our 7260, our Category 6 LTE product with carrier aggregation early this quarter.”

In reply to a question, Brian said that they intend to bring these products inside late in 2015 or early 2016 since they see it as important to be able to leverage their process technology in every market. Talking of process technology, they confirmed that 10nm production would start in 2015 with volume in 2016.

Margins are expected to come down a little in Q4 since they will be ramping multiple 14nm fabs simultaneously. And another datapoint that is important for the stock price is that they announced they would buy back $4B in stock in Q3 with more in Q4 (they bought back $2B in Q2). The total buyback will eventually be $20B.


More articles by Paul McLellan…

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Catching IC Manufacturing Defects With Slack-Based Transition Delay Testing

Catching IC Manufacturing Defects With Slack-Based Transition Delay Testing
by Daniel Payne on 07-16-2014 at 3:00 pm
Categories: EDA, Synopsys

Test engineers are often the unsung heroes in the semiconductor world, because they have the tough job of deciding if each IC is good or bad, while taking the least amount of time on a tester and ensuring that the tests are actually finding and uncovering all manufacturing and process variation defects. Simple stuck-at fault models are no longer sufficient to catch all of the actual defects, so to achieve the highest quality and lowest Defective Parts Per Million (DPPM) new Transition Delay (TD) patterns are being used. Extending TD testing with Slack-Based Transition Delay (SBTD) testing is a new approach for even higher defect coverage. A recent webinarpresented by Synopsys and Avago focused on this test topic.

Continue reading “Catching IC Manufacturing Defects With Slack-Based Transition Delay Testing”

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Andes Plays an ACE

Andes Plays an ACE
by Paul McLellan on 07-16-2014 at 9:01 am
Categories: Andes Technology, IP

There is a perception that ARM is the only microprocessor game in town due to their strong position in many markets, especially mobile. In areas where the instruction set shows through, then this is probably true. There is no rush to build smartphones where the application processor is something else. But even in a phone there are perhaps ten more processors where the instruction set doesn’t show through since the user has no access to the code (bluetooth, audio decode, and so on). For these processors the decision matrix is different. Power, cost and configurability are the important dimensions. As the dominant IP supplier of microprocessors, ARM is not going to have a strategy to be the lowest price and commodify their market. It turns out that they are not the lowest power supplier either. And they are less interested in configurability than others since it doesn’t play to their strength which is that ARM is a standard.

Andes, which I like to describe as the biggest microprocessor company that you’ve never heard of (although you should have by now, I’ve been writing about them since the time I first ran across them at the Linley Mobile Conference about 18 months ago) is a Taiwanese company that historically has done most of their business in Asia. But now they are moving into the US and already have several licensees.

Up until now, AndesCores have had two of the three attributes that users require: they are not as pricey as ARM and they are lower power than equivalent cores. They also have a range of cores from simple low performance, very low power and small up to multi-stage pipeline, high performance and, while not as low power obviously as the slower cores, still very low when measured by MIPS/W.

The reason that customization of the instruction set is so important is that increasingly functionality that used to be implemented in hardware (so Verilog or SystemVerilog) is moving into software for time to market and flexibility reasons. But running software implementations of many DSP and video-processing functions on a general purpose microprocessor is too expensive in terms of power (and sometimes the performance is not enough). For example, MP3 decode on a general purpose microprocessor consumes much more power than doing it on a core with the right additional instructions. And trying to implement an LTE modem or a lot of video processing algorithms on a general purpose microprocessor will fall short on the performance available when running the processor flat out. It seems to now be received wisdom that most of these “offload” functions are best implemented in a processor core optimized for either the specific algorithm or at least for the domain (e.g. video). This gives you 90% of the flexibility of pure software and 90% of the hardware performance/power of a pure hardware implementation.


Now Andes have the EN801 which is the first extensible AndesCore. This is accomplished partially in the way the core itself is configured using ACE, the Andes Custom Extension framework and partially through the software environment used to do the configuration called COPILOT, which, pushing acronyms to some sort of asymptotic limit, stands for Custom OPtimization Instruction develOPment tools.


The EN801 is based on the highly efficient AndesCore N801, which has a 3-stage pipeline. The basic core remains important since it is used to implement the 80% of the code that is rarely executed with excellent power characteristics and reasonable performance. For the other code, the inner loops and so on, additional instructions can be added to implement them very efficiently. Added instructions can be single cycle or multi-cycle, interruptible or non-interruptible, up the 3 reads and 2 writes from the registers. When different instructions have some overlap in functionality, logic sharing is possible.


One example is building a finite impulse response (FIR) filter. Using pure C code and no instruction extensions takes 175 cycles. Adding a FIR instruction reduces this down to 10 cycles. The pure C code also consumes 28 times as much power. Of course there is a cost in terms of added hardware, nearly 7K gates. But you can trade off area, power and performance to hit what you consider the sweet spot, that is one of the attractions of configurability.

Andes website is here.


More articles by Paul McLellan…

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Thread is why Nest has extra 802.15.4 goodies

Thread is why Nest has extra 802.15.4 goodies
by Don Dingee on 07-15-2014 at 4:00 pm
Categories: Arm, IP

From last week: “Chipmakers can’t afford to wait on the sidelines, hoping their standard fare gets picked up and fits in with one of these [#IoT]teams.” This week, it’s ARM, Freescale, and Silicon Labs joining with Google and others on Thread. Yet another consortium? A lot more to this story. Continue reading “Thread is why Nest has extra 802.15.4 goodies”

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Keywords: FD-SOI, Cost, FinFET

Keywords: FD-SOI, Cost, FinFET
by Eric Esteve on 07-15-2014 at 4:21 am
Categories: FD-SOI, Foundries, STMicroelectronics

How to synthesize a pretty good article Is SOI Really Less Expensive, and even more important the impressive amount of comments (56) generated? Let’s start with the initial article. Pretty good, but slightly biased, when you carefully dissect it, like I did in one of the comments (you can find it in-extenso at the end of this post). In short, if FD-SOI goes into large production level (remember that Samsung has just licensed the technology), this will generate a positive impact on raw SOI wafers, accounting for 9 to 10% of the fully loaded wafers, and not 15%, in the above mentioned article. The second point (not high production dependent) is even more important: the article compares FD-SOI offering 3 Vt with Bulk, offering also 3 Vt.

If you don’t really know the technology, you may think that that’s a fair comparison. Unfortunately, it’s not! FD-SOI library requires only using two Vt when using an equivalent library (optimizing the leakage current) on Bulk will require at least four Vt. FD-SOI processing will then require less mask level, impacting again the fully loaded wafer cost. That is, you pass from par (100% normalized price for each technology) to 100% for Bulk to be compared with 90% for FD-SOI 28nm. The industry consensus is that 28nm will stay for long, and is the preferred node for cost sensitive products (like low-end wireless application processor), thus a 10% cost difference is really important. Now, the question is: should a marketing campaign be based on cost only? As a former ASIC PMM, I strongly think that using cost as the unique argument is at first not enough and finally dangerous. Highlighting the differentiators is much efficient!

We have described in this post how to benefit from the Forward Body Bias (FBB) effect in FD-SOI to increase the performance, or decrease the power consumption at the same performance level (just take a look at the article to get the complete picture). The biasing capability is a real differentiator, and the reason is that you can’t use it with FinFET!

If you don’t trust me, just look at this article from Ed Sperling in SemiconductorEngineering: “IP and FinFet at Advanced Nodes” mentioning Bernard Murphy, CTO of Atrenta: “The standard MCU guys, when they want to dial down power, don’t want to mess with the architecture because that has ripple impacts on a lot of other areas. So they use biasing, which is a great way to reduce leakage. But that doesn’t work with finFETs, and if you still have a power problem with your MCU you have to change the architecture.”
This biasing differentiation lead to the probably most important feature coming with FD-SOI: lower power consumption. It can be ultra low-power if you design a SoC for mobile application, and it can be simply more power efficient (at the same performance level) if you design a high performance networking IC. Benefiting from lower power consumption will have a tremendous impact on chip packaging and cooling, and all along the chain on massive power consumption of a server farm.

So, why the SC industry did not jump into FD-SOI technology? We get the answer in this excellent comment from IanD:

At the point where it became clear that something had to replace planar bulk technology and the industry had to decide whether to go with bulk FinFET or FDSOI (or even SOI FinFET), several things happened to influence this. The first was Intel announcing FinFET (and how fantastic is was) at least a couple of years before anyone expected it to happen, which caused a bit of a panic reaction largely driven by customers screaming “We must have FinFET to stay competitive!”. Also at this point FDSOI — especially the UTBB substrate capability — was not really ready and seen as risky and expensive, and FinFET was seen as the safe option. There was also a concern about future scaling to 10nm and below on the assumption that EUV would be ready and that these would be mass-production low-cost processes, with FinFET seen as scaling better to 7nm and 5nm which would all follow on from 10nm at the usual rate. So the industry rushed towards FinFET, probably much faster than they would have liked to without Intel’s bombshell — which as has been said many times, was a good choice for them making x86 CPUs, but not so obviously for the rest of the industry.

Since then things have changed somewhat. Some of the disadvantages of FinFET have started to emerge when SoC designers have started to actually use it — remember there isn’t such a thing as a free lunch, and the good points of FinFET in some applications (high drive, high speed, high density) are also bad points in others (high power density, higher gate capacitance, worse hotspot and EM issues) since the two are inextricably linked. Process variability which was not a killer issue for Intel CPUs is an issue for most other applications, and unlike for FDSOI can’t be trimmed out with FinFETs. …
Nobody’s suggesting that TSMC are stupid, they made the right decision based on what their customers were claiming for and given the state of FinFET and FDSOI at the time. Whether this was right given what we know now can be debated for years — hindsight is a wonderful thing, isn’t it? — but at least it now seems that FDSOI will be available and supported by multiple suppliers and IP providers for those people who are working in application spaces where it is better than FinFET, so at least the choice is there. For sure FinFET will be dominant initially as the juggernaut rolls on, but if FDSOI delivers on its low-power promises it should attract an increasing share of the market for applications where this is the #1 priority.

Another comment (see below) is not very positive about people promoting FD-SOI, but I think it is very smart in pointing the reason why FDSOI was not successful in the past: uncertainty.

From: Kencweng
Stop beating around the bush. The major challenge in FDSOI is not the substrate cost, the design ecosystem or even the stupidness of curtain persons. According to the substrate providers, the cost of SOI will soon be reduced. Based on my personal experience, porting a physical IP to FDSOI is not that difficult as what people think. Designing a physical IP for FinFET is harder. The design ecosystems are not that much different. Granted, we are all smart engineers.

IMHO, it is the uncertainty or the unknown fact(s) associated with any “promising” or “innovative” technology that makes the adoption so difficult. Unfortunately, the groups of persons who have been promoting SOI either ignore this or have their own agenda. What do we expect us to do after observing the struggle of persons who have chosen SOI? The persons who stay with bulk seem to be more successful.

All I can say is good luck for all persons who are pushing for SOI. May they succeed this time!

Uncertainty is not a scientific, quantifiable feature, it’s human, but it’s real! This is why the latest information about FD-SOI “Samsung Endorse FDSOI” is also the most important for years. Put yourself into the decision maker shoes. You were previously being cautious about FD-SOI because of uncertainty. Don’t you think that the same person will change his mind after seeing the 2[SUP]nd[/SUP] larger and most performing SC player adopting this technology? Just leave a couple of quarters, the time to start consolidating an IP ecosystem and for Samsung to familiarize with the technology, and check for FD-SOI adoption, let say during 2015…

From Eric Esteve from IPNEST

The pricing comparison seems to be the result of a deep research, nevertheless we can make two comments about the Tables, applying for 28nm and 14 nm as well:

  • Starting Wafer Cost is over-evaluated for SOI wafers in full production
  • Mask Layers are under-estimated for Bulk in 28nm or FinFET in 14nm if you take into account the various Vt you need to implement (4 to 5 Vt) to offer the same latitude than FD-SOI (with 2 Vt only) in respect with the leakage current.


Wafer Cost
Since 2011, the agreement is $500 (in 28nm) for a SOI wafer, and $130 for a bulk wafer. The ratio is 3.8, when the Table (28nm) indicates 3% vs 15%, or a 5 ratio. Moreover, the bulk wafer pricing is at the lowest, as the 28nm Bulk is in full production. It is not un-reasonable to foresee a price decline for SOI wafer, when FD-SOI will be in full production at both STM and Samsung! Instead of 3% (bulk) and 15% (FDSOI), we may use 3% and 9-10% when in full production, or 12% as of today… Let say that the cost impact for FDSOI in full production should be (-5%)!

Multiple Vt in 28nm
Inserting the same number of Vt (3) in the table for Bulk and FD-SOI is not accurate: FD-SOI offer consists of only 2Vts and wide leakage control/optimization is reached through the use of multichannel libraries allowing to accommodate from 24nm to 40nm channel length in the std-cells pitch. For the same leakage control, with bulk technology you would have to use 4 Vts. The same applies on bitcells where to get the same range of the FD-SOI offer, bulk technologies have to differentiate several specific implants, adding masks. Why using multiple Vt approach? FD-SOI technology allows in the std-cells pitch to accommodate multi-channel libraries with the Lpoly ranging from Lmin=24nm to 40nm. This gives a great control over leakage when optimizing for power an implementation. The 2 Vts offered by FD-SOI provide a control over leakage of 1/200x (RVT L=40nm being 1/200 of the leakage of LVT Lmin=24nm, the leakiest device). To get the same leakage control range in a bulk technology (that allows a much reduced multichannel range), you need to use 4 Vts in a SoC.
FD-SOI library requires only using two Vt when using an equivalent library (optimizing the leakage current) on Bulk will require at least four Vt. The bottom line is that we count more masks on FDSOI than needed (to be removed) and less masks on Bulk (to be added), the difference being 4 to 5 masks levels, or another (-5%)!
That is, you pass from par (100% normalized price for each technology) to 100% for Bulk to be compared with 90% for FD-SOI 28nm. The industry consensus is that 28nm will stay for long, and is the preferred node for cost sensitive products (like low-end wireless application processor), thus a 10% cost difference is really important.
The same argumentation applies for 14 nm technologies. Even if the decision to select FinFET is not purely based on cost, but on better performance or leakage behavior, a 10% cost difference may have a certain impact, when making the decision. Moreover, If we consider on the edge devices processed in 14nm, the unit price is expected to be high. If you remember, we have mentioned the Forward Body Bias (FBB) capability available with FD-SOI. FBB allow either decreasing power, either increasing performance (frequency) of the same chip. But in a wafer fab, the same device is not processed the same way: it can be Slow, Typical of Fast, and you know it after test. When dealing with high variability, you may end up losing some yield because of it. FD-SOI has FBB as a plus for playing with process compensation, to eventually recover slow parts.

If your application requires chips in the high range or performance, that means that you have to trash a part of the production… except if you use FBB to compensate. Thus, you can keep the chip price in the acceptable range, as you can increase the number of good die (in respect with the performance) per wafer… This cost impact is difficult to quantify, as it will depend on the unit price, the level of performance, but we know from Intel marketing for processors that it can be high.
To summarize, even if a few percent cost difference may look negligible, the aggregation of these “small” differences lead to a 10% difference on the processed wafer cost. 28 nm technology node is expected to stay the mainstream for very long, due to the Moore’s law interruption, especially for the high volume, cost sensitive devices like low-cost application processor. As far as I remember from my ASIC PMM days, a 10% difference is all but negligible, thus I suggest using the right wafer price from the beginning. The devices implemented in 14 nm are probably not cost sensitive, but rather chase for high performance and/or ultra-low power. But is it a reason for pricing FD-SOI 10% higher than it should be?

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Cadence Announces Quantus Next Generation Extraction

Cadence Announces Quantus Next Generation Extraction
by Paul McLellan on 07-14-2014 at 7:00 pm
Categories: Cadence, EDA

Today Cadence announced their next generation extraction solution called Quantus QRC. Actually they are technically announcing it tomorrow, since it is being announced at CDNLive in Korea where it is already Tuesday morning.

As with the other recently announced tools that end in -us, Tempus (timing signoff) and Voltus (power integrity), there is a lot of emphasis on being scalable to large numbers of CPUs giving up to 5X faster performance for single and multi-corner extraction runs. A lot of emphasis has been put on getting best-in-class accuracy especially for FinFET processes. It is backwards compatible with the prior version of QRC in that it uses the same technology files and the results correlate. There is also a random walk field solver that allows correlation to be checked (obviously only on a tiny part of a design, field-solvers are not full-chip tools).

Cadence have also worked closely with TSMC to ensure that the results correlate with silicon. Quantus QRC is fully certified at TSMC for 16nm FinFET and technology files are already available. It is also the first extraction solution certified to support 3D-IC (TSV-based designs).

Quantus is integrated into the Encounter platform (so there is the same engine under the hood during implementation as there is during signoff, which reduces spurious ECO loops).


It is also integrated into the Virtuoso platform. The integration is tight, in that there is no stream in and out between the two tools and so the extracted view flow allows for faster circuit performance debugging. Quantus executes right from the Virutuoso UI. It handles all the things you would expect such as RF, substrate noise analysis, inductance extraction, powerMOS extraction, RC and RLCK reduction and more.

It turns out I know a lot more than you might expect about circuit extraction since in about 1983 I wrote VLSI Technology’s circuit extractor. It didn’t do anything especially clever, it ran a scan-line across the whole (flat) chip that might have as many as…wait for it…10,000 gates, identified the transistors and the interconnectivity. I didn’t even have to worry about lateral capacitance or even resistance. But we only had 10 MIPS of CPU power and a couple of megabytes of memory, so it was non-trivial to get good performance. Even though computers are several hundred thousand times faster (and you can have hundreds of them) I can appreciate that keeping both the accuracy and the performance up given how many things interact with everything else (especially in FinFET) is an achievement.

Customer experience at AppliedMicro and Open-Silicon validates that it scales to 100s of CPUs and does deliver both accuracy and much faster run times.


For example, on a 20nm design of 39M gates, running on 32 CPUs it runs in 6 hours versus 15 for plain old QRC for a speedup of 2.5X. If the CPUs are increased to 64 then the speedup is 4.3X, so close to the 5X. Other designs (see the table) get even bigger speedups.

So, in summary:

  • 5 times faster, scalable to 100s of cores
  • best-in-class accuracy, silicon proven
  • in-design convergence to accelerate design closure
  • fully qualified in TSMC 16FF


More articles by Paul McLellan…

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EUV and DSA from Imec and #semiconwest

EUV and DSA from Imec and #semiconwest
by Paul McLellan on 07-14-2014 at 7:00 am
Categories: ESD Alliance, Semiconductor Services

All the details of how we will build semiconductors going forward depend on whether we have EUV in our arsenal or not. Imec is very close to this since they work closely with ASML (who are about an hour and half’s drive away just outside Eindhoven in the Netherlands). At the imec technology symposium we were given a quick summary of what the current issues are.


So where exactly is EUV? Well, the good news is that the basic technology can indeed print features in experiments. The trouble is that is a long way from being usable in manufacturing. Everyone knows that the biggest problem is the light source. It needs to be much more powerful. Zapping droplets of tin with a high powered laser doesn’t produce a lot of EUV (and that assumes it is aligned: at SPIE Advanced Lithography Conference this year TSMC reported that when they turned on their EUV equipment the laser was misaligned and promptly destroyed the machine).


But there are other problems too:

  • several resists show collapse (the resist washes off) with firm rinsing although something called a dry development rinse process seems to show promise
  • none of the resists produce adequate line width roughness (LWR) with acceptable sensitivity. You can have sensitivity or LWR control but not both. There is now a focus on different materials
  • masks (which, remember, are reflective masks using silicon-molybdenum in 1/4 wavelength layers to generate interference-based reflection) have defects. The defects come from imperfection in the base material before the Mo-Si layers are added. At that point they are too small to see (and very expensive to even look: think of searching for a golf-ball in the state of California) and only become visible once mirror has been made
  • front-side (on the mirror) particle contamination. Any contamination on the mask is in the focal plane and will therefore print (unlike refractive masks that have a pellicle to keep contamination out of the focal plane). Use of a pellicle for EUV is being considered but almost everything absorbs EUV so there are very limited choices for pellicle material, crystalline silicon being the best it seems.
  • backside particle contamination. the mask/mirror is electrostatically clamped to the reticle clamp and contamination on the back can distort the mask.


I also heard from a colleague who does process modeling that he’d been told by a true lithography expert that even if they get EUV to work, then it will probably not be economic. “We are getting so good at multi-patterning that even if EUV works it will still be more expensive.”


The other great white hope of lithography is directed self-assembly (DSA). For this conventional lithography is used to lay down guides at, say, 84nm (which can be single patterned). Then immiscible polymers fill the gaps and they magically line up (if you get the recipe just perfect) at, say 28nm pitch. A similar approach can be used for holes (contacts and vias) whereby a trench can be used to amplify the pitch to get vias on a much smaller spacing.

The basic idea seems to work although there are challenges:

  • placement accuracy, getting the DSA structures such as contacts to be in just the right position
  • DSA modeling: we don’t really have much yet
  • Design for DSA: not all structures can be created by DSA, basically at this point only grids of lines and spaces, and certain contact structures. So not all existing design approaches are DSA ready
  • defect understanding and mitigation: we just don’t have that much experience yet
  • this is “lithography in a bottle”. Purity of the chemicals is paramount. Impurities “print”.


More articles by Paul McLellan…

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Paving the Path for Robust Electronic System Design

Paving the Path for Robust Electronic System Design
by Pawan Fangaria on 07-13-2014 at 7:30 pm
Categories: Ansys, Inc., EDA

In today’s era of low power and high performance components, preferably on a single chip provides impetus to much larger electronic systems packaged into much smaller cases; smartphones are the immediate examples which encapsulate multiple functions other than the intended ones, viz. phone and data communication. As an example, a smartphone today performs complete function of video recording, viewing and displaying, what a handy-cam was doing a couple of years ago. So you can imagine, doing a live video conferencing or watching a complete movie on a smartphone is not a big deal. The same kind of phenomenon is happening in other applications such as medical, aerospace and automotive; electronics packed into compact spaces to be operated efficiently and conveniently with continuous supply of power and without any break over long duration of operation or any major heat up.

So, how does that happen? One may say it’s not a rocket science. But one must say it’s a science to save those rockets from electronic malfunctioning; most of the systems are controlled by MCUs in electronic boards. The robustness of electronic systems in terms of power consumption, noise, power and signal integrity, EM Interference, electro-thermal, electromigration and electrostatic discharge must be looked at with an integrated approach from bottom up, i.e. dies of chips, their packages and complete systems including PCBs. These days most of the electronics is driven by semiconductors and that means accounting for newer and newer physical effects at nano-meter process nodes like 28nm and 14nm, operating at much reduced voltages and narrow margins for various kinds of noises. That’s science giving rise to robust electronic engineering!

This reminds me about Apache’smerger with Ansys. While Ansys is leading the system design and engineering space solving mechanical, electro-magnetic, electro-mechanical, fluid dynamics and other multi-physics problems for large systems, Apache pioneers in semiconductor IC power optimization, noise and reliability solution at chip, package and system level. It’s a perfect merger integrating the two spaces which complement each other in most respects. In coming days, we will see further closer interaction between the electronic & electrical engineering and the semiconductor space.

The trigger to my mind about this thought was an articleposted by Yukari Ohno about a success story of Ansys’s chip-package-system (CPS) co-simulation solution used by LSI(Avago Technologies) in establishing a robust verification methodology and evaluating and selecting the best package design (that supplied the cleanest power with least noise) for their storage and networking chips. With a single simulation environment for complete chip and package, the chip-package routing was designed to identify and eliminate the noise due to DDR I/O switching activity on PLL supply. The author of the article is Cornelia Golovanov of LSI Corporation. I remember attending her webinar based on this design and development activity at LSI. The details of that study and development are put up here in this article, a must read to understand and appreciate the context of IC/SoC integration into package and system for robust electronic design. Consider the same smartphone example; all those operations can be possible only when there is sufficiently large, efficient, low-power, low-noise, and low-latency and durable storage mechanism in place.

Going back to the initial days of the CPS co-simulation solution introduced by Apache when I had watched an interesting youtube video, to my pleasant surprise, I found it is still there intact. It’s a 2 minutes video that tells about the CPS system which allows seamless communication between chip, package and system engineers to improve overall power and reliability. It’s a real progress happening since then.

RedHawk is an industry standard IC Power Integrity and sign-off solution and Sentinel is a high capacity, high performance chip, package and PCB co-design and sign-off solution. Both work hand-in-hand enabling IC aware system power analysis as well as package aware IC power analysis.

It’s a perfect environment that brings the chip, package and system worlds together. Going forward in future, are we going to see more such mergers between large system design companies and semiconductor design automation companies?

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