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Managing Stress in 3D

Managing Stress in 3D
by Beth Martin on 09-02-2014 at 1:32 pm
Categories: EDA, Siemens EDA

A new publication on mechanical stress in integrated circuits, co-edited by Valeriy Sukharev, Principal Engineer for Calibre R&D at Mentor Graphics, has just been released by AIP Publishing. “Stress-Induced Phenomena and Reliability in 3D Microelectronics” includes 14 key papers from four international workshops held in the U.S., Germany and Japan and is available at http://bit.ly/1w1svjo. The publication isn’t free, you’ll need to buy ($28) or rent ($4) it.

Development of 3D IC integration provides a potential solution to overcome the wiring limit imposing on interconnect density, performance and power consumption of integrated circuits. Management of mechanical stress is one of the key enablers for the successful implementation of 3D-integrated circuits using through silicon vias (TSVs). The potential stress-related impact of the 3D integration process on product reliability must be understood and shared, and designers need a solution for managing stress.

The co-editors selected papers to focus on Design-for-Reliability (DFR) and together they describe a stress management simulation flow that would enable designers to model stress implications on their designs quantitatively. The papers also discuss multi-scale modelling and simulation, multi-scale materials parameters and multi-scale analysis.

This is the second work in a series on stress management. The first publication, called “Stress Management for 3D ICS Using Through Silicon Vias” is available at http://amzn.to/1o60QE4.

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Design Collaboration across Multiple Sites

Design Collaboration across Multiple Sites
by Pawan Fangaria on 09-02-2014 at 12:00 pm
Categories: Cliosoft, EDA

Any SoC or IC design project, whether implemented at the same design site or multiple sites requires some data management tools to manage things such as a central data repository, revision management of files, etc., for effective co-ordination of work among different team members. Given the challenge of meeting the shrinking time-to-market windows, semiconductor companies are creating design centers wherever it is economically viable to operate or where a substantial good talent pool is available. As a semiconductor professional myself, I have often wondered about the ramifications on design schedules and design efficiency when collaborating across globally-dispersed design centers.

I realized the impact when I met one of my old acquaintances during my regular morning walk last Sunday. On enquiring about his rather irregular morning walks, he explained that it was due to the very long hours he was compelled to work. He further elaborated that his design team was facing challenges in collaborating with different design team members in different parts of the world. Curious, I politely enquired whether it was due to communication issues. Based on my friends explanation, I understood that some groups within their company rely on an open source revision management system that uses mirrored sites, despite which file transfers into the repository as well as the ‘rsync’ between their mirrored sites was also taking a long time. Since it was open source software that they were using for data management, the support was very limited. Moreover, they had been using customized scripts to set triggers, which needed to be upgraded, and the person maintaining the scripts at his local office had left. Other groups were not using any data management systems and were using a name-based file versioning system.

Also Read: Webinar: Improving Collaboration Within Dispersed Design Teams

My poor friend was stuck with late night sync-up meetings accommodating common time for all sites twice a week and of course managing to understand accents and diffierent ways English was spoken in different regions. Even though they had local sync-ups for the analog, digital and firmware parts of an SoC, they still needed to regularly consolidate all the work together to verify that they were working with the latest versions, for example, with the latest behavioral models from analog designers. And as a result of the chaos, his tapeout schedule had slipped, something which his managers were not too happy about.

Given the disorganized nature with which data management was set up, and the constant meetings my friend needed to have to ensure everyone was in sync, it was no wonder that my friend was stressed out. I remembered my old library design days when I had experienced headaches in regular mirroring of hierarchies for proper regression runs and when we had to babysit transfer of hundreds of design files, data or executable files to/from customer sites in the USA.


Figure: Globally-dispersed design centers collaborating on a design

In my opinion, owing to the complex nature of the design flows and designs being created, having a robust data management tool is no longer a luxury but an absolute necessity, especially when multiple design centers are concerned. It helps keep the engines of the design project well oiled and allows the designers to be more productive. Most importantly, it helps reduce the un-necessary stress in designers’ lives.

So, what are the requisites a data management must have in order to enable a design team, dispersed globally across different sites, to be more productive? Should we look at using open source software for data management or should we rely on commercial software? Here are some of the considerations I would think through:

· While I am a believer in open source software, and some of them are extremely good, the support is rather limited. The last thing I would like in a high-pressure project is to be stuck with some issues and being forced to browse through online forums to find a solution. Commercial data management solutions such as ClioSoft’s SOS and Perforce score in this area in terms of the level of support being provided. Moreover, commercial data management vendors are more amenable to work with you to customize the software to meet the unique requirements of your company.

· Commercial data management solutions provide a better feature set and roadmap compared to open source software.

· Although networks have large bandwidth these days, designers still suffer latency while accessing files from their central repostiories. Having a cache management system at each of the design sites, with regular automatic sync-ups with the data in the central repository, would help eliminate the latency problem. The local cache system should be configurable to store the commonly used revisions of the data, specific to the local design site. An additional advantage of this approach is that in the event of network down time, designers could continue to work without stopping at the local design centers.

· Network disks from vendors such as Netapp are not cheap. Hence from a cost perspective, it may not be prudent for the designers to copy the entire design database into their work area as the disk space usage can very easily balloon up. Ideally, the designers should be able to check out only the files that they want to modify into their local work area, while referring to the local site cache for the rest of the files.

· For the semiconductor insustry, espcially for analog, mixed-signal and backend designers, does it make sense to use a hardware configuration system such as ClioSoft’s SOS, which is built for big data sizes and performance, or a software configuration system such as Perforce? The requirements of the semiconductor industry to some extent differ from that of the software industry.

· No matter how much preacution a design team manager takes, a common problem he continues to face at the time of a design tapeout is the number of changes which are made at the last minute. As a result there are problems such as the central repository not being up to date, or unsolicited fixes being done at the last minute, which tends to de-stabilize the release. This can be resolved by maintaining specific release tags and ensuring that all files have them before the release and after fixes of all open defects against them. One of the requirements therefore would be the ability to set as many tags and labels as one wants during a design project cycle. This helps considerably while coordinating with team members at multiple locations.

· In order to restrict further changes in the files with release tags, there should be strict access control mechanisms that set the files to read-only mode the moment they are promoted with a release tag. In fact, access control must be used to allow or restrict access to particular groups whenever required.

· Design managers should be able to leverage off existing reports or create their own reports to determine the audit trail or to determine whether the same version of the IP is being used by all the team members.

· There must be an integrated defect tracking system that can be reviewed for the required fixes so that one can ascertain that the required fixes from other parties are done.

· There should also be a mechanism to take snapshots of the design very easily. There should be an easy mechanism for maintenance of tags and labels for hand-off of specific modules. This is very useful for designers when they are running different experiments in different directories to meet the performance criteria. It is etremely easy to lose track of which directory has the correct results. Having a mechanism to tag the directories would be extremely useful.

Do you have any other insights into what a data management tool for a semiconductor company must have? Comments are welcome!

Also Read

Webinar: Collaboration Within Dispersed Design Teams

Leveraging Design Team Energy!

Webinar: Making Design Reuse Work

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MIPS 64 bit CPU Architecture

MIPS 64 bit CPU Architecture
by Eric Esteve on 09-02-2014 at 4:47 am
Categories: Imagination Technologies, IP

Imagination Technologies has just launched the 5[SUP]th[/SUP] generation of MIPS CPU core, the 64-bits Warrior, or I6400 family, offering a total compatibility with the 32-bit previous architecture. MIPS Warrior I-class processor cores offers 64-bit processing in applications including embedded, mobile, digital consumer, advanced communications, networking and storage. I6400 is designed to be an extremely flexible, low-power 64-bit processor architecture capable of scaling across a wide range of applications, from microcontrollers to 64-bit servers. This 64-bit architecture provides hardware virtualization in all cores, hardware multi-threading, multi-domain security and multicore/multi-cluster support.

If we take a look inside the I6400 family of cores, customers will benefit from:

  • Highly efficient, scalable 64-bit performance:The I6400 will enable customers to set new price/performance points across markets. The I6400 can be implemented across a very wide range of performance, power and area operating points allowing reaching high frequencies in aggressive implementations. Design architect may implement multi cores and multi clusters configurations, including a mix of heterogeneous multi cluster, highly appreciable in mobile systems.
  • Hardware multi-threading:The I6400 features hardware multi-threading technology that supports up to four hardware threads per core.

Hardware multi-threading leads to higher utilization and CPU efficiency. Moreover the simultaneous multi-threading (SMT) technology in the I6400 enables execution of multiple instructions from multiple threads every clock cycle. Preliminary benchmarking shows that adding a second thread leads to performance increases of 40-50% with less than a 10% cluster area increase.

  • Hardware virtualization:To provide increase security and reliability and enable a unified security and virtualization strategy throughout the system, the I6400 joins the entire range of MIPS Warrior cores in incorporating hardware virtualization technology (this includes support for up to 15 secure/non-secure guests).

  • Unified security strategy:The I6400 core is designed to address the privacy and security needs of evolving and emerging connected applications. The core is optimized to support multiple independent security contexts and multiple independent execution domains. The solution scales to support secure content delivery, secure payments, identity protection and more across multiple applications and content sources.
  • Advanced power management:PowerGearing™ offer the ability to provide a dedicated clock and voltage level to each core in a heterogeneous cluster, while maintaining coherency across CPUs so that sleeping cores only need to wake when needed.
  • Efficient FPU: The proven hardware Floating Point Unit (FPU) in the I6400 supports both single and double precision capabilities relevant to general computing as well as improved control systems processing.
  • 128-bit SIMD:The I6400 features 128-bit SIMD support, delivering high performance and high throughput for a wide range of tasks that can exploit the efficiencies of SIMD execution in data-parallel applications. It is built on the MIPS SIMD architecture with instructions defined to be easily supported within high-level languages such as C or OpenCL for fast and simple development of new code, or to leverage of existing code.

Nothing is better than a picture (see above) and some numbers to illustrate the I6400 Power/Performance/Area (PPA) optimization. Targeting TSMC 28 HPM technology, the base core configuration, including 32 KB Instruction, 32 KB Data for the level 1 cache, two threads/core, SIMD/FPU and H/W virtualization with 15 guests, occupy one mm2 and deliver 5.6 CoreMark/Mhz or 3.0 DMIPS/Mhz. This performance level assuming worst case conditions (Vnom -10% and SS corner Silicon), nevertheless, higher frequencies can be achievable with more aggressive implementation techniques. The cluster configuration in this example is a quad core with 128 virtualized global interrupts and 1 MB of level 2 cache, for an estimated area of 7 mm2.

The successful semiconductor device will have to exhibit low power consumption while offering high performance, not only for mobile application but also in enterprise or consumer systems. Power efficiency (or performance in DMIPS or CoreMark per Watt) is the keyword. Advanced power management, or PowerGearing for MIPS I6400, is based on the following techniques:

  • Fine grained, block level, and core level clock gating
  • For each core (in multi-core cluster):

    • Sleep mode
    • Dynamic Voltage and Frequency Scaling (DFVS)
    • Can be implemented at different performance/power optimization point
  • Directory-based coherency architecture optimized for low power

    • Sleeping cores only wake when needed for coherency

Imagination expects the industry to move for architecture neutrality, thus the CPU choice should be based on technical superiority. The I6400 features set addresses wide range of next generation applications, allowing customers to optimize their resource investment when targeting various applications.
Imagination is already engaged with multiple lead I6400 licensing partners, with general availability scheduled for December 2014. Contact info@imgtec.com for more information.

From Eric Esteve from IPNEST

More Articles by Eric Esteve…..

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How to detect weak nodes in a power-off analog circuit?

How to detect weak nodes in a power-off analog circuit?
by Jean-Francois Debroux on 09-01-2014 at 4:00 pm
Categories: EDA

Most analog cells have a power off mode intended to reduce power consumption. In this mode, all the circuit branches between the supply lines are set in a high impedance mode by driving MOS gates to a blocking voltage. This is a somewhat similar situation to that in tri-state digital circuits.

When a branch is set in that high impedance mode, all the nodes in that branch are in high impedance too. The concern is that voltages on these nodes are undefined. More precisely, the actual voltages on these nodes are defined by leakage currents. Some leakage currents pull the voltages up while others pull them down. Depending on actual leakage currents values, the high impedance nodes or weak nodes can have any value, normally within one diode drop outside the supply voltage lines.

If such a weak node drives a CMOS inverter input, this one can draw a significant current if the weak node voltage is incidentally close to the inverter threshold.

Detecting such a situation is important as it may impair production yield or even worse it may happen in the field later on after some leakage current has drifted. But it is not a simple task since leakage currents are not always realistically modeled and anyway, they change from wafer to wafer and from device to device. Monte-Carlo analysis might help but leakage currents are not always statistically modeled properly.

A feature of most analog simulators such as SPICE derivatives, Eldo, Spectre, and probably others can be used to reveal weak nodes.

This common feature is that circuit branches conductance cannot be lower than a simulator parameter called “gmin”. This parameter often defaults to 1E-12 but can be changed arbitrarily by the user. The effect of this parameter is that the simulated circuit has a 1/gmin resistance in parallel to any branch. It is normally intended to simplify the first iterations. But these added resistances are not suppressed when the solution is reached. This is why gmin must be set appropriately with respect to the circuit operating currents in order to limit the impact on the result. We can use this feature to detect weak nodes.

Let’s analyze the following potentially faulty circuit:

To analyze it, let’s simulate the operating point and measure the supply current for various gmin values over a wide range. The following graph was obtained with Eldo for a 180 nm CMOS process:

The curve shows four different areas from left to right: A horizontal branch, a steep positive slope, a plateau and a positive slope. The rightmost positive slope at high gmin values results from the current flowing through the 1/gmin resistances in the branches. The leftmost horizontal branch results from leakage currents. But the plateau and the steep slope on the left result from the weak node effect. The reason is that when 1/gmin gets low enough, the two branches driving the weak node drive it towards VDD/2 causing simultaneous conduction in the inverter.

Now, let’s fix that circuit by driving the weak node to 0 (1 would work too) and run the same analysis again:


Now, the curve is normal, with a nearly constant about 1 decade per decade slope and an horizontal branch on the left. One can note that the default 1e-12 gmin value is high enough in that case to hide the actual leakage current.

The gmin sweeping method can detect weak nodes through their signature. If a plateau exists for intermediate gmin values and even more significantly if a steep slope exists, there are chances that weak nodes affect the circuit power off current. Then, tracing the currents trough the circuit hierarchy drives you to the issue location.

In order to check that you can use this method with your simulator, you can use the faulty circuit above and its fixed version. This method has proved to be useful in many cases, but it cannot be proved it will always detect weak nodes, especially for large circuits since the faulty current can be hidden by the sum of normal leakage currents. This is why I suggest using this method incrementally for every individual block upwards to the circuit top.

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September is Semiconductor Design Webinar Month!

September is Semiconductor Design Webinar Month!
by Daniel Nenni on 09-01-2014 at 9:00 am
Categories: EDA

The nice thing about webinars is that if you register for the live one and you can’t attend you will still get first notice when the replay goes up. The other nice thing is that you can read a blog review of a webinar or whitepaper on SemiWiki first to see if it is worth your time. If you do attend a webinar you can also post a review of it on SemiWiki if you think it is worth other people’s time, absolutely.

The SemiWiki calendar is one of the most traveled areas and webinars are the primary reason. Members can post webinar notices or other events on the calendar for all to see. Collaboration is the key to the success of the fabless semiconductor ecosystem and webinars are very collaborative.

Looking at September I don’t remember seeing so many webinars in one month but it certainly is an encouraging sign:

[LIST=1]

  • Reduce Your Design Risk By Enabling a Comprehensive Signoff Flow for Timing Constraints
  • VCS AMS for Advanced SoC Mixed-signal Verification
  • Physical Lint: Fast RTL Analysis that Identifies Logic Structures Known to Negatively Impact Design Convergence
  • Flow to improve collaboration within dispersed design teams
  • Pre-silicon Optimization of System Designs using the ARM CoreLink NIC-400 Interconnect
  • SoC Emulation Made Easy
  • Quick Introduction to SCE-MI
  • IP Signoff
  • Static Design Rule Checks in FPGA Design
  • TCAD to SPICE Simulation of SiC and Si Power Devices
  • Powerful and Easy to Use RTL Restructuring
  • TSMC Open Innovation Platform Ecosystem Forum

    Okay, the TSMC OIP is not a webinar but it is definitely a premier fabless semiconductor ecosystem event:

    The TSMC Open Innovation Platform® Ecosystem Forum brings together TSMC’s design ecosystem companies and our customers to share real case solutions to today’s design challenges. Success stories that illustrate best practice in TSMC’s design ecosystem will highlight the event.

    More than 90% of last year’s attendees last year said that the Forum helped them “better understand TSMC’s Open Innovation Platform” and that “they found it effective to hear directly from TSMC OIP member companies.”

    This year’s event will prove equally valuable as you hear directly from TSMC OIP companies about how to leverage their technology to your design challenges!

    This year, the forum is a day-long conference kicking-off with Trend-setting addresses and announcements from TSMC executives.

    The afternoon sessions include 30 selected technical papersfrom TSMC’s EDA, IP, Design Center Alliance and Value Chain Aggregator member companies, and an Ecosystem Pavilion featuring up to 80 member companies showcasing their products and services.

    Date:     Tuesday, September 30th, 2014 8:00 AM – 6:30 PM
    Venue: San Jose Convention Center, CA
    Learn About:

    • Emerging advanced node design challenges including 16 FinFET, 16FinFET+, 20nm, 28nm and TSMC-specific design solutions
    • Successful, real-life applications of design technologies and IP from ecosystem members and other TSMC customers
    • Ecosystem-specific TSMC reference flow implementations
    • New innovations for next generation product designs

    Hear directly from ecosystem companies about their TSMC-specific design solutions

    Network with your peers and 1,000 industry experts and end users.

    TSMC Open Innovation Platform Ecosystem Forum is an “invitation-only” event. Please register to attend. We look forward to seeing you at the 2014 Open Innovation Platform Ecosystem Forum.

    • Posted on

    Power and Thermal Analysis of Data Center and Server ICs

    Power and Thermal Analysis of Data Center and Server ICs
    by Daniel Payne on 08-31-2014 at 4:00 pm
    Categories: EDA

    The server market is a diverse, yet standardized market. The ICs and components designed and manufactured in final assemblies must meet form factor requirements for rack mount and blades. The form factor enclosures and the component placement dictate the thermal-mechanical properties and hence the thermal cooling limits which are driven by the energy and power consumption of the system.

    The workloads for server applications also vary significantly but all share elements of reliability, security and manageability. Many server operating systems combine virtualization technologies, and the applications can be multi-threaded and amenable to heterogeneous or symmetrical multi-processing.Related: Power Modeling and Simulation of System Memory Subsystem

    Simulation of the dynamic behavior of complex multi-core CPU designs, with high reliability storage and memory and high throughput IO is important for meeting thermal and power targets. You can over design and lose on costs, or target narrow use profiles and not meet performance or QoS requirements. Many performance and functional simulators do not address IO throughput and do not provide suitable trace information for accurate system-level power estimation. Traditional benchmark software workload analysis often does not account for error conditions, fault handling, user or network-defined conditions affecting packet throughput, processing as well as security and virtualization features.

    After determining the primary network operating system you will run on the server, estimated number of concurrent users and any storage requirements, the next critical decision to make is selecting the appropriate server form factor.

    Servers come in three general form factors: tower, rack and blade.

    So how could you go about designing IC’s for server requirements with such diversity of applications?

    Build a thermal-mechanical model
    Start with the targeted form factors in which your IC design will be used. In some IU rack enclosures there is no local fan cooling. Many rack enclosures have multiple variable speed fans and elaborate cooling mechanisms. The enclosure and component placement may dictate the TDP (thermodynamic power) limit of key components, notably the CPU’s, chipset and memory modules.

    • Consider the enclosure, PCB/Assembly and packaged device volumes in x, y and z coordinates. Then the material stack up, material properties and HTC’s.
    • Assign the power sources to the associated volumes consuming power and sensors or probes to monitor the temperature.
    • For an IC that could be used in several different enclosures, you could have models of each chassis or enclosure, and then a model of the PCB/assembly for that enclosure and of course, the package model of your IC’s.
    • When you model the HTC you can place sensors or probes at strategic locations such as the inlets, fan exhaust, CPU die/package, memory modules or memory devices.

    Related: ESL Tool Update from #51DAC

    Power models of the ICs
    Pre-existing IP used can be re-used where the dynamic, leakage, and state dependent power equations are applicable. The power model architect can map the server IC power states and system states to the IP block. The power architect must also account for server specific functions such as redundancy, ECC, failover and recovery mechanisms are quantified in terms of logic area. The corresponding active, idle power and standby or leakage power states and percentage of residency in each state. New IP power models are created using the power model parameterization as above recanted as: Logic/transistor count or area, power states, power equations per state, percentage of occupancy or residence in each state as a function of workload and operating condition.

    Power stimuli
    The stimulus can be performance or functional simulators from server database and web server applications in the form of CSV or VCD exported traces. Portions of the trace can also be used to inject error conditions, retries or other activity based on characterized data or statistical data. In this way the power architect can get activity factor and dynamic power of the processing, memory, and storage subsystem that are unique to server workloads. The IO and connectivity power can also be modeled using bandwidth and traffic generators with security and reliability features enabled, and disabled. Throughput can be adjusted based on error conditions, retries and packet payload delivery. The user can create complex power traces by adding steps or tasks and concatenating the power stimulus to drive the power model with concurrent and pipelined tasks.


    For multiple use case and multiple form factors and layouts consider using an ESL power-thermal profiling tool flow:

    Docea Powerprovides an ESL power and thermal solution using using the Ace Thermal Modeler which can generate compact thermal model that can be used to run coupled power-thermal simulations as well as a Thermal Profiling tool which can be used with power traces from characterized workloads.

    Summary
    Power and thermal modeling for server IC’s and SoCs is much like the approach used for SoCs in smartphone, tablet and mobile applications. However the key items are:

    • The IP blocks often have server specific hardware features such as ECC, security and packet processing acceleration. The corresponding power models need to comprehend server specific features and account for the power in server specific power states.
    • Server power states are based on high availability and QoS so throughput is key. Processor and memory active and idle states are highly optimized and many components can be in low latency yet standby power levels. New IP has been developed for latency tolerant IO and new bus technologies.
    • Server specific features like security and error handling need to be included in the power model. The security, reliability and manageability functions may add power, but in some instances the power penalty is highly dependent on system software and operating conditions.
    • The power stimulus should provide configurable conditions for error injection, congestion and encryption/decryption in the event traces to activate server specific features.
    • The thermal model needs to account for various chassis, PCB orientation, airflow and ambient environmental conditions.
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    TCAD to SPICE Simulation of Power Devices

    TCAD to SPICE Simulation of Power Devices
    by Daniel Payne on 08-31-2014 at 1:30 pm
    Categories: EDA

    The periodic table shows that Silicon (Si) is in a column along with other elements like Carbon (C) and Germanium (Ge). With so much emphasis on Silicon, you’d think that the other semiconductor materials have been neglected a bit.

    Silicon is a wonderful material and most of our consumer electronics and handheld devices use this material for transistors. However when we start to open the hood of an automobile, or ride an electric subway there’s another semiconductor SiC (Silicon Carbide) used for high-voltage applications. Companies like GeneSiC Semiconductor have designed a family of 1700V and 1200V SiC transistors for power electronics in:

     

    • Telecom and networking power supplies
    • Uninterruptable power supplies
    • Solar inverters
    • Industrial motor control systems
    • Downhole applications


    ​SiC Transistor

    To learn more about SiC, I plan to attend awebinarhosted by Dr. Eric Guichard from Silvacoon September 23rd from 10AM to 11AM (PDT). Eric has been with Silvaco since 1995, and prior to that he worked as a senior SOI engineer at LETI and Thomson Military and Space.Related: Teach Yourself Silvaco


    Dr. Eric Guichard, Silvaco

    Silvaco has a strong presence in the TCAD area and at this webinar will provide a discussion of the methods used to design, simulate and optimize the performance of power devices using TCAD and SPICE simulations. Wide-bandgap semiconductors such as SiC have begun to attract attention due to their projected improved performance over silicon. Simulating SiC devices is more challenging relative to silicon-based device. In this webinar Eric will review the requirements to accurately simulate SiC-based power devices. He will also present a completely automated TCAD to SPICE flow that helps reduce the cost and time taken to develop a Silicon-based IGBT power device.

    Related: Silvaco News. Silicon Valley, China and Korea

    Here’s what to expect at the webinar:

     

    • Key challenges of power device TCAD simulation
    • Key challenges of SiC TCAD simulation
    • TCAD simulation of SiC IGBT, Trench MOS and DMOS
      • 2D and 3D TCAD simulations (meshing, solver, physical models)
      • When to use 3D over 2D
    • Full TCAD to SPICE IGBT flow example
      • Process and Device simulations for IV curve generation
      • TCAD-based SPICE parameter extraction using HiSIM-IGBT compact model
      • Correlation between circuit performance and process variation
      • Circuit performance optimization


    DMOS Transistor cross-section


    ​N-channel IGBT cross-section

    I’ve attended previous Silvaco webinars and found them to be informative, detailed and hosted by technical authorities with deep experience. My favorite part of a webinar is the Q&A time at the end, when engineers get their questions answered by the expert.

    Related: Modeling and Analysis of Single Event Effects (SEE)

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    Big Data, the Cloud and the Internet of (Silicon) Things

    Big Data, the Cloud and the Internet of (Silicon) Things
    by Paul McLellan on 08-31-2014 at 7:01 am
    Categories: eSilicon, Semiconductor Services

    Next week, eSilicon are kicking off a very widespread survey to measure some important semiconductor design and manufacturing challenges. Their goal is to measure customer sentiment regarding how Big Data, the Cloud and the Internet can impact these challenges. But here’s a secret, the survey is already live and you can go and fill it in right now.

    I went through the survey (I didn’t finally submit it since my “latest design” was a blog post stored in the cloud on the internet but didn’t involve any silicon design). The survey is 22 questions long and will take 5-10 minutes to complete. And there are prizes! You’ll be entered to win one of five $100 Amazon gift certificates (or they will donate $100 to the Red Cross if you prefer).

    After asking you about the technology of your last design, eSilicon get onto what factors were difficult. Embedded software, quality/stability of project inputs, power closure, performance, yield management, area, IP bugs, test, packaging, and so on.

    Next, on to business challenges such as time to market, production leadtimes, production cost, mask tooling cost and more.

    The heart of the survey is how you want to see big data, the cloud and the internet leveraged in semiconductor design and manufacturing processes.

    I won’t run through all the questions. After all, you should really go over there and read them all and fill in your answers. The more data collected the more useful the responses will be.

    But question 18 is interesting. It asks which channels are most important for keeping you informed about semiconductor design and manufacturing. Newsletters, magazines, vendor websites, social media, conferences; and which ones. And of course blogs. This question should clearly be answered SemiWiki, although I might just be biased.


    The rubric from eSilicon says: Over the last 14 years eSilicon has optimized ASIC designs and accelerated time-to-market for our customers. Using our deep design and manufacturing experience, plus customizable IP, we’ve successfully delivered almost 200 million chips across 170+ customer designs. We’re working on a wide range of exciting designs today.

    We’ve always leveraged database and Internet technologies to automate our business, resulting in a more transparent, predictable and reliable experience for our customers. We see Big Data and the Cloud playing important roles going forward. We want to know what you think, to better understand your needs and ensure that our Big Data, Cloud and Internet of (Silicon) Things strategies are aligned.

    Your answers will be kept in confidence and your responses to our questions will not be used to try to sell you anything.

    The link to the survey is here.

    More articles by Paul McLellan…

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    Webinar: Collaboration Within Dispersed Design Teams

    Webinar: Collaboration Within Dispersed Design Teams
    by Daniel Nenni on 08-30-2014 at 7:00 am
    Categories: Cliosoft, EDA

    In the face of shrinking time-to-market windows, semiconductor companies are aggressively vying with each other to emerge with new or variants of existing ICs and SoCs to gain market share. The growth of the mobile market –wireless, networking, storage, and computing – as well as new areas such as the Internet of things (IoT) and wearables has resulted in an increased use of analog/mixed-signal (AMS) and/or RF functionality coupled with digital logic. To emerge as leaders in a specific market segment, design teams need to overcome increasing challenges to tape out chips successfully. Not only are teams using more IPs in a given design, they also are dealing with challenges such as developing complex functionality, managing multifaceted design flows using best-in-class tools, and complex mixed-signal verification, often in the face of shrinking geometries.

    Webinar registration: Flow to improve collaboration within dispersed design team

    Exacerbating all of the above is the difficulty of finding all the necessary talent in one location. This has resulted in semiconductor companies opening up design centers all over the world, wherever good talent is available, and investing heavily in the training of new college graduates. But for an SoC to be taped out on schedule, these dispersed design team members must work in tandem with each other as well as overcome their cultural and communication barriers. As the design teams get larger and spread across geographical boundaries, it becomes an increasing dilemma to coordinate the work amongst the team members, especially for analog and mixed-signal designs.


    For design team managers and engineers to be more productive and efficient, they need quick answers to questions such as:

    • What design changes have been checked in this week?
    • Is the layout for this design DRC/LVS clean?
    • The design was working yesterday. What changed?
    • Which revision of the schematic was the layout created for?
    • Which designs have been completed and frozen?
    • Looks like the schematic had some ECOs! What exactly changed?

    Managing large teams spread across multiple sites has never been very easy. It becomes more difficult when one considers the challenges of taping out a mixed-signal SoC successfully, across different time zones and cultures. To improve collaboration between multi-site design team members, it is important to lay the foundations of a good infrastructure and invest in data management software. Without the presence of design data management and a formal collaboration process, a lot of time is spent on needless communication. This often leads to a big loss of productivity for the engineers and creates spurious errors, which take considerable time to rectify.

    Also Read: Leveraging Design Team Energy!

    Of course, a data management solution has to work with complex design flows and enhance productivity rather than adding more overhead for the design engineers. To learn about a flexible, comprehensive and non-intrusive data management flow that works with different design tools and will help improve design collaboration between widely-dispersed team members, ClioSoft is giving a webinar on the use of the SOS Design Collaboration Platform integrated with Cadence Virtuoso® technology.

    Webinar registration: Flow to improve collaboration within dispersed design team

    Also Read

    Leveraging Design Team Energy!

    Webinar: Making Design Reuse Work

    Importance of Data Management in SoC Verification

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    Assertion Synthesis: From Startup to Mainstream

    Assertion Synthesis: From Startup to Mainstream
    by Daniel Payne on 08-30-2014 at 7:00 am
    Categories: EDA

    In college many of us dreamed of starting up our own company by offering something new that has never been done before. Today I spoke by phone with Yunshan Zhuin Shanghai, and he has actually lived out this scenario by founding NextOp in 2006, then getting that company acquired by Atrentain 2012. The new capability that NextOp created was something called assertion synthesis, and the product name is BugScope.


    Continue reading “Assertion Synthesis: From Startup to Mainstream”