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Semiconductor Expert Forum

Podcast EP212: A View of the RISC-V Landscape with Synopsys’ Matt Gutierrez

Podcast EP212: A View of the RISC-V Landscape with Synopsys’ Matt Gutierrez
by Daniel Nenni on 03-15-2024 at 10:00 am

Dan is joined by Matt Gutierrez. Matt joined Synopsys in 2000 and is currently Sr. Director of Marketing for Processor & Security IP and Tools. His current responsibilities include the worldwide marketing of ARC Processors and Subsystems, Security IP, and tools for the development of application-specific instruction set processors. Prior to joining Synopsys, Matt held various technical and management positions with companies such as Cypress Semiconductor, Fujitsu Limited, and The Silicon Group. Matt has over 25 years of experience in the semiconductor, computer systems, and EDA industries.

Matt provides an overview of what’s happening in custom processors and the impact of the RISC-V ISA. Matt also discusses what Synopsys is doing to enable application-specific processor design, including the recent announcement of its ARC-V processor IP.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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CEO Interview: Patrick T. Bowen of Neurophos

CEO Interview: Patrick T. Bowen of Neurophos
by Daniel Nenni on 03-15-2024 at 6:00 am
Categories: AI, CEO Interviews, Semiconductor Services, Silicon Catalyst

Patrick T. Bowen

Patrick is an entrepreneur with a background in physics and metamaterials. Patrick sets the vision for the future of the Neurophos architecture and directs his team in research and development, particularly in metamaterials design. He has a Master’s degree in Micro-Nano systems from ETH Zurich and PhD in Electrical Engineering from Duke University, under Prof. David Smith. After graduation, Patrick cofounded Metacept with Prof. Smith; Metacept is the world’s foremost metamaterials commercialization center and consulting firm.

Tell us about Neurophos. What problems are you solving?
We say we exist to bring the computational power of the human brain to artificial intelligence. Back in 2009 it was discovered that GPUs are much better at recognizing cats on the internet than CPUs are, but GPUs are not the answer to the future of AI workloads. Just as GPUs were better than CPUs for neural networks, there could be architectures that are better than GPUs by orders of magnitude. Neurophos is what comes next for AI after GPUs.

AI large language models in general have been limited because we haven’t had enough compute power to fully realize their potential. People have focused primarily on the training side of it, just because you had to train something useful before you could even think about deploying it. Those efforts have highlighted the incredible power of large AI models, and with that proof people are starting to focus on how to deploy AI at scale. The power of those AI models means we have millions of users who will use them every day. How much energy does it cost per user? How much does the compute cost per inference? If it’s not cheap enough per inference, that can be a very limiting thing for businesses  that want to deploy AI.

Energy efficiency is also a big problem to solve.  If you have a server that burns say 6 kiloWatts, and you want to go 100 times faster but do nothing about the fundamental energy efficiency, then that 6 kiloWatt server suddenly becomes a 600 kiloWatt server. At some point you hit a wall; you’re simply burning too much power and you can’t suck the heat out of the chips fast enough. And of course there are climate-change issues layered on top of that. How much energy is being consumed by AI? How much additional energy are we wasting just trying to keep data centers cool? So, someone needs to first solve the energy efficiency problem, and then you can go fast enough for the demands of the applications.

People have proposed using optical compute for AI for nearly as long as AI has existed. There are a lot of ideas that we work on today that are also old ideas from the 80s. For example, the original equations for the famous “metamaterials invisibility cloak”, and other things like the negative index of refraction, can be traced back to Russian physicists in the 60s and 80s. Even though it was sort of thought of, it was really reinvented by David Smith and Sir John Pendry.

Similarly, systolic arrays, which are typically what people mean when they say “tensor processor”, are an old idea from the late 70s. Quantum computing is an old idea from the 80s that we resurrected today. Optical processing is also an old idea from the 80s, but at that time we didn’t have the technology to implement it. So with Neurophos, we went back to reinventing the optical transistor, creating from the ground up the underlying hardware that’s necessary to implement the fancy optical computing ideas from long ago.

What will make customers switch from using a GPU from Nvidia, to using your technology?
So, the number one thing that I think most customers care about really is that dollars per inference metric, because that’s the thing that really makes or breaks their business model. We are addressing that metric with a solution that truly can increase the speed of compute by 100x relative to a state of the art GPU, all within the same power envelope.

The environmental concern is also something that people care about, and we are providing a very real solution to significantly mitigate energy consumption directly at one of its most significant sources: datacenters.

If you sit back and think about how this scales… someone has to deliver a solution here, whether it’s us or someone else. Bandwidth in chip packaging is roughly proportional to the square root of the area and power consumption in chip packaging is generally proportional to the area. This has led to all sorts of contorted ways in which we’re trying to create and package systems.

Packaging is one of the things that’s really been revolutionary for AI in general. Initially it was about cost and being able to mix chiplets from different technology nodes, and most of all, about memory access speed and bandwidth because you could integrate with DRAM chips. But now you’re just putting more and more chips in there!

Using the analog compute approach restores power consumption for compute down to the square root of area instead of proportional to area. So now the way in which your compute and power consumption scales goes the same way; you are bringing them into balance.

We believe we’ve developed the only approach to date for analog in-memory compute that can actually scale to high enough compute densities to bring these scaling laws into play.

How can customers engage with Neurophos today? 
We are creating a development partner program and providing a software model of our hardware that allows people to directly load PyTorch code and compile that. That provides throughput and latency metrics and how many instances per second etc. to the customer. It also provides data back to us on any bottlenecks for throughput in the system, so we can make sure we’re architecting the overall system in a way that really matters for the workloads of customers.

What new features/technology are you working on?
Academics have for a long-time sort of dreamt about what they might do if they had a metasurface like we’re building at Neurophos, and there are lot of theoretical papers out there… but no one’s ever actually built one. We’re the first ones to do it. In my mind most of the interesting applications are really for dynamic surfaces, not for static, and there is other work going on at Metacept, Duke, and at sister companies like Lumotive that I, and I think the world, will be pretty excited about.

Why have you joined the SC Incubator and what are the Neurophos’ goals in working with their organization over the next 24 months?

Silicon Catalyst has become a prestigious accelerator for semiconductor startups, with a high bar for admission.  We are excited to have them as a partner.  Hardware startups have a big disadvantage relative to software startups because of their higher demo/prototype cost and engineering cycle time, and this is even more true in semiconductor startups where the EDA tools and mask costs and the sheer scale of the engineering teams can be prohibitively expensive for a seed stage company.  Silicon Catalyst has formed a pretty incredible ecosystem of partners that provide significant help in reducing their development cost and accelerating their time to market.

Also Read:

A Candid Chat with Sean Redmond About ChipStart in the UK

CEO Interview: Jay Dawani of Lemurian Labs

Seven Silicon Catalyst Companies to Exhibit at CES, the Most Powerful Tech Event in the World

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Checking and Fixing Antenna Effects in IC Layouts

Checking and Fixing Antenna Effects in IC Layouts
by Daniel Payne on 03-14-2024 at 10:00 am
Categories: EDA, Siemens EDA
2 Comments

Planar CMOS cross-section – antenna DRC

IC layouts go through extensive design rule checking to ensure correctness, before being accepted for fabrication at a foundry or IDM. There’s something called the antenna effect that happens during chip manufacturing where plasma-induced damage (PID) can lower the reliability of MOSFET devices. Layout designers run Design Rule Checks (DRC) to find areas that violate PID and then make edits to pass all checks.

A traditional antenna design rule will measure the metal (or via) layer to MOSFET gate layer, and if the area ratio is too large then the layout must be fixed by adding a protection diode.

Planar CMOS cross-section – antenna DRC

One IC layout scenario that a traditional DRC for antenna effects cannot handle is for AMS designs that have multiple power domains, using multiple isolated P-type wells as shown below. A new approach called path-based verification is required for the following four scenarios.

Risk connection has PID issue
Imbalanced area ratios between metal layers and well layers from two isolated wells
Complex connectivity connections
Unintentional protection diodes

These four layout scenarios can only be detected by an EDA tool that knows about devices, connectivity and electrical paths during the area calculations for metal and MOSFET gate layers. This is where the Calibre PERC tool from Siemens EDA comes in, as it can perform the complex path-based checks to identify PID areas, find electrostatic discharge (ESD) issues, and locate other paths that your design group is looking for. Here’s the PID flow for using Caliber PERC:

PID flow using Calibre PERC

Using this flow on an IC layout and looking at the results in Calibre RVE results viewer showed that a PID violation was found, because a risk connection was established in metal1 level, but the protection connection didn’t happen until the metal2 level.

PID violation at metal2 layer

The next PID violation was identified from imbalanced area ratios of metal layer and the N-buried layer (nbl). The area highlighted in purple (rve) is the victim device.

Imbalanced area PID issue

To get complete PID coverage your design team will have to use both the traditional DRC-based antenna checks plus the path-based checks. Run DRC-type checks early in the design stages as a preventative step. As more metal connections in a layout are completed, then paths form across isolated P-type wells are made, it’s time to add path-based verification, providing complete coverage.

In this early IC layout it’s time to run traditional DRC-based antenna checks to confirm the layout passes PID validation.

Prevent PID issues before all metal connections completed

As more metal paths are added to the IC layout, then it’s time to use the path-based tool, because it properly understands both the risk connection and protection connection.

Run Calibre PERC path-based checks

Summary

IC layouts must meet rigorous design rules to pass reliability and yield requirements set by the foundry or fab process being used. Traditional DRC-based antenna design rules can still be used for early-stage layout, but as more metal layers are added to complete the interconnects, then a path-based checking with Calibre PERC becomes necessary.

As the paths across isolated P-wells are established, the path-based flow of Calibre PERC can be used to check the IC layouts at IP, block/module and even full-chip levels for signoff. So it’s recommended to use both flows together to meet the reliability and yield goals.

Read the Technical Paper at Siemens online.

Related Blogs

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Arteris is Unleashing Innovation by Breaking Down the Memory Wall

Arteris is Unleashing Innovation by Breaking Down the Memory Wall
by Mike Gianfagna on 03-14-2024 at 6:00 am
Categories: AI, Arm, Arteris, IP, RISC-V

Arteris is Unleashing Innovation by Breaking Down the Memory Wall
(courtesy of Arteris)

There is a lot of discussion about removing barriers to innovation these days. Semiconductor systems are at the heart of unlocking many forms of technical innovation, if only we could address issues such as the slowing of Moore’s Law, reduction of power consumption, enhancement of security and reliability and so on. But there is another rather substantial barrier that is the topic of this post. It is the dramatic difference between processor and memory performance. While systems of CPUs and GPUs are delivering incredible levels of performance, the memories that manage critical data for these systems are lagging substantially. This is the memory wall problem, and I would like to examine how Arteris is unleashing innovation by breaking down the memory wall.

What is the Memory Wall?

The graphic at the top of this post illustrates the memory wall problem. You can see the steady increase in performance of single-threaded CPUs depicted by the blue line. The green line shows the exponential increase in performance being added by clusters of GPUs. The performance increase of GPUs vs. CPUs is estimated to be 100X in 10 years – a mind-boggling statistic. As a side note, you can see that the transistor counts for both CPUs and GPUs cluster around a similar straight line. GPU performance is delivered by doing less tasks much faster as opposed to throwing more transistors at the problem.

Many systems today are a combination of a number of CPUs doing broad management tasks with large numbers of GPUs doing specific tasks, often related to AI. The combination delivers the amazing throughput we see in many products. There is a dark side to this harmonious architecture that is depicted at the bottom of the chart. Here, we see the performance data for the various memory technologies that deliver all the information for these systems to process. As you can see, delivered performance is substantially lower than the CPUs and GPUs that rely on these memory systems.

This is the memory wall problem. Let’s explore the unique way Arteris is solving this problem.

The Arteris Approach – A Highly Configurable Cache Coherent NoC

 A well-accepted approach to dealing with slower memory access speed is to pre-fetch the required data and store it in a local cache. Accessing data this way is far faster – a few CPU cycles vs. over 100 CPU cycles. It’s a great approach, but it can be daunting to implement all the software and hardware required to access memory from the cache and ensure the right data is in the right place at the right time, and consistent across all caches. Systems that effectively deliver this solution are called cache coherent, and achieving this goal is not easy. A software-only coherency implementation, for example, can consume as much as ~25% of all CPU cycles in the system, and is very hard to debug. SoC designers often choose cache coherent NoC hardware solutions instead, which are transparent to the software running on the system.

Andy Nightingale

Recently, I had an opportunity to speak with Andy Nightingale, vice president product management & marketing at Arteris. Andy did a great job explaining the challenges of implementing cache coherent systems and the unique solution Arteris has developed to cope with these challenges.

It turns out development of a reliable and power efficient cache coherent architecture touches many hardware and software aspects of system design. Getting it all to work reliably, efficiently and hit the required PPA goals can be quite difficult. Andy estimated that all this work could require 50 engineering years per project. That’s a lot of time and cost.

The good news is that Arteris has substantial skills in this area and the company has created a complete cache coherent architecture into one of its network-on-chip (NoC) products. Andy described Ncore, a complete cache coherent NoC offered by Arteris. Management of memory access fits well in the overall network-on-chip architecture that Arteris is known for. Ncore manages the cache coherent part of the SoC transparently to software – freeing the system designer to focus on the higher-level challenges associated with getting the CPU and all those GPUs to perform the task at hand.

Andy ran down a list of Ncore capabilities that was substantial:

  • Productive: Connect multiple processing elements, including Arm and RISC-V, for maximum engineering productivity and time-to- market acceleration, saving 50+ person-years per project.
  • Configurable: Scalable from heterogenous to mesh topologies, supporting CHI-E, CHI-B, and ACE coherent, as well as ACE-Lite IO coherent interfaces. Ncore also enables AXI non-coherent agents to act as IO coherent agents.
  • Ecosystem Integration: Pre-validated with the latest Arm v9 automotive cores, delivering on a previously announced partnership with Arm.
  • Safe: Supporting ASIL B to ASIL D requirements for automotive safety applications, and being ISO26262 certified.
  • Efficient: Smaller die area, lower power, and higher performance by design, compared with other commercial alternatives.
  • Markets: Suitable for Automotive, Industrial, Enterprise Computing, Consumer and IoT SoC solutions.

Andy detailed some of the benefits achieved on a consumer SoC design. These included streamlined chip floorplanning thanks to the highly distributed architecture, promoting efficient resource utilization. The Arteris high-performance interconnect with a high-bandwidth, low-latency fabric ensured seamless data transfer and boosted overall system performance.

Digging a bit deeper, Ncore also provides real-time visibility into the interconnect fabric with transaction-level tracing, performance monitoring, and error detection and correction. All these features facilitate easy debugging and superior product quality. The comprehensive ecosystem support and compatibility with industry-standard interfaces like AMBA, also facilitate easier integration with third-party components and EDA tools.

This was a very useful discussion. It appears that Arteris has dramatically reduced the overhead for implementation of cache coherent architectures.

To Learn More

I mentioned some specifics about the work Arteris is doing with Arm. Don’t think that’s the only partner the company is working with. Arteris has been called the Switzerland of system IP. The company also has significant work with the RISC-V community as detailed in the SemiWiki post here.

Arteris recently announced expansion of its Ncore product. You can read how Arteris expands Ncore cache coherent interconnect IP to accelerate leading-edge electronics designs here.  In the release, Leonid Smolyansky, Ph.D. SVP SoC Architecture, Security & Safety at Mobileye offered these comments:

“We have worked with Arteris network-on-chip technology since 2010, using it in our advanced autonomous driving and driver-assistance technologies. We are excited that Arteris has brought its significant engineering prowess to help solve the problems of fault tolerance and reliable SoC design.”

There is also a short (a little over one-minute) video that explains the challenges that Ncore addresses. I found the video quite informative. 

If you need improved performance for your next design, you should definitely take a close look at the cache coherent solutions offered by Arteris. You can learn more about Ncore here. And that’s how Arteris is unleashing innovation by breaking down the memory wall.

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2024 Outlook with Elad Alon of Blue Cheetah Analog Design

2024 Outlook with Elad Alon of Blue Cheetah Analog Design
by Daniel Nenni on 03-13-2024 at 10:00 am
Categories: Blue Cheetah Analog Design, Chiplet, IP

elad alon sq

We have been working with Blue Cheetah Analog Design for three years now with great success. With new process nodes coming faster than ever before and with chiplets being pushed to the forefront of technology, the die-to-die interconnect traffic on SemiWiki has never been greater and chiplets is one of our top search terms.

Tell us a little bit about yourself and your company. 
I am the CEO and co-founder of Blue Cheetah Analog Design. I am also an Adjunct Professor of Electrical Engineering and Computer Sciences at UC Berkeley, where I was previously a Professor and co-director of the Berkeley Wireless Research Center (BWRC). I’ve held founding, consulting, or visiting positions at Locix, Lion Semiconductor (acquired by Cirrus Logic), Wilocity (acquired by Qualcomm), Cadence, Xilinx, Sun Labs, Intel, AMD, Rambus, Hewlett Packard, and IBM Research, where I worked on digital, analog, and mixed-signal integrated circuits for computing, high-speed communications, and test and measurement. According to Lance Leventhal at the Chiplet Summit, I have 280 published articles and 75+ patents. I have to admit I’m not sure about those numbers, but I do have a lot of experience with integrated circuit design – and particularly in analog / mixed-signal circuits – which is proving invaluable in the era of chiplets.  This is the last I’ll say about myself directly – in the rest of this interview, I’ll be telling the story of Blue Cheetah and our vision for chiplets and the overall semiconductor market.

What was the most exciting high point of 2023 for your company?
We announced silicon success on our die-to-die interconnect IP and picked up many exciting design wins. We’ve publicly disclosed DreamBig, Ventana, and FLC as our customers, and most recently, we announced our design win with Tenstorrent. We will announce more design wins soon. To our knowledge, most of the emerging chiplet product companies are using Blue Cheetah die-to-die interconnect, as are a number of large corporations.

What was the biggest challenge your company faced in 2023?
Thanks to the amazing support (not only financially) from our investors – particularly from our founding investors Sehat Sutardja and Weili Dai, as well as NEA (which led our Series B round in 2022) – along with our unique product offering (customized die-to-die interconnect IP), I’m happy to say that funding and filling the sales funnel have not been our biggest challenges. Keeping up with demand, on the other hand, is definitely keeping us on our toes; I always like to tell the members of my team that this is a very good challenge to have the opportunity to address.  The tremendous momentum building around chiplets drives the demand for Blue Cheetah’s solutions, so in some senses, the challenge is in scaling up along with that ongoing revolution.

How is your company’s work addressing this biggest challenge?
In the bigger picture, hardware and silicon designers look to chiplets as a key enabler for ever more capable and cost-efficient systems. Chiplets are well established amongst large players that control all components/aspects of a design (i.e., single vendor), and the allure of a “plug and play” chiplet market has garnered significant attention and investment from the industry.  Although a number of technical and business hurdles need to be overcome before that vision fully comes to fruition, the large majority of the benefits of that vision can be realized immediately.  Specifically, small groups of companies with aligned product strategies and (typically) complementary expertise are forming multi-vendor ecosystems.  Within these ecosystems, the companies can coordinate on the functionality, requirements, and interfaces of each chiplet (and, of course, the die-to-die interconnects that glue them together) to meet the needs of a specific product and/or product family. Blue Cheetah’s solutions support all three of these use cases (single-vendor, multi-vendor ecosystem, and plug-and-play), and many of our customers/partners are pioneers of the multi-vendor ecosystem approach.

What do you think the biggest growth area for 2024 will be, and why?
Indeed, the semiconductor market is in the middle of a major resurgence in recognition, investment, and (averaged over the last ~3 years) growth.  AI has played an enormous role in this resurgence. Still, the basis is broader than that – consider, for example, that today, 7 out of the top 10 companies, as ranked by market capitalization design, incorporate and/or sell their own semiconductors. (If you look at the top 10 tech companies by market cap, it goes to 9 out of 10, with the 10th being a semi manufacturing equipment supplier.)  The capabilities/cost structure of a company’s chips directly drives the user experience/value of the company’s products/services, and the companies delivering those products are in the best position to know what silicon capabilities/cost structure have the highest impact.  This hopefully makes it clear why specialization and customization are major themes; they have been for ~5+ years already and will continue to be in 2024 (and beyond).

How is your company’s work addressing this growth?
Chiplets are, in principle, the ideal vehicle to achieve the goals of specialization and customization with favorable manufacturing and design cost structures.  Ideally, a company can focus on its differentiating technologies while incorporating leading solutions to the remaining components of the product via (possibly other vendors’) chiplets and IP. At the same time, each chiplet can be targeted to the specific manufacturing technology / die size with the best cost/yield characteristics for that function.  Of course, all of these chiplets need to communicate with each other, and that is where Blue Cheetah is focused.  Blue Cheetah is unique in offering die-to-die interconnect solutions with the extensive customizability and configurability needed to meet the needs of the full range of chiplet products.  We also support the most comprehensive set of process technologies – we have already implemented our IP in 7 different nodes, including 5nm and below.

What conferences did you attend in 2023, and how was the traffic?
2023 was an action-packed year for us in terms of conferences – I believe someone from the Blue Cheetah team was at a conference once every month or at most two – and in-person attendance is definitely up (approaching or exceeding pre-COVID levels).  For example, we were at the Chiplet Summit, ISSCC, DAC, OCP Global Summit, and several foundry events. Our silicon demo generated a lot of interest, and we were very happy with the engagement from the people and partners who visited our booth.

Will you attend conferences in 2024? Same or more?
2024 is looking to be even more action-packed – both in terms of conferences (we’ve already been at CES and the Chiplet Summit) and more broadly.  With the global drive to establish and rejuvenate local semiconductor capabilities, we plan to expand to additional international venues this year to further foster relationships across a broad industry base.

Also Read:

Chiplet ecosystems enable multi-vendor designs

Die-to-Die Interconnects using Bunch of Wires (BoW)

Analog Design Acceleration for Chiplet Interface IP

Blue Cheetah Technology Catalyzes Chiplet Ecosystem

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Automotive Electronics Trends are Shaping System Design Constraints

Automotive Electronics Trends are Shaping System Design Constraints
by Bernard Murphy on 03-13-2024 at 6:00 am
Categories: AI, Automotive, Cadence, EDA, IP

Electronics in car

Something is brewing in automotive electronics. Within a one-month window most of the product announcements and pitches to which I am being invited are on automotive topics. Automotive markets have long been one of the primary targets for suppliers to system designers, but this level of alignment in announcements seems more than a coincidence. Pulin Desai (Group Director, Product Marketing and Biz Dev for Tensilica Vision and AI DSPs at Cadence) helped me understand some of the motivation. He sees two key drivers in automotive: demand for a consolidated view of software development across a diverse set of platforms (central, zonal and edge) and demand to limit hardware development cost. The Cadence Tensilica group has expanded its product line to meet these trends, particularly in support of advanced perception around the car and in the cabin.

Managing “smarter everywhere” versus software complexity and cost

Intelligence is touching everything in the car. Emerging trends are in intelligent backup camera and rear-view mirrors, now with object recognition to detect a child or a dog behind the car. Inside the cabin for driver management systems, sensing when the driver is not paying attention. For occupancy monitoring systems (OMS) detecting if you left a child in the car when you leave. Interestingly both DMS and OMS use a combination of video and radar monitoring.

For perception outside the car, we’re already familiar with forward-facing video paired with object detection to sense collision risks and for lane keeping. These now routine safety features are being coupled with 4D imaging radar (4DR), adding a rich and less weather-sensitive complement to video perception. Video plus 4DR will offer new levels of capability and safety such as adaptive cruise control, essential to further advances in ADAS and autonomy.

Combined, these are all appealing features, but OEMs/Tier1s are eventually stuck with integrating everything in software to manage control through the cockpit screen and other controls, for navigating, playing high quality audio, saving power, handling safety, activating AC, etc, etc. Making that integration manageable demands unified software-defined across all these distributed functions.

On the hardware front, while there is a lot of buzz around AI suppliers, AI parts alone are far from enough to build what the OEMs need: signal processing for object recognition before AI, specialized accelerators to handle 4D point clouds, efficient and cost-effective inferencing for the non-generative AI tasks. Add to that all the other necessary compute functions (CPU cluster, memory management, communication, etc). With the performance and low power delivered by the most advanced semiconductor processes, integrated in single package solution to keep costs down.

How do OEMs square this circle? Pulin says he sees the leaders each pushing their own common differentiated platform architectures, hosting distributed compute around the car, across model lines, and into the future. While also reducing cost and keeping car prices reasonably in line with our expectations. Very interesting.

Stepping up to the trend

Think about vision+radar applications as an illustrative example. However partitioned, the system starts with a camera for image capture followed by a complex chain of image signal processing functions (DSP-based) – before any AI operations can begin. The radar starts with an antenna (maybe 16×16 receive/transmit) followed by an equally complex chain of signal processing to generate a 4D radar point cloud, again before AI-based recognition.

Radar signal processing uses complex Fourier analysis, an algorithm manageable on a DSP for 1D or 2D radar with relatively low field of view and resolution. However, 4D imaging radar has a higher field of view and higher resolution, generating huge amounts of data per frame for which additional hardware assistance is needed to achieve acceptable frame rates.

Cadence has just announced their Tensilica Vision 331 and Vision 341 DSPs to support signal processing for computer vision and radar imaging together with entry-level AI (such as driver face-id) and sensor fusion. Both cores deliver improved power, performance and area for high-end multi-sensor processing. They also offer a radar boost mode through instruction set optimizations, delivering up to 4X performance improvement for Vision 331 and up to 6X performance improvement for Vision 341. Plugging in an optional Vision 4DR accelerator for big radar data cubes delivers a further 4X in performance for the 341 core (together with a 6X area advantage) and up to 7X performance boost for the 331 core. The DSP cores also extend AI performance up to 80 TOPS when paired with a single (Cadence) Neo NPU.

How do such options help OEMs reduce chip types while supporting scalability? Before we even get to chiplets and multi-die solutions, consider a single-chip heterogeneous IP-based design. Routine stuff for those of us in the SoC design world. Unfortunately, it seems media saturation coverage on a certain GPU for AI has led some folks outside the chip world to believe that GPUs are the necessary, maybe even sufficient minimum for any automation. Not realizing that outside of datacenters, heterogeneous design is king (just look at smartphones).

Heterogeneous design (image above) builds around a mix of multiple core functions. Multiple DSPs to handle the signal processing for perception-heavy applications representative of the bulk of new and emerging auto electronics. Domain-specific accelerators to ensure high frame-rate throughput. Compact and cost-effective neural accelerators (not GPUs) to handle the bulk of convolutional recognition tasks. A GPU if needed for high-end (transformer) AI models, communication IPs, CPUs for control and memory management.

This general approach to system-on-chip (SoC) is already well proven in many proprietary and off-the-shelf chips, including those from automotive semiconductor suppliers. It’s not a big leap to imagine that OEMs could design (or outsource design for) their own unique system architectures following a similar approach. Providing them with one multi-purpose design whose cost they can amortize across most applications in the car, excepting perhaps central compute (big, expensive devices) and drivetrain MCUs (tiny, very low cost devices).

What about a consolidated view of software?

For an OEM software developer, if almost every chip in a car is an instance of their common platform chip this problem is largely solved. Of course, the underlying IPs should share common, standards-based APIs: OpenCL for both DSPs and GPUs, Simulink for connection to MATLAB, together with the usual AI model interfaces (ONNX, TensorFlow and PyTorch). Exactly what the whole Tensilica IP line supports together with their NeuroWeave software compiler toolchain to map from the standard trained networks (TensorFlow, MXNet, PyTorch, Caffe2 and Jax) to the target device.

I can’t help thinking that the auto OEMs must be drawing inspiration from Amazon AWS success with their Graviton platform, now distributed widely across their datacenters and a unified focus for innovation in following generations (a trend also happening in other hyperscalers). Common heterogenous architecture auto platforms will be quite different in some ways, but the long-term value of a common platform is not so different.

You can learn more about the latest Tensilica release HERE.

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2024 Outlook with Jim Cantele of Altair

2024 Outlook with Jim Cantele of Altair
by Daniel Nenni on 03-12-2024 at 10:00 am
Categories: AI, Altair, EDA

Jim Cantele

Jim Cantele, global SVP of sales and technology at Altair, is an electronics industry veteran with deep knowledge of EDA software and services. Before joining Altair during the acquisition of Runtime Design Automation in 2017, Jim held executive-level management positions at a number of leading EDA and semiconductor companies, including Cadence, Siemens (Mentor Graphics), Samsung Semiconductor, and Microchip (Supertex). We worked with Runtime Automation before the acquisition and have known Jim for many years.

Tell us a little bit about yourself and your company.
Altair is a global leader in computational intelligence that provides software and cloud solutions in simulation, high-performance computing (HPC), data analytics, and AI. Altair enables organizations across all industries to compete more effectively and drive smarter decisions in an increasingly connected world — all while creating a greener, more sustainable future.

As global SVP of sales and technology at Altair, I’ve been fortunate to be at the center of many exciting innovations across the company, acquisitions of complementary technologies that have broadened our solutions portfolio, and partnerships with future-facing organizations to collaborate on today’s accelerated-growth areas including AI and quantum computing. After spending time at large enterprises including Cadence and Mentor Graphics, as well as startups such as One Spin Solutions, Celestry, and Runtime Design Automation — which was acquired by Altair in 2017 — I can appreciate that Altair offers the best of both worlds: It’s not only a solid, established company but also an agile organization that encourages diversity, creativity, and innovative thinking.

What was the most exciting high point of 2023 for your company?
It’s hard to pick just one! Last year was packed with new solutions. We announced Liquid Scheduling to scale distributed computing with our Altair® PBS Professional® workload manager, as well as Altair® InsightPro™ for streamlined HPC and cloud reporting. For the EDA space we introduced an integrated solution built with our Altair® Accelerator™ scheduler combined with Altair® NavOps® for dynamic cloud scaling, and we also created a dashboard that combines Accelerator with our data analytics solutions. Nothing is as exciting as launching an innovation that will move computing forward and make it easier for users to design, engineer, and make new discoveries.

What was the biggest challenge your company faced in 2023?
Many of our recent challenges have focused on convergence. The lines between on-premises vs. cloud, HPC vs. high-throughput computing, and similar traditionally divergent technologies are blurring, and every tech company needs to deliver solutions that incorporate many different elements that, in today’s world, commonly include machine learning (ML), deep learning (DL), and AI. Many of our customers’ product integrations require combinations of data analytics, simulation, and HPC technologies to be successful, and they all have different challenges on top of various resource and budget constraints. Our challenge at Altair is to pull all the right technologies together and deliver them in an effective, easy-to-use package.

How is your company’s work addressing this biggest challenge?
We’re developing and delivering advanced AI-driven solutions that leverage, among other technologies, our Altair® RapidMiner® data analytics and AI platform. RapidMiner enables users to extract and transform their data, build data and machine learning workflows, and process and display real-time data. We’ve found that RapidMiner is very useful in combination with other Altair solutions, and work is ongoing to fuse synergistic technologies like these to benefit users on a whole new level. Work is ongoing and we’ll unveil additional solutions with new and combined capabilities in 2024.

What do you think the biggest growth area for 2024 will be, and why?
We have three focus areas: data analytics, simulation, and HPC, each with different major growth areas. For semiconductor companies, we’re seeing an increase in demand for HPC job requirements at runtime, both on-premises and in the cloud. They need advanced information on workflow, memory, core count, and license requirements. We’re also focused on both the immediate uses for and the future potential of AI, which is becoming increasingly pervasive in today’s world. Quantum computing is still new and flawed, with problems scaling for real-world problems, but it’s a big future growth area too.

How is your company’s work addressing this growth?
Our product integrations with AI and ML via RapidMiner is addressing the market and setting organizations up with a path to modernization and automation. The analytic power of the RapidMiner platform, combined with Altair simulation and HPC tools, is quickly delivering results in this area. There will be more to come throughout 2024.

What conferences did you attend in 2023 and how was the traffic?
In 2023 I attended some informative TSMC semiconductor events, as well as the Design Automation Conference in San Francisco. DAC was extremely well-attended with lots of networking opportunities and visits with old friends and colleagues, plus an exciting view into the latest technologies from vendors throughout the semiconductor and EDA industry. Everyone seemed eager to participate and engage. Multiple Altair Technology Conferences (ATCs) were an excellent opportunity to discuss the latest trends, technologies, and innovations powered by the convergence of computational science and AI. Altair also participates in the SC supercomputing conference each fall, plus several smaller conferences throughout the year.

Will you attend conferences in 2024? Same or more?
We’ve already started the year off with a bang: This January was Altair’s first time at CES (formerly the Consumer Electronics Show) in Las Vegas. CES was quite an event, packed with tech enthusiasts and rolling along with a high energy level and enthusiastic crowd — a fascinating and informative experience. I’m looking forward to attending DAC again this summer and SC24 in Atlanta this fall, plus worldwide GSA and TSMC events. I’ll rarely pass up an opportunity to connect with colleagues and customers and learn more about everyone’s latest advances.

Additional questions or final comments?
Today’s tech world is an exciting place to be, with immense growth and even greater growth potential. At Altair, I’m proud to be part of the technological evolution that’s converging to move computing, business, and knowledge forward. It’s the technology our future will be built on.

Also Read:

Altair’s Jim Cantele Predicts the Future of Chip Design

How to Enable High-Performance VLSI Engineering Environments

Optimizing Return on Investment (ROI) of Emulator Resources

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No! TSMC does not Make 90% of Advanced Silicon

No! TSMC does not Make 90% of Advanced Silicon
by Scotten Jones on 03-11-2024 at 2:00 pm
Categories: Foundries, Semiconductor Services, TechInsights, TSMC
26 Comments

Slide1

Throughout the debate on fab incentives and the Chips Act I keep seeing comments like; TSMC makes >90% of all advanced silicon, or sometimes Taiwan make >90% of all advanced silicon. This kind of ill-defined and grossly inaccurate statement drives me crazy. I just saw someone make that same claim in the SemiWiki forums and I decided it was time to comment on this.

Let’s start with defining what is an advanced semiconductor. Since the specific comment is about TSMC, let’s start with the TSMC definition, TSMC breaks out 7nm and below as advanced. This is a good break point in logic because Samsung and TSMC 7nm both have densities of approximately 100 million transistor per millimeter squared (MTx/mm2). Intel 10nm also has approximately 100 MTx/mm2, therefore we can count Samsung and TSMC 7nm and below and Intel 10nm and below.

That all works for logic, but this whole discussion ignores other advanced semiconductors. I would argue that there are three truly leading edge advanced semiconductors in the world today where state-of-the-art equipment is being pushed to the limits of what is achievable: 3DNAND, DRAM, and Logic. In each case there are three or more of the worlds largest semiconductor companies pushing the technology as far and as fast as humanely possible. Yes, the challenges are different, 3DNAND has relatively easy lithography requirements but deposition and etching requirements are absolutely at the edge of what is achievable. DRAM has  a mixture of lithography, materials and high aspect ratio challenges. Logic has the most EUV layers and process steps but they are all equally difficult to successfully produce with good yield.

Including 3DNAND and DRAM means we need an “advanced semiconductor” limits for these two processes. When 7nm was first being introduced for logic, 3DNAND was at the 96/92 layer generation and DRAM was at 1y. We will use those as the limits for advanced semiconductors.

In order to complete this analysis without spending man-days that I don’t have to spare, I simply added up the worldwide installed capacity for 3DNAND 96/92L layers and greater, DRAM 1y and smaller and Logic 7nm (i10nm) and smaller. Furthermore I broke out logic into TSMC and other.

Figure 1 illustrates the worldwide installed capacity in percentage broken out by those categories.

Figure 1. Worldwide Advanced Silicon Installed Capacity by Category.

From figure 1 it can be seen that TSMC only represents 12% of worldwide “advanced silicon”, way off the 90% number being thrown around. Now utilization could change these numbers some and I haven’t included that due to time constraints, but I don’t think it would change this that much and as the memory sector recovers it will become a non issue.

I also looked at this a second way which is just worldwide advanced logic, see figure 2.

Figure 2. Worldwide Advanced Logic Installed Capacity by Category.

From figure 2 we can see that even when we look at Advanced Logic TSMC is only 64% versus “90%”.

The only way we would get to 90% is if we defined “advanced silicon” as 3nm logic. This would require a good definition of what 3nm logic is. On a density basis TSMC is the only 3nm logic process in the world, Samsung and Intel are really 5nm processes on a density basis, although Intel i3 is in my estimation the highest performing process available.

In conclusion, TSMC actually only makes up 12% of worldwide Advanced Silicon and only 64% of Advanced Logic. This is not to minimize the importance of TSMC to the global electronics supply chain, but when debating things as important as the worldwide semiconductor supply chain we should at least get the numbers right.

Also Read:

ISS 2024 – Logic 2034 – Technology, Economics, and Sustainability

How Disruptive will Chiplets be for Intel and TSMC?

2024 Big Race is TSMC N2 and Intel 18A

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2024 Outlook with Hassan Triqui CEO of Secure-IC

2024 Outlook with Hassan Triqui CEO of Secure-IC
by Daniel Nenni on 03-11-2024 at 10:00 am
Categories: Secure-IC, Security

Hassan Triqui

Hassan TRIQUI has over 20 years of experience in the technology sector. Prior to spearheading Secure-IC’s development into a major player in embedded cybersecurity solutions, Hassan was a former senior executive at Thales and Thomson. Hassan is a pioneer, a Brittany Tech patriot, and passionate about providing solutions that generate the real trust that clients deserve.

Secure-IC is the rising leader in embedded cybersecurity for embedded systems and connected objects. Established back in 2010, the company has accomplished major milestones such as more than a billion IPs (Intellectual Properties) deployed, and more than 250 patents and 350 scientific publications.

Secure-IC offers cutting-edge technologies that are fully digital, certifications compliant, and silicon proven (Securyzr™), complemented by its cybersecurity evaluation tools (Laboryzr™) and its expertise for certifications and consulting services (Expertyzr™). All being backed-up by a strong and experienced team making it the only one-stop-shop for embedded security solutions.

Tell us a little bit about yourself and your company.
Today, Secure-IC is proud to be the security provider for numerous renowned customers around the world in different applications. For instance, MediaTek with its flagship Dimensity 9300 implementing AI for mobile, or UnseenLabs with its satellites fleet implementing PQC (Post-Quantum Cryptography) to ensure a safer world.

This incredible story relies on its co-founders who supported this project and conveyed it straight to success thanks to all Secure-IC’s workforce along the years. Our leadership and management ensure every day that Secure-IC continues to develop best of breed security solutions and satisfy its customers by guiding the company towards its ‘Chip-to-Cloud’ vision. One key success factor that enabled the company to succeed was and still is its commitment to its global ecosystem.

What was the most exciting high point of 2023 for your company?
Secure-IC has been showing a high growth rate for a couple of years and therefore is starting to check major milestones.

Indeed, one exciting milestone for 2023 was the construction of its brand-new international headquarters based in Rennes, France. This new HQ has for objectives to offer the best conditions to its engineering workforce with high-tech laboratories and top performance datacenter for faster and safer data. Moreover, customers and security partners will be able to observe what Secure-IC has been achieving for the last years with its showroom displaying top-notch technologies from around the world.

What was the biggest challenge your company faced in 2023?
From a start-up to a global corporation with more than 150 employees nowadays, Secure-IC’s biggest challenge in 2023 was managing the growth. Indeed, not only did the workforce keep on growing fast across the globe, but the company’s revenues also kept the pace to a 2-digit growth each year, making Secure-IC one of the key players in the industry.

Such growth implies ‘change management’ at both corporate and operational levels, required for the corporation to scale-up and better serve its customers while minimizing the impact on people by making it as smooth as possible. At Secure-IC, action plans and long-term vision have been established to ensure this transition is realized in the best way possible.

How is your company’s work addressing this biggest challenge?
As explained before, this challenge was long before predicted by Secure-IC’s management team and therefore being handled carefully.

Hence, one objective that has been identified was the streamlining of internal processes. By doing so, the company ensures that its customers have the best experience with its project management team and that they are well served across the world. As a result, Secure-IC is proud of its 95%+ satisfaction rate, showing the strong relationship that exists between the company and its customers, as intended by its mission being to partner.

On top of that, Secure-IC aims at remaining the leader in terms of technology. Therefore, the company also addresses its challenge of growth by keeping on sharpening its differentiating technologies, as well as developing a clear product portfolio coupled with ambitious roadmaps to make sure that it offers best of breed technology and products including PQC and AI for instance.

What do you think the biggest growth area for 2024 will be, and why?
The 21st century is marked with its non-stop hockey stick curve-based technological improvements, which is especially illustrated through Moore’s law for semiconductors. As a result, not only pure software-based technologies were brought out to every application of our daily lives, but semiconductors too.

One example is the automotive industry. Moving from simple architectures with limited embedded systems on board to complex architectures (ECUs for each function to ZCUs controlling parts of the vehicle), cars from tomorrow are now being completely reinvented. Such technological improvements require from global organizations and governmental administrations to converge on global standards for ensuring optimized autonomous driving systems connected with the environment (V2V – Vehicle to Vehicle and V2X – Vehicle to Everything communications) as well on certifications to ensure both the security and safety of drivers and their environment (ISO 21434, ISO 26262…).

Such complexity opens doors to more attacks, being as complex as their target. One example, the successful attack targeting a Tesla shows the world how critical it has become to secure embedded systems against both physical and software attacks.

We also foresee other key driving forces in the industry. One example that keeps on growing every day is the rising popularity of Artificial Intelligence (AI) (esp. generative AI) and the explosion of the associated use cases. These functions will have to be implemented in devices and leverage the acceleration of hardware.

Security is an absolute must-have for any AI-application and its implementation in chipsets and devices in general since data must be protected, from the cloud all the way down to the chip (as described by Secure-IC’s Chip-to-Cloud vision), from the training data to the model itself, while preserving privacy, etc. Chipmakers and system companies are already starting to develop and produce ‘AI-chips’, which must be ‘trustworthy’ to be adopted.

AI will also make some attacks easier to perform and threats more dangerous.

Of course, AI is also an incredible technology to enhance security functions and design security policy.

Last, datacenter security and chiplets will be key trends to be closely followed-up.

How is your company’s work addressing this growth?
To address the evolution of the automotive space, Secure-IC’s teams produce significant efforts in understanding the needs of the whole value chain including the OEMs and Tier 1 with key partnerships and projects. In other words, Secure-IC not only listens to its customers but also to its customers’ customers to make sure its long-term vision and product roadmaps are accurate and maximizes the value it brings to the table.

As a matter of fact, Secure-IC is proud to offer its customers safe and secure technologies, such as ISO 26262 ASIL-D compliant security solutions ensuring them best of breed security according to global standards.

Regarding AI, Secure-IC already has its Securyzr™ solutions adapted to the AI-threat models. We are also deeply and constantly investigating on how the use of AI can enhance our portfolio and productivity (both on the protection and analysis sides), as proven by the launch of our Intrusion Detection System IDS (attached to our integrated Secure Element S700 Series for Automotive), leveraging AI.

What conferences did you attend in 2023 and how was the traffic?
Secure-IC has a very unique positioning of thought leadership in embedded cybersecurity and works by definition in an international stage. Therefore Secure-IC participate and speak at more than 4 events per month, which is very special for a company our size.

In 2023, Secure-IC actively participated in major global conferences, including CES Las Vegas, DAC, Mobile World Congress, Embedded World, ICCAD in China, Indocrypt in India, or Chipex in Israel. Secure-IC’s presence is aimed at showcasing cutting-edge technologies, connecting with customers, and gathering industry insights, but also to leading technology and scientific conferences worldwide.

These conferences provided a great platform to engage with diverse audiences and contribute to the cybersecurity community. The launch of the Security Science Factory (Secure-IC’s innovation engine) underlines the commitment to knowledge dissemination and cybersecurity awareness. The response was overwhelming, with booths and sessions attracting substantial traffic, reinforcing the impact of Secure-IC in the cybersecurity landscape.

Will you attend conferences in 2024? Same or more?
Absolutely, in 2024, Secure-IC is poised for even greater visibility and presence on the global stage. As a fast-growing company, our commitment is to align our growth with an increased presence at industry events. To achieve this, our executives and representatives are planning to attend approximately 50 conferences worldwide.

Also, we are planning our important product announcements alongside those key moments in the year.

We encourage you to visit our booth at Mobile World Congress in Barcelona this February (booth 5B41-2), at FIC (International Cybersecurity Forum) in March or Embedded World next April.

Additional questions or final comments?
In this multi-connected world, embedded security is needed everywhere. Secure-IC positions itself in a way that customers can find a unique answer encompassing multiple security concerns of theirs while keeping in contact with only one provider: One-Stop-Shop.

Secure-IC successfully served more than 250 customers across the globe since its incorporation and will continue to do so by providing security solutions that go one step further from Chip-to-Cloud with a key goal: enabling trusted data.

If you want to learn more information about Secure-IC we invite you to subscribe to our monthly newsletter here.

Also Read:

Rugged Security Solutions For Evolving Cybersecurity Threats

Cyber-Physical Security from Chip to Cloud with Post-Quantum Cryptography

How Do You Future-Proof Security?

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How Sarcina Technology Makes Advanced Semiconductor Package Design Easier

How Sarcina Technology Makes Advanced Semiconductor Package Design Easier
by Mike Gianfagna on 03-11-2024 at 6:00 am
Categories: Sarcina Technology, Semiconductor Services

How Sarcina Technology Makes Advanced Semiconductor Package Design Easier

For a long time, package engineering was part of the cleanup crew for chip design. The glory was all around the design of advance monolithic chips on the latest technology node. Once the design was done, the package/test team would take the design over the finish line, adding the required I/O specs, lead frame, load board and test program. It wasn’t a glorious job. Over the past decade or so, that has all changed. Today, packaging requires the integration of many parts of the system, with demanding thermal and performance characteristics. Testing and qualification are also a lot more complex and difficult, requiring the coordination of many supply chain entities to get it right. Simply put, the package engineer is now a rock star. These skills are quite valuable. In this context, read on to see how Sarcina Technology makes advanced semiconductor package design easier.

The Last Mile Problem for Advanced Semiconductors

As mentioned, packaging/test/qual for advanced chip designs is no longer straight-forward. The semiconductor part of the system isn’t just a monolithic chip. Multiple dice typically implement various advanced algorithms with dedicated designs. Add to that chiplets for communication protocols and massive 3D memory stacks on some kind of interposer and you start to see the complexity of the problem.

These devices have stringent power budgets and massive performance demands. Signal integrity, power integrity and thermal management all play an important role as well, both during design and during test and production qualification. This whole process demands a large variety of skillsets, software, and hardware.

During my time at eSilicon, we delivered several advanced designs like this. I can tell you from first-hand experience the skills, software and hardware required are massive. And the production qualification can be daunting as well, requiring the involvement of many supply chain partners who contributed to the design. Until the design successfully entered volume production, none of these companies made money.

The last mile problem occurs when organizations that do a small number of tapeouts try to assemble a team needed to get this job done. It is NOT cost-effective to assemble such an operation for small numbers of designs. It is also close to impossible to keep the best talent engaged in such an environment.

What Sarcina Technology Does

Founded in 2011 in Palo Alto, CA, Sarcina Technology offers a broad range of package, test, and qualification services. The company created the Application Specific Advanced Packaging, or ASAP category. It provides advanced package design, test, assembly and production management services with proven resources and a noteworthy 100 percent first-time silicon success track record.

Digging a bit deeper, Sarcina partners with major OSATs and foundries around the world. Its engineering and production teams are in Taiwan, where many of its manufacturing partners are located. The company also collaborates with Intel Foundry Services and maintains offices in North America and Europe in addition to Taiwan. It aims to reduce overhead and accelerate time-to-volume for its customers with a boutique, collaborative experience. Unique, one-stop wafer-in, product-out (called WIPO) services are delivered.

Sarcina’s customers include tier 1 system, network, comms and AI companies. The company offers an impressive portfolio of advanced technology and a track record in many application areas. You can learn more about these details at the Sarcina website here. To whet your appetite, here are a few examples of their work: 

AI 2.5D Silicon Interposer Package

  • 5 mm x 47.5 mm HFCBGA with 2019 BGA balls
  • 1 ASIC + 2 HBMs on a silicon interposer
  • 12 substrate layers
  • 320 Watts
  • 32 lanes of 25 Gbps SerDes
  • 16 lanes of 16 Gbps PCIe-4

Data Center High Power, Pin-Count, Performance Flip-Chip BGA Package

  • 65 mm x 65 mm HFCBGA with 4092 BGA balls
  • 1 ASIC
  • 16 substrate layers
  • 200 Watts
  • 96 lanes of 56 Gbps PAM4 SerDes
  • 384 bits of LPDDR5 at 6400 Mbps

Photonic IC Package

  • 14 mm x 18 mm SiP with 336 BGA balls
  • 1 PIC, 1 ASIC and 1 MCU
  • 10 substrate layers
  • 4 lanes of 56 Gbps PAM4 SerDes

Bio-Compatible Medical Package

  • 5 mm x 81.5 mm with 392/784 leads
  • 2-4 substrate layers
  • Bio-compatible dielectric material
  • Bio-compatible plated gold as electrodes
  • Small electrode openings to hold molecules
  • Tight opening tolerance for accurate test

How Sarcina Does It

Successfully delivering such a wide range of services begins with talent and experience. Thanks to the varied technology challenges and high velocity of workflow at Sarcina, the best-of-the-best finds a rewarding career there. Achieving such stellar results goes beyond raw talent, however.

Sarcina also has access to best-in-class tools for package/PCB design and porting, as well as 2.5 and 3D modeling and simulation. For 2.5D silicon interposer packaging, interposer design, O/S test pattern insertion, fab, and interposer wafer sort are provided. In addition,

package substrate design, power and signal integrity analysis, thermal simulation, and substrate fabrication are provided. ASIC wafer sort, assembly, final test, and production services are also part of the package.

For 3D applications, SiP (system-in-package) and WLP (wafer level package) are part of the offering, as is 3D X-ray technology to prevent wire-to-wire shorts. Sarcina also offers experience with chiplets. The company has MCM/chiplet packages in production. Stringent power integrity/signal integrity channel simulation maximizes device yield and rigorous DFM drives high assembly yield. Integrated testing services make chiplets “single-die simple”.

Support for photonic IC packaging is also provided to increase digital network transmission speed and bandwidth. Integrating the photonic IC with optical fiber delivers energy efficiency and lowers cost. The company also has experience in automotive and space grade packaging to survive stretched temperature ranges, operate under harsh environmental conditions, and pass stringent qualification standards.

In the analysis area, power integrity channel simulation analyzes the entire channel: chip-package-PCB-VRM to assure power supply minimum voltage meets spec at die bump. Signal integrity channel simulation ensures a quality eye diagram, supporting state-of-the-art advanced high speed I/O protocols. The company has production-proven results for LPDDR5, 56G SerDes and PCIe-5. Thermal simulation is also performed at the system level to accurately predict silicon junction temperatures.

And extensive wafer sort and final test hardware services are provided. ATE platforms include 93K, UltraFlex, J750EX, and Catalyst.

What’s Next?

The challenges discussed here are substantial. An organization with experience and track record across all these areas can provide the margin of victory. It’s good to know Sarcina Technology has already built the team, infrastructure, and track record that so many design teams need. Drop them an email at sales@sarcina-tech.com to find out how they can complement your team on your next project.  And that’s how Sarcina Technology makes advanced semiconductor package design easier.