SemiWiki – Page 683 – The Open Forum for Semiconductor Professionals

January 1, 2016July 18, 2025

How Not To Be Incoherent

How Not To Be Incoherent
by Bernard Murphy on 01-01-2016 at 7:00 am
Categories: Arm, IP, Synopsys

The advantage of working with cache memory is the great boost in performance you can get from working with a local high-speed copy of chunks of data from main memory. The downside is that you are messing with a copy; if another processor happens to be working in a similar area, there is a danger you can get out of sync when reading and writing copies of the same main-memory addresses. That’s where cache-coherence protocols come in, to keep those copies in sync where needed, and since ARM is the de-facto supplier of cache-coherent bus-fabrics connecting their processors to cache memories and to other IPs, VIP becomes essential to verify correct usage across all the flavors of AMBA your design may contain.

The Synopsys VIP for the AMBA4 ACE and AMBA5 CHI protocols is an excellent example of why use of proven VIP is so important in testplans. You have to contend with multiple protocols, coherent and non-coherent agents and interconnect, all the possible varieties of state transitions among the agents, ordering complications and more. Since the ACE specification alone is nearly 200 pages, it would be crazy to try to recreate all the required checks and particularly all the coherency protocol checks associated with these standards. Instead you buy a proven VIP which self-configures (given some guidance) to your design and generates a testbench that will run sequences to perform all the standard-required tests, provide related checks, do coverage analysis and more. Which leaves you free to focus on how your architecture applications perform to your market objectives.

So yeah, VIP is good, etc, etc but isn’t this just another in a long line of VIP? Well not quite. Suppose just for the sake of argument that you had the time, money and interest to build this yourself (you don’t – there are no extra-credit projects in this area). Of course this would take lots of expertise and time to evolve/debug/prove what you had built. But that isn’t really so different from other VIP. What makes this domain especially challenging is the non-determinism in cache-based systems and potentially long latencies between source of errors and the ultimate effect of those errors, all made more complex in systems with coherency management. For all practical purposes, the number of types of software that can run on these systems, multiplied by the number of types of data they must process, multiplied by an unpredictable level of real-time interrupts gives you an infinite number of possible scenarios hitting caches in unpredictable sequences.

What happens if you get this even a little bit wrong? Unlike a small error in a peripheral protocol, an error in cache behavior is an error in the heart of the machine – there really are no bounds to how badly (or, worse yet, subtly) that can affect behavior. You may not even see the impact of a low level bug inside the time-windows you are testing – an error of this type can manifest quickly or can take days to bubble-up to observable misbehavior on silicon. Which means that this is an area where any level of imperfection truly is not an option.

For these reasons, cache coherence VIP must be developed by protocol experts in very close collaboration with the IP provider (ARM). It has to provide comprehensive tests and checks for all possible failure modes and it has to provide super-streamlined debug support, starting from a protocol view and drilling down to signal and logic root causes, because if it takes you too long to debug problems, you’ll run out of time before you really know the coherency interaction is really safe. That’s really why this VIP is, in an important sense, more critical than any other VIP.

You can learn more about the Synopsys AMBA VIP HERE.

mbed OS abstraction battles IoT hyperfragmentation

mbed OS abstraction battles IoT hyperfragmentation
by Don Dingee on 12-31-2015 at 12:00 pm
Categories: Arm, IoT, IP

In the days of bit banging and single-threaded loops, programming a microcontroller meant grabbing a C compiler (or even before that, an assembler) and some libraries and writing bare metal code. High performance networking and multi-tasking was usually the purview of heavier real-time operating systems (RTOS) or, if an MMU was available, embedded Linux.
Continue reading “mbed OS abstraction battles IoT hyperfragmentation”

December 31, 2015

PUF the Magic (IoT) Dragon

PUF the Magic (IoT) Dragon
by Bill Montgomery on 12-31-2015 at 7:00 am
Categories: IoT, Security

Most people are familiar with Biometrics, the measurement of unique physical characteristics, such as fingerprints, and facial features, for the purpose of verifying human identity with a high level of certainty. The iris and even a person’s electrocardiogram (ECG) can be used as a secure biometric identifier.
Continue reading “PUF the Magic (IoT) Dragon”

December 30, 2015

2016 – Intelligent Things of the Internet

2016 – Intelligent Things of the Internet
by Pranay Prakash on 12-30-2015 at 4:00 pm
Categories: IoT

Change is happening fast with the Internet of Things (IoT). Devices are getting smarter. We all know that and have seen the evolution over the last several years – from smart thermostats to toasters. But smartness is a relative term and as we enter 2016 we will see more devices/machines that are becoming intelligent. And when you’re intelligent you do things better, faster and a lot of times without the help of anyone. That is what’s happening in the intelligent devices world. In some cases humans are controlling and talking to these devices and in others devices are talking to each other.

On one of my international flights in 2015, I grabbed the chance to watch Ex Machina, a wonderfully done movie which attempts to close the gap between humans and machines. If you haven’t watched, recommend giving it a shot. The main non-human character in this movie called ‘Ava’ is a humanoid robot built with Artificial Intelligence (AI) – she is smart but also has emotions. Ava is possibly the closest a robot can get to humans from an emotional standpoint and yet do a lot more in terms of smartness and efficiency. If I were to make a grand and ambitious prediction, I would say we’re going to get to super intelligent machines like ‘Ava’ connected to blazing speed wireless internet fast but realistically, I don’t feel it is a #tech2016 phenomenon 🙂 However, I am certain we are headed in that direction and the following trends in 2016 will help in getting there:

Wireless Connectivity
Everything is getting connected. We’re seeing technologies like WiFi and Bluetooth come default on many devices for home and even in commercial applications. Then there are ZigBee, Z-Wave protocols as well being used for connectivity in smart lighting etc. It is hard to say how protocol standardization will evolve but surely in 2016 device vendors will increasingly adopt some form of wireless connectivity. As a consumer, I get disappointed if I don’t see an option for wireless connectivity these days. At the upcoming CES event in January 2016, we can expect to see an explosion of wirelessly connected consumer devices.

Wearing IoT
We will see us move from carryingIT/IoT devices to wearing IoT devices. We’re a little distant from having connectivity chips planted in our bodies 🙂 however like clothes, wearable devices will become part of our everyday living. The biggest advantage of embracing wearables is your email, app, text is always on you vs the pain of trying to find your smartphone when you misplace and need it the most. In the last couple years, there have been quite a few jewelry based IoT startups that are trying to connect your ring, necklace etc in an attempt to connect YOU. This space will be very active in 2016.

Software Driven Everything
Post connectivity, these devices need to be managed. Whether it is simple upgrade, security fix or control of connected devices, software is important. Software will manifest in multiple different ways – there are already a plethora of apps out there for simple day to day operations e.g. turning your home temperature up and down remotely. The revolution is already begun and we’re seeing software driven cars, drones, home appliances and many applications in commercial buildings and other industries.

Self-driving cars will become a ‘practical’ reality over the next few years but it will need internet connection and coherent interaction of software, machines and sub-systems. Software is also critical in the shape of IoT platforms to help develop apps, manage devices and more. In 2016, we will see new IoT software developer ecosystems evolve and there will be more interesting apps and possibly consolidation of IoT platforms as we go forward. Cloud will play a very active role as platforms evolve – Microsoft, IBM, Amazon and others are already pushing and positioning their cloud platforms for IoT.

Analytics and Algorithms
Without data analytics and algorithms connected devices will still be pretty dumb. In the journey to ‘Ava’, we will see analytics taking a center stage. The ability to process data fast, visualize information, draw conclusion, make decisions and act at lightning speed – we will need machines to do all of that if we want to evolve to an automated world. 2016 will be the year when we will see self-learning capabilities added to more machines. This is critical to the successful formation of the humanoid brain which will be always connected and unlike human brains will be made of silicon and software.

I am looking forward to an exciting#BigIdeas2016 year as IoT transforms. Let the ‘Intelligent Things of the Internet’ talk in 2016!

Also on LinkedIn

December 30, 2015

The Silicon Valley Apocalypse!

The Silicon Valley Apocalypse!
by Daniel Nenni on 12-30-2015 at 12:00 pm
Categories: General

Based on the Behavioral Sink Experiments in the 1950s it is hard for me to believe that Silicon Valley will continue with the unicorn fueled hyper expansion we are currently experiencing without some very serious repercussions, both social and financial. First let’s talk about the social issues which to me are the most interesting.

The Behavioral Sink Experiments found that populations of social animals (mice and rats) in space and resource limited environments would explode then implode into extinction as a result of social decay. The hypothesis was that nature has its limits in how social animals can thrive/survive:

Among the males the behavior disturbances ranged from sexual deviation to cannibalism and from frenetic overactivity to a pathological withdrawal from which individuals would emerge to eat, drink and move about only when other members of the community were asleep.

After being part of the Silicon Valley rat race for 30+ years I have never seen anything like the crowds we have today. We are over building and over populating way beyond what our environment can handle. The roads are the clearest sign. Back in the day you could miss traffic by leaving before 7am and coming home before 5pm. Now you have to leave before 5am and start your trip home before 3pm otherwise a 40 mile commute turns into an 80 to 120 minute stress test. Leaving at 10am and returning home at 7pm no longer works either. Traffic is now a way of life and with gas prices at record lows it is only going to get worse. Traffic accidents, which are now an everyday thing, also increase social decay.

And is there anybody in Silicon Valley that is working a 40 hour week? No, we are working even more hours per week for the same or less pay then we used to, absolutely. So you have to ask yourself, “how is this all going to end socially?”

Financially speaking we have seen two meltdowns in the past two decades: The Dot Com Bubble and the Subprime Mortgage Crisis. The only remotely positive result socially is that the divorce rate actually went down during these two periods. Partly because couples could not afford two separate households but I digress…

Clearly we did not take those two financial life lessons to heart since we are probably approaching yet another financial meltdown that can be called “The Unicorn Walking Dead” or maybe “The New Age of Unicorpses”.

Those at the top tier of the billion-dollar funding club, companies such as Airbnb Inc. and Uber Technologies Inc., will survive relatively unscathed, said Max Wolff, chief economist at Manhattan Venture Partners, but he expects a “meaningful correction” to ripple through the club. Some of today’s unicorns will keep being fancy pets and some of them will be meat, Wolff said.

By the way, out of the 130+ unicorns not one of them are ACTUAL semiconductor companies, even though without semiconductor innovation none of those unicorns would exist. Something for the unicorn breeding VCs to think about wouldn’t you say?

December 30, 2015

Lighting Up The Cloud

Lighting Up The Cloud
by Bernard Murphy on 12-30-2015 at 7:00 am
Categories: EDA, General, Intel Foundry, Silicon Photonics

In our rush to imagine a world populated with IoT devices, tech advances at the top end of this ecosystem (the cloud) don’t seem to get much airtime. But this isn’t because they are limited to modest refinements. As one example, there is active technology development in connectivity around fiber-based communications within the datacenter.

I always like to start with why changes are happing; an Intel shareholder update explains this quite well. These clouds (datacenters) are seeing three big shifts: massive growth in scale driving massively increased bandwidth demands, the same growth in in the scale of the building(s) containing the datacenter, requiring cabling reach up to 2km, and a change in traffic patterns from hierarchical enterprise flows (masters feeding/controlling slaves) to cross-system flows, emerging thanks to network function virtualization (NFV) and software-defined networking (SDN), requiring more flexible connectivity (less hierarchy).

Copper can’t keep pace with these demands, hence for some time fiber has been the preferred medium for connectivity, for all the usual reasons – low attenuation, security, material cost and more. The preferred light source is vertical-cavity surface-emitting lasers (VCSEL) operating at 850nm. But high-speed VCSELs typically have large spectral width, leading to dispersion in the fiber which limits reach to ~100m; they are also tend to higher power requirements than demanded by large datacenters.

Recent articles have suggested that silicon photonics may provide an answer. VCSELs are built in specialized devices distinct from the compute engine, but there is an intuitive appeal in building the optical link into the same chip (or package) as that engine, potentially improving performance, power and cost, also leveraging the technology and capabilities already developed for semiconductor manufacture. Intel and IBM certainly believe this. The Intel shareholder update I mentioned earlier shows silicon photonics can already meet the 2km reach requirement and is therefore able to bridge the gap between VCSEL reach and full datacenter size (I assume this would be as a result of narrower spectral width from the lasing source though Intel does not elaborate on this point). Better yet, the promise is that silicon photonics can drive 4 optical channels into one fiber, increasing capacity at no additional cost over cheaper single-mode fiber, where high performance VCSEL connections require multi-mode fiber.

So much for the promise – reality seems to be less clear. First, the silicon photonics domain appears to be as susceptible to hype as other domains; unsurprising since some companies have been investing in this area for years without serious (commercial) progress. On a brighter note, you can now buy devices (from Cisco, Mellanox and Infinera, for example) which use the technology, also the compelling needs remain, so this is hardly a failure. But silicon-based lasers still struggle with reliability (unlike VCSELs), which may be why Intel had a false-start release early in 2015, though they are now shipping production silicon. And the VCSEL folks are not standing still; research work has demonstrated the feasibility of VCSELs operating in the same range claimed for silicon photonics.

The net seems to be that VCSELs are proven today in production usage but have reach and power limitations which in principle could be overcome though not yet demonstrated outside the lab (?), whereas silicon photonics has promise but still seems to be teetering on the edge between promise and delivery. At the end of the day, this race may be decided as much by bill-of-materials and manufacturing cost as by technology, and that’s where silicon photonics should have the edge.

An article introducing the promise of silicon photonics can be found HERE. You can read the Intel shareholder update HERE. An article reviewing whether we are past the silicon photonics hype phase is HERE. A nice comparison of VCSELs versus silicon photonics can be found HERE. For an example of research in extending useful operating parameters of VCSELs, see HERE.

Tuning Analog IP for High Yield at SMIC

Tuning Analog IP for High Yield at SMIC
by Daniel Payne on 12-29-2015 at 12:00 pm
Categories: EDA, MunEDA

Analog IP is more difficult to design and optimize for a given process node compared to digital IP, so any automation for analog designers is always welcome. The engineers at SMIC in China have customers that design analog IP and often they need to know how to optimize it for a specific process, so I watched a presentation by Josh Yang, Senior Director at SMIC recently about how they do this. SMIC has six fabs in China and they serve as a foundry with process nodes ranging from 0.35um down to 28nm, with 24nm and 14nm in development. Customers of SMIC design across many market segments, like: Power management, wire-line communication, image & display, MCU, smart card, wireless, mobile computing, memory, digital home and smart everything.

SMIC customer designs may be fabricated in more than one location, so using process monitoring is important to keep the process variations within an acceptable range allowing design centering to maximize yields. Shown below are sensitivity analysis results for a process parameter called Vtlin to uncover how it correlates to other parameters:

Process monitoring is both measured in silicon and modeled prior to silicon. Models are used to predict variations in: Idsat, Ioff, BVDS, Vtlin and Isub. Sensitivity analysis is then run on these models using a software tool from MunEDA called WiCkeDto determine which process parameters effect variation the most, and even predict model parameter variations in order to debug parametric yield issues in analog IP. The WiCkeD tool has also helped SMIC engineers to debug several functional issues with analog IP, like:

40nm 10bit SAR ADC ENOB issue
40nm 2.0G low jitter PLL maximum frequency issue
0.18um 12bit ADS with missing code issues in the GSM receiver
55nm 8bit ADC with distortion issues

Voltage Reference Optimization
One SMIC customer designed a voltage reference and regulator circuit, however two of the reference voltage values had higher variation in silicon than simulated with a 3 sigma range in monte carlo, so they wanted to know if it was a circuit issue in their IP or a process issue. SMIC engineers ran worst case analysis in WiCkeD and found good correlation to silicon measurements:

VDD12 – 3 sigma minimum Vref=931.21m, 3 sigma maximum Vref=1.4681
VDD15 – 3 sigma minimum Vref=1.1664, 3 sigma maximum Vref=1.8354

The tool flow at SMIC with WiCkeD for this type of circuit analysis follows the following steps:

[LIST=1]

Sensitivity Analysis helps to find the key devices

3 sigma Worst Case Distance (WCD) analysis based on key devices to predict worst values

Yield Optimization based on the key devices

Circuit is modified based on analysis to improve silicon results

Bandgap in DAC Optimization
The accuracy of a DAC circuit depends heavily upon the bandgap voltage reference value, and one SMIC customer had a circuit where the bandgap voltage variation was 0.890 to 0.930, which is +/- 2.2% across voltage and temperature ranges. What they really wanted was a tighter voltage variation across voltage and temperature ranges. The initial analysis in WiCkeD shows regions of failure in red, and passing in green:

After going through the analysis and optimization steps using WiCkeD the new circuit layout shows an improvement on bandgap variation of 0.892 to 0.896, which is +/-0.22%across voltage and temperature ranges. Notice the improvements shown graphically in green:

Low Power Bandgap for IoT Application
The final example came from a low power bandgap used in an IoT application where they ran an automated yield optimization to meet the specification of under 500 nA of current.

Summary
Analog designers and foundries can both benefit from using new automation tools that allow analysis and optimization of analog IP blocks. MunEDAoffers the WiCkeD tool used by SMIC in their foundry business to help customers optimize their IP. To watch the SMIC presentation visit the MunEDA web site here.

Related Blogs

December 29, 2015September 1, 2024

IEDM Blogs – Part 5 – Intel and Micron 3D NAND

IEDM Blogs – Part 5 – Intel and Micron 3D NAND
by Scotten Jones on 12-29-2015 at 7:00 am
Categories: Foundries, Intel Foundry, Samsung Foundry

At IEDM Intel and Micron presented “A Floating Gate Based 3D NAND Technology With CMOS Under Array” authored by Krishna Parat and Chuck Dennison.

As I previously discussed in my blog on the IEDM memory short course and blog on IMEC’s work on high mobility 3D NAND channels, continuing to scale 2D Flash has become extremely difficult and the major Flash producers are all moving to 3D NAND.

The memory short course blog can be accessed here.
The IMEC high mobility channel for 3D NAND can be accessed here.

Samsung was the first to introduce 3D NAND with their Terabit Cell Array Transistor (TCAT) and Toshiba has been in hot pursuit with their Bit Cost Scalable (BiCS) approach. Both of these approaches plus proposed 3D NAND from SK Hynix and Macronix have all been based on a charge trap devices where a silicon nitride layer is used to trap electrons.

The basic process for these devices can be thought of in three parts:

CMOS – the fabrication of CMOS to control access to the memory array.
Memory array – deposition of the memory layers, channel, slot and stair step formation.
Interconnect – interconnect of the CMOS and memory array.

To-date the 3D NAND devices in production have been charge trap based memory cells and the CMOS has been arranged off to the sides of the memory array.

In the Intel-Micron paper the first floating gate 3D NAND cell is described as well as the first instance of the CMOS being fabricated under the memory array.

The fabrication of CMOS under the memory array follows a flow similar to CMOS off to the side but adds interconnect that will also be under the memory array. We expect a pair of tungsten interconnect layers will be required.

The memory array fabrication begins with deposition of oxide and polysilicon layers pairs. The devices described in the paper has 32 memory layers plus select transistor layers and dummy layers. After the layers are deposited the array formation proceeds as follows:

[LIST=1]

Cell hole formation.

Etch back the gate polysilicon layers to create a recess.

Interpoly dielectric formation – I believe this is ONO.

Floating gate deposition – I believe this is polysilicon.

Floating gate etch back to isolate the floating gates, basically islands of polysilicon are created in the recesses formed in step 2.

Tunnel oxide and channel formation.

Although not specifically addressed I would expect this to be followed by slit and stair step processes.

I have heard a rumor that Intel-Micron creates their stair step with far fewer masks than Samsung. The challenge of stair step formation is a that a thick photoresist layer is deposited, one film pair is etched and then the photoresist image is “shrunk” and another film pair is etched. Because the photoresist film is getting thinner with each “shrink” there is a limit to how many layer pairs can be done by each mask. I have heard Intel-Micron gets more film pairs out of each mask, possibly by etching stairs that are narrower.

Following the memory array formation, interconnect would be fabricated similar to the Samsung and Toshiba processes with the additional need to etch vias down to the CMOS under the memory array.

The Intel-Micron process trades added process complexity to put the CMOS under the memory array against die area, so how do they do?

Samsung initially entered the market with a 24 layer 2 bit/cell device; they then introduced 32 layer 2 bit per cell and 3 bit per cell devices, and recently announced a 48 layer 3 bit per cell device. So how does the Intel-Micron 32 layer 2 bit per cell and 3 bit per cell devices compare? The following table summarizes the five parts. Please note that a die size for the Samsung 48 layer devices is not yet available and the value presented is our estimate.

[TABLE] align=”center” border=”1″
|-
| style=”width: 106px; text-align: center” | Company
| style=”width: 69px; text-align: center” | 3D layers
| style=”width: 66px; text-align: center” | Bits/cell
| style=”width: 108px; text-align: center” | Capacity (Gb)
| style=”width: 96px; text-align: center” | Die size (mm2)
| style=”width: 114px; text-align: center” | Density (Gb/mm2)
|-
| style=”width: 106px; text-align: center” | Samsung
| style=”width: 69px; text-align: center” | 24
| style=”width: 66px; text-align: center” | 2
| style=”width: 108px; text-align: center” | 128
| style=”width: 96px; text-align: center” | 132.2
| style=”width: 114px; text-align: center” | 0.97
|-
| style=”width: 106px; text-align: center” | Samsung
| style=”width: 69px; text-align: center” | 32
| style=”width: 66px; text-align: center” | 2
| style=”width: 108px; text-align: center” | 88
| style=”width: 96px; text-align: center” | 87.3
| style=”width: 114px; text-align: center” | 0.98
|-
| style=”width: 106px; text-align: center” | Samsung
| style=”width: 69px; text-align: center” | 32
| style=”width: 66px; text-align: center” | 3
| style=”width: 108px; text-align: center” | 128
| style=”width: 96px; text-align: center” | 68.9
| style=”width: 114px; text-align: center” | 1.86
|-
| style=”width: 106px; text-align: center” | Samsung
| style=”width: 69px; text-align: center” | 48
| style=”width: 66px; text-align: center” | 3
| style=”width: 108px; text-align: center” | 256
| style=”width: 96px; text-align: center” | 91.9 (est)
| style=”width: 114px; text-align: center” | 2.49
|-
| style=”width: 106px; text-align: center” | Intel-Micron
| style=”width: 69px; text-align: center” | 32
| style=”width: 66px; text-align: center” | 2
| style=”width: 108px; text-align: center” | 256
| style=”width: 96px; text-align: center” | 168.5
| style=”width: 114px; text-align: center” | 1.52
|-
| style=”width: 106px; text-align: center” | Intel-Micron
| style=”width: 69px; text-align: center” | 32
| style=”width: 66px; text-align: center” | 3
| style=”width: 108px; text-align: center” | 384
| style=”width: 96px; text-align: center” | 168.5
| style=”width: 114px; text-align: center” | 2.28
|-

From the table it can be seen that the new 32 layer Intel-Micron device with the CMOS under the memory array is significantly denser than the Samsung 32 layer device. Of course as Intel-Micron are introducing their 32 layer device Samsung is introducing a 48 layer device and undoubtedly hard at work on putting the CMOS under the memory array on their devices as well.

December 28, 2015

IEDM Blogs – Part 4 – IMEC InGaAs Channel for 3D NAND

IEDM Blogs – Part 4 – IMEC InGaAs Channel for 3D NAND
by Scotten Jones on 12-28-2015 at 4:00 pm
Categories: Foundries

At IEDM IMEC presented “MOCVD In[SUB]1-x[/SUB]Ga[SUB]x[/SUB]As high mobility channel for 3-D NAND Memory” authored by E. Capogreco, J. G. Lisoni, A. Arreghini, A. Subirats, B. Kunert, W. Guo, T. Maurice, C.-L. Tan, R. Degraeve, K. De Meyer, G. Van den bosch, and J. Van Houdt.

On December 15[SUP]th[/SUP] I had the opportunity to have a conference call with Arnaud Furnemont, director of memory department, at IMEC and discuss this work.

With the well published difficulties with continuing to scale 2D NAND, all of the leading NAND Flash producers have introduced 3D NAND. Micron has even gone as far as to announce that 16nm will be their last 2D NAND generation.

For 3D NAND a stack of alternating layers is deposited, either oxide-nitride or oxide-poly and then a channel opening is etched down through the stack. Currently 32 layer devices are in production with 48 layer devices being introduced. The long term plan for 3D NAND is to continue to add layers to the stack until over a hundred layers will be in use creating 1 terabit memories. There is also the need to create slits down through the stack and a stair-step at the array edge for interconnect.

Some of the key integration challenges for 3D NAND are:

Stress in the memory stack.
Creating holes and slits through such a tall stack.
Resistance of the channel.

The work in this paper is specifically targeted at channel resistance.

In 2D NAND the memory cell channels are single crystal silicon with relatively good mobility.

For 3D NAND, once the channel opening is etched down through the memory stack, a polysilicon tube referred to as a “macaroni channel” is formed in the etch opening. As the number of memory stack layers increases, the height of the macaroni channel increases. Because polysilicon has lower mobility that single crystal silicon, the channel resistance becomes a problem as the channel height increases.

In this work a three memory layer stack was created using the Bit-Cost Scalable (BiCS) approach championed by Toshiba and San Disk (oxide-poly layers). 45nm channel openings were etched down through the layers and an InGaAs channel was then grown. The resulting channels showed a 10x improvement versus their process of record polysilicon channel.

To-date the work is based on the BiCS process. I asked about the TCAT process Samsung utilizes particularly in light of Samsung being the first to market with 3D NAND. Arnaud said that TCAT will be next. Also, the work presented at IEDM just covered the channel mobility, since the original work was completed they have demonstrated program/erase of data and saw no change in the memory cells versus the POR.

For a full implementation of this process there is still work to do:

They need to integrate a metal gate. When the memory cell is based on a nitride trap layers such as BiCS and TCAT use a metal gate is needed to create a high work function. The Micron floating gate 3D NAND I will address in a separate blog wouldn’t need a metal gate.
Currently the channel is solid and they need to create a macaroni channel.

This work is an important step in addressing the challenges of continuing to scale 3D NAND.

December 28, 2015

Big Auto Fearing IoT!!

Big Auto Fearing IoT!!
by Al Gharakhanian on 12-28-2015 at 7:00 am
Categories: Automotive, IoT

In my advisory role I routinely interact with many customers and IoT thought leaders and invariably get acquainted with their point of views. I find most of these insights unique, informative, and most interestingly unmentioned in major news outlets. My intention for posting this is to share some of these findings with you.

Yet Another IoT Wireless Proposal !!
As if having eight IoT wireless proposals was not enough, we got a new one a couple of weeks ago. The technology is named Starfishand has been developed by Silver Spring. They announced the initial rollouts to take place in 7 cites in US, Europe, and India. Silver Spring is the leading manufacturer of “Smart Grid” connectivity equipment mostly sold to electric and gas utility companies worldwide. Starfish is a IPv6 mesh-based technology built on the Wi-SUN interoperability standard of IEEE 802.15.4g and allegedly can deliver 1.2 Mbps speeds, 10ms latency and up to 50 miles point-to-point range. While in-depth and meaningful information about Starfish is scant, the following are a few notable characteristics:

[LIST=1]

Like SigFox and LoRa, Starfish is based on sub-GHz ISM band

Similar to SigFox, Silver Spring intends to be a service provider and not just an equipment company (yet another example of a traditional hardware company vying for a recurring subscription business model)

The initial rollout of this public network will be based on their legacy-installed base (nearly 25M nodes). It is unclear how a public network can be deployed using equipment owned by third parties

No cost or power consumption information is available and the existing implementation is based on a Systems-on-Chip (SoC) developed by Silver Spring bolted to an off -the-shelf radio chip

So why is there so much interest to gain a foothold on an IoT Wireless technology? The rationale is pretty simple. Consider billions or even trillion of dollars that has been spent by wireless operators to build a worldwide cellular infrastructure. Such a massive investment has been well justified since eventually every world citizen able to use and afford a mobile phone will have one. Now imagine a world that each person that has one mobile handset is surrounded by dozens of “smart things” that need to communicate with each other. This presents an enormous business opportunity for the carriers both in terms of subscription fees as well as valuable data collected. Promoters of winning connectivity technology for IoT will enjoy a tremendous tail wind when it comes to monetizing the IoT build out.

Nuances in Home Automation Gadgets
Most people envision connected thermostats, smoke detectors, and smart lighting when they hear the term “Home Automation”. We have come a long way and Home Automation (HA) devices are covering a much wider territory. This category now encompasses home security, music distribution, IoT, and Remote Health Monitoring in addition to temperature and lighting control. The advent of flexible voice-driven HA hubs such as Amazon’s Echo has eased the task of controlling wares around the house using voice commands.

Reviewing the nuances of the upcoming CES show in Las Vegas, the following conclusions can be drawn:

[LIST=1]

The sheer number of connectivity protocols is mind bugling. We now have DECT, ULE, ZigBee, Z-Wave, Thread, Weave, AllSeen, OIC, Insteon, EnOcean, WiFi, and BLE Mesh. BLE (Bluetooth low energy) Mesh is the latest entrant to the HA arena. This is essentially enhanced Low Energy Bluetooth (BTLE) in order to extend its reach and up its data rate

There is now a new product category added to the HA mix. The category consists of detectors and sensors for home use that are able to perform Audio & Video Analytics. Such wireless sensors contain a camera and/or a microphone and can capture and analyze images and relay their findings to the control Hub. As an example, they are able to detect motion, recognize faces, and detect fire and smoke. On the audio side, the devices are able to analyze the captured sounds and identify a cry for help or slurred speech of elderly suggesting a stroke

There is a trend to build devices that have multiple functionalities. One notable example is a new product from MYXYTY that is essentially a floor-standing 360-degree Bluetooth speaker but it also integrates LED lighting, camera, microphone, pico-projector, and even a perfume diffuser.

On the service side, there are an increasing number of companies such as iControl, and Zonoff that are capitalizing on the complexities involved in product selection, installation, and the management of all these new gadget. Their value proposition is to handle A-Z of the home automation issues of homes and offices

Big Auto Fearing IoT !!
Alphabet and Apple are aggressively pressing carmakers to install variations of their operating systems in the car entertainment systems (head units) for many good reasons. This obviously has many benefits for the consumer in the form of added connectivity, device integration, and a slew of innovative services. The parties that gain the most from this trend are the ones that own the operating system. Alphabets and Apples of the world are essentially able to extend their footprint into millions of vehicles. They are able to collect tons of valuable user data and a can now establish a new eCommerce front not to mention pushing targeted advertisement to the drivers and passengers.

Major automakers view this as a loss of valuable territory. They don’t want to end up like Samsung that pays a heavy price in profit margins just because they don’t have control over the mobile OS. German behemoths are particularly worried about this loss of control since they employ one out of seven worker in Germany and they have not been particularly successful in developing a homegrown operating system.

Happy Holidays & Peace on Earth
Al Gharakhanian

We at Upsideclosely track the developments in the emerging field of Internet of Things (IoT). Our mission is to discern facts from fiction. We are committed in helping our clients make the optimal product planning and strategic decisions