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Drift is a Bad Thing for SPICE Circuit Simulators

Drift is a Bad Thing for SPICE Circuit Simulators
by Daniel Payne on 10-07-2016 at 12:00 pm
Categories: EDA, Synopsys

My first job out of college was with Intel, located in Aloha, Oregon and I did circuit simulations using a proprietary SPICE circuit simulator called ASPEC that was maintained in-house. While doing some circuit simulations one day I noticed that an internal node in one of my circuits was gradually getting higher and higher, even exceeding the value of VDD. What in the world could be causing this, the voltage cannot climb higher than VDD, I thought. Finding a senior engineer Clair Webb, I showed him the plot and asked, “What did I do wrong?”

His reply, “Oh, your circuit is OK, it’s the circuit simulator that has a bug. Go file a bug report.” Wow, I was stunned, because I presumed that in the commercial world there were no software bugs and that the SPICE answers were always to be trusted. Have times changed that much with circuit simulators producing the wrong results?

If you’re doing signal and power integrity designs then there are extracted interconnect netlists that are part of your circuit, and it’s possible that you can see DC drift on signals during transient analysis. The HSPICE team over at Synopsys has anticipated that you might experience this drift issue, so they’ve created a 15 minute Webisode titled, “Drift-free Transient Simulation for Signal and Power Integrity Analysis – Using deCap-aware Rational Functions.”

The R&D engineer at Synopsys explaining how to best use HSPICE in this webisode is Ted Mido. He talks about a new feature in HSPICE on scattering parameter handling that will make sure that your transient circuit simulations are drift-free. The example circuit used is an 8 GBps differential PRBS simulation. You can even get this complete demo case at no cost by requesting it.

The online signup is here and taking up just a quarter of an hour learning more about HSPICE will certainly save you from getting the wrong analysis results for SI and PI simulations. Mido-san talks about topics like:

  • Small extracted capacitances in the range of nF and pF for transient results at GHz speeds
  • Larger extracted capacitance for decoupling capacitors in packaging with capacitance values in the mF range for transient results in KHz speeds
  • S-parameters with a very wide range of values
  • How convolution is used when starting from S-parameters and going to transient analysis
  • Inverse FFT or rational function modeling for approximation
  • Recursive convolution
  • Computation effort versus run times
  • Separate sets of S-parameters for packaging and chip interconnect
  • HSPICE automatically detecting and separating S-parameters for coupling decap and chip interconnects
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Climbing the dimensions (part 1)

Climbing the dimensions (part 1)
by Claudio Avi Chami on 10-07-2016 at 7:00 am
Categories: General

Translated and adapted from an article by Jaime Poniachik
The novel Flatland was written en 1884 by Edwin A. Abbot. This novel describes a fantastic, two-dimensional, flat world. Hence the name of the novel. This world has living beings. They have only two dimensions and they move in a plane which they cannot abandon.

It is not difficult to imagine a bi-dimensional reality. An amoeba, for example, laid on a flat surface is essentially living on a two- dimensions reality. It will explore and get food moving its pseudopods up and down, left and right, but not above or below its “body”.

In the same way that there is a three-dimensional world (ours), and the amoebas two-dimensional world, we can try to imagine how a four-dimensional world would be. Please note that we are talking about a four dimensional spatial world. Time is commonly regarded as an additional dimension, but it is not spatial (and we cannot easily move on it back and forth).

The Mystery of the Yellow Room
In “The Mystery of the Yellow Room”, suspense master Mr. Gaston Leroux (author of “The Phantom of the Opera”), proposes the following enigma: A woman that has been attacked nearly to death, is found in a locked room. A similar case is proposed by Edgar A. Poe in his story, “The Murders in the Rue Morgue”. In both cases, the authors finally give the reader a plausible explanation of how the crimes were executed inside rooms apparently locked from the inside.

A three-dimensional being could execute the perfect crime in a bi-dimensional world. A crime that even Leroux or Poe would not be able to explain.

In a bi-dimensional world, a locked room could be, for example, a rectangle. No creature from this bi-dimensional world would be able to enter the locked room, unless it forced its doors or opened a hole in its walls (the rectangle perimeter).

But a three-dimensional assassin could easily enter the locked room from the third dimension, commit the crime and abandon the locked room, leaving no trails behind.

In the same way, a criminal from a four dimensional reality could easily enter a perfectly locked three-dimensional room without touching its walls, its ceiling or its floor. It almost makes you look behind your back in awe.

A peek into hyperspace
What is the aspect of a four-dimensional object? We will try to imagine an hypercube, a cube of four dimensions.

To try (somehow) to imagine the hypercube we will explore its analog bodies on lesser dimensions.
Let’s start by the square. The square is a figure. It is flat, it has only two dimensions. It can be built using one-dimensional elements. Let’s say that we take a pair of segments. Then we connect their vertices using another pair of equal length segments. Using one-dimensional elements (the segments) we have built a two-dimensional figure, the square. This can be seen in figure 1.


Figure 1 – A square, a 2-D figure built using 1-D segments

We can also imagine that the square “connects” between two 1-D universes, the upper segment and the lower segment.

Now let’s climb to the third dimension. A cube can be built in a similar way as we built the square. This time we draw a square in one plane, and then another square in a parallel plane. If we connect each one of the vertices of the top square with the bottom square, we get a cube, as shown in figure 2.


Figure 2 – A cube, a 3-D body built connecting 2-D squares

Now let’s imagine we have a cube floating in space. We have another cube floating on another three-dimensional space. If we connect all eight vertices from one cube with those of the other cube, we have built an hypercube.

Representing such a beast is a little more complicate than telling how to build it. A possible representation (in two dimensions!) of an hypercube is shown on figure 3. If we were able to see four dimensions, we would see that all its edges are ortogonal by pairs, as they are in the square and in the cube.


Figure 3

– An hypercube (tesseract), a 4-D body built connecting 3-D cubes


Counting the elements

A square has a single face, four vertices and four edges
We climb another dimension to 3-D. There we find that the cube has six faces, eight vertices and twelve edges.
When we climb to the fourth dimension, we find that the tesseract has sixteen vertices.
On the following table we can see elements for each figure or body, starting from the first dimension and climbing into the fourth dimension:

Vertices Edges Faces Bodies
Point 1 – – –
Segment 2 1 – –
Square 4 2 1 –
Cube 8 12 6 1
Tesseract 16 32 24 8

The quantity of vertices for each figure follows a simple rule, it is 2 to the power of the dimension. But the formula for the quantity of edges, faces, etc. are a bit more complicated.

Also read: Climbing the dimensions (part 2)

My blog: FPGA Site

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Takata’s Deepest Betrayal

Takata’s Deepest Betrayal
by Roger C. Lanctot on 10-06-2016 at 4:00 pm
Categories: Automotive

There’s been a lot of betrayal in the automotive industry over the past few years. Consumers have been betrayed by car makers that failed to identify, report or anticipate problems or that deliberately misled their customers. But no betrayal was deeper than that of Takata and the ongoing airbag recall effort. And Takata’s primary victim was Honda.

Approximately 34M vehicles from more than 30 brands (and another 7M worldwide) have been identified as being subject to the Takata recall in the U.S., related to airbags that can explode and expel shrapnel capable of injuring or killing drivers. It is nearly impossible to identify a car brand untouched by the recall other than Volvo, which dodged this recall bullet thanks to its relationship with Takata competitor Autoliv. Even Swedish neighbor Saab fell victim to the recall, most likely due to its partial and then full ownership by GM prior to its ultimate bankruptcy.

But no brand has suffered a more severe blow than American Honda Motors. But the blow was as much psychic as it was financial and logistical, for Honda has long prided itself on its research acumen and its unique supplier relationships.

Having just finished reading “The Honda Way” by Jeffrey Rothfeder the prospect of Honda being blind-sided so miserably by a supplier, even such an important one as Takata, is almost unthinkable. Rothfeder details Honda’s extensive onboarding and vetting process for new suppliers – and the steady engagement with those suppliers to improve processes and reduce costs throughout the life of the relationship.

Honda is known to embed engineers at manufacturing facilities for its suppliers, according to Rothfeder, and the company isn’t above diving into the financial records of its suppliers to better identify and root out inefficiencies. These close ties have proven to be beneficial to both Honda and its suppliers. As trust and cooperation flower between Honda and its supply chain partners both organizations generally flourish.

Other car makers have equally strong ties to Takata. GM has been known to direct smaller Tier 2 suppliers to engage with Takata, making Takata something of an agent for GM. But no car maker snuggles up to its partners, like Takata, in as intimate a fashion as Honda.

So it is painful that Honda stands as the leading victim of the Takata recall with 10.7M Honda and Acura vehicles affected, nearly one third of the total for all brands. Rothfeder’s “The Honda Way” was completed and published before the Takata recall crisis unfolded, so Rothfeder is forced to cover the event in an Afterword.

He writes, in part: “Honda has a rigid program of monitoring supplier activities closely and demanding annual improvements in quality and output. This policy has been in place for decades and results in a somewhat unorthodox relationship between Honda and its suppliers, one in which Honda essentially molds the companies that it buys parts and components from in its image, fusing its culture and operational practices with the suppliers’ to produce real collaboration.

“This approach was undone in Takata’s case for two reasons: Takata had an excellent perceived safety record throughout the auto industry, and Takata’s products were viewed as too proprietary and complex – unlike other parts, like electrical components, headlamps, engine components, and so on – for the automaker to diagnose potential problems. In taking this stance, Honda essentially gave Takata a free pass that few of its other suppliers enjoyed.”

The result for Honda is equivalent to the impact of the Tohoku earthquake and tsunami of 2011 which interrupted production for Honda and other car makers and suppliers. Honda recovered from the earthquake and tsunami – closely collaborating with suppliers to ensure they retained their personnel and operational readiness during the downtime in order to be prepared when production roared back to life.

The recall tsunami has brought with it a similarly forthright response. The difference is that recovery in this instance is heavily dependent on Honda’s dealer network. More than any other car maker, Honda and its dealers have embraced the challenge to track down affected cars to complete the recall work.
I have seen the outreach efforts by Honda dealers first hand. My mother recently sold her 2003 Honda Civic. She described the multiple calls she received from her Honda dealer trying to get the vehicle in to do the recall repair. Honda dealers generally have embraced the effort to round up customers and pull them in for recall work – with one dealer in particular standing out – Kuni Honda in Colorado – which instituted an aggressive program of early morning and after hours recall work on behalf of their customers.

Even the efforts of the most determined dealer networks, such as Honda’s, face serious headwinds in trying to get potentially dangerous airbags off the roads. Consumers either can’t be bothered, or don’t take the matter seriously enough.

The Takata recall experience has taught the industry that the responsibility for customer and vehicle engagement by car makers and their dealers extends well beyond the point of sale. It has also taught us all that there is no free pass and that supplier relationships are forever, or at least for as long as the vehicle remains operational.

Takata betrayed an industry with its dangerous airbags. But no car maker felt that betrayal more directly and deeply than Honda.

Roger C. Lanctot is Associate Director in the Global Automotive Practice at Strategy Analytics. More details about Strategy Analytics can be found here: https://www.strategyanalytics.com/access-services/automotive#.VuGdXfkrKUk

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Smarter Cities and The Internet of Things

Smarter Cities and The Internet of Things
by Bill McCabe on 10-06-2016 at 12:00 pm
Categories: IoT

Parking meters, information signs, CCTV, traffic signals – almost everywhere that you look in a modern city, there’s a microchip embedded device, connecting to what has now become known as the all-encompassing Internet of Things. Although we often overlook the fact, cities are, in essence, huge and complex businesses. Cities compete for residents, investors, tourists, and even funding from central government. For cities to remain relevant, they have to become smarter, leaner, and more connected. The IoT is helping the world’s largest cities to do this, and it’s all happening on a grand scale, and at a phenomenal rate.

According to Gartner Research, in this year alone, 5.5 million new ‘things’ are expected to become connected every day. From consumer devices like smartphones and fitness devices, to interactive flat panel displays and information kiosks, IoT is seeing huge adoption rates and staggering investment. Just over a year ago, an IDC FutureScape report predicted that local government bodies would represent up to a quarter of all government spending, specifically because of investment into the research and implementation of connected technologies.

Simple Ideas are Changing How Cities are Run
Looking at just a few of the innovative technologies from the last five years, it is possible to start developing a picture of what smart cities will look like within the next decade. Bitlock is an innovative technology that uses proximity keys to automatically activate or deactivate bike locks. At the same time, the system uses an owner’s smartphone to record the GPS location of the lock and bike. Such a system could be utilized on a large scale, such as in a bike sharing program in heavily congested cities. Private and government organizations could track bikes for better management, and they could even use the uploaded data to provide real time updates for bike availability, while also recording patterns of utilization.

Streetline is another smart city technology that shows great promise. Using networked parking sensors, Streetline can record parking availability in real time, and report to city officials and publicly available smartphone apps, simultaneously. The technology is in widespread use around Los Angeles, and as of May this year, over 490 million individual parking events had been recorded and reported using Streetline sensors. Studies have shown that smart parking systems can reduce peak parking congestion by up to 22%, and can reduce total traffic volume by 8%. With other technologies like IBM’s Intelligent Transportation Solutions, local governments could utilize devices to gather real time aggregated data which can be used to measure traffic volume, speed, and other metrics, which could be used to design better policy and city planning.

Opportunities for IoT Skilled Professionals
Innovative technologies like these are just the beginning of what is possible in a smart city. Emerging technologies have the potential to make major cities more functional and convenient for residents and visitors, and more manageable for government bodies. Even so, there are still challenges to overcome. Infrastructure is a major challenge, and cities will need to plan and implement high speed networks, as well as the servers that are necessary to support their sensors and other systems. Storage and processing needs will increase as IoT becomes more widespread, and security will need to become a major area of focus. Security is not just necessary to safeguard systems, but also to protect end user privacy and data.

It’s clear that smart technologies and IoT are the future of the world’s major cities. Which in turn means that experienced developers, operations professionals, engineers, and IT security specialists will be in high demand, with growing opportunities in the immediate future, and in the coming years.

For more information please check out our new website www.internetofthingsrecruiting.com

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Processors, Processors, Processors Everywhere

Processors, Processors, Processors Everywhere
by Tom Simon on 10-06-2016 at 7:00 am
Categories: Arm, Automotive, EDA, Events, Intel Foundry, IoT

At first glance a processor conference might seem a bit arcane, however we live in an era where processors are ubiquitous. There is hardly any aspect of our lives that they do not touch in some way. Last week at the Linley Processor Conference the topics included deep learning, autonomous driving, energy, manufacturing, smart cities, commerce and more. The conference was led off by a keynote from the conference’s namesake Linley Gwennap, who touched on all the main themes for the following two days.

The keynote presented many familiar topics and ideas, along with several surprising ones. Let me summarize the most interesting points.

Linley observed that increasing wafer costs have reached the point where the price per transistor is actually going up. 20nm was the crossover point for this. As Linley puts it – “Moore’s Law is only for the rich.” The effect of this will be that cost sensitive products will stay at 28nm. Thus mainstream products will be limited in the amount of integration they contain. However, high end products will continue to move to new advanced nodes because the justification for higher prices exists.

During the era of declining transistor costs, processors were in a race that demanded a new release every two years, which starved necessary architecture changes. We saw a continuous stream of general purpose processors as a result. This is likely to change. Specialized architectures can offer a 10 or even 100 times improvement in performance-per-watt metrics. We see numerous examples of this from companies such as Tensilica, or Microsoft with their “Catapult” project which combines an FPGA with a general-purpose processor. The other trend that this will drive is the addition of more specialized processing in accelerators to offload CPU’s.

Vision processing has become a very active area because it has widespread applications. Vision processing is being used in gaming, mobile devices, industrial applications and advanced automotive. Vision Processing Units (VPU’s) which serve this market are available from Cadence, Ceva, Synopsys, and VeriSilicon. Large verticals such as NXP and Intel are entering this market through acquisitions.

Neural networks are also changing the processor landscape. Neural network training requires massive data bandwidth and high precision floating point processing. Whereas, the recognition process needs highly parallel but smaller data size processing. Many players are active in this market. Google has developed a special purpose ASIC for TensorFlow. There is also Wave Computing, Intel with its acquisition of Nervana Systems, as well as IBM and others.

Linley pointed out that data center growth has been very good for Intel. This market has grown by 11%. Interestingly the public cloud which includes Amazon Google and Alibaba is the fastest growing segment. Intel’s Xeon E5 has become the mainstream processor for 2S systems. This is now using the 14nm Broadwell-EP. Also there is the Xeon D which offers a single socket SOC with up to 16 Broadwell cores. Avoton initially targeted low-cost micro servers with its eight Atom cores. However, the interest in micro servers has diminished leaving Avoton to target the embedded market.

At the same time Intel is seeing challengers for Xeon. IBM has its Open Power initiative, which is bearing fruit with the several Power8 processors already available in servers. And in 2017 we can expect to see Power9 based servers. Also AMD is moving forward with a new Zen CPU.

There is also a bevy of activity in ARM based alternatives to the x86 architecture. AppliedMicro is seeking advantage with X-Gene 1 and 2. Cavium is focusing on high throughput with their upcoming ThunderX. QUALCOMM and Broadcom could also deploy new ARM server processors in 2017.

ARMv8 processors are moving into the embedded space. For instance, AppliedMicro and Cavium both offer embedded versions of their multicore ARMv8 server processors. QUALCOMM is likely to do the same on designs using over 24 ARMv8 CPU cores. NXP is now sampling QorIQ LS2 with up to eight Cortex-A72 cores. And the Broadcom StrataGX line moves to Cortex A57.

The usual distinction between server processors and embedded SOC’s is beginning to blur. Some Intel processors are suitable for both server and networking designs. Activities such as network function virtualization are starting to use server infrastructure. What were previously network processors are starting to look like multicore embedded processors where we see SMP Linux and GNU tools. This means that some of these network processors come with vastly improved development environments. The winning future network architecture is in flux.

One of the big stories from this conference was how network function virtualization is moving from the core to the edge. This is enabled by new development tools and changing hardware. We are seeing intelligent network adapters that include processors or FPGA’s that offer a wide range of programmability. This makes it possible to offload a large number of tasks. In some cases, virtual switch functions are running in virtualized servers on the NIC. This will do a lot to improve performance inefficiency.

Linley feels pretty strongly that the real market for IOT is business. There is high motivation in business for the improvements that IOT can bring. Anywhere there is cost savings there is a reason to innovate. IOT offers a compelling business case because of the many ways that it can improve process efficiency, conserve resources, improve security and grow markets. We can already see it being used in smart meters, parking, lighting, energy, vending machines and more.

The consumer and home market will certainly grow as well, especially as this technology gains momentum. Consumers are motivated by convenience, time savings, security, as well as status and social engagement. However, the direct economic benefits it brings are smaller and less tangible.

Processors will play a central role in making IoT data secure, which is an essential prerequisite for market growth. Linley emphasized that IoT data needs to be secure during transmission. With the ease of interception of wireless data, it needs to be encrypted. Stored data at rest in the cloud is also potentially vulnerable. Cloud service providers need to take precautions. IoT sensor and edge devices are vulnerable to hacking because they are difficult to physically secure. This is where secure boot comes into play. Also secure on-chip storage for crypto keys is necessary. Lastly, there needs to be a way to authenticate incoming commands.

Next he spoke about how cars are now built containing dozens of processors. Microcontrollers are used for things like windows, wipers etc. Then there are the processors used for in-dash electronics. Applications include navigation, user interface as well as digital dashboards and the surround view video. Pile on top of this the processing needs for ADAS, and we can easily see why automotive is a huge and growing market for processors. Linley sees this market at $10 billion annually and growing. In fact, he is suggesting that it could double by 2025.

For a moment let’s look at the requirements for ADAS. The players in this market are names from the smartphone processor market. Nvidia, NXP and TI are all recognizable with Tegra, i.MX and OMAP, respectively. Though, most of these need a vision processing engine to boost performance in the ADAS application. This is where Neural Networks come into play. For recognition massively parallel 8-bit operations are needed. For ADAS there is also a sensor fusion processing requirement of the highest order. Radar, Lidar, ultrasonic, infrared and optical all need to be combined to create the internal 3D virtual world the ADAS system will use to make effective and safe operational decisions.

Already Tesla, Volvo and others offer driver assist, which in many cases does an impressive job. These systems require driver supervision, but greatly aid in reducing driver workload. The first wave of autonomous vehicles could hit the market in 2018. At the very least they will be built with the processing power, but may lack the final software. Ford recently announced that it plans to produce a fully autonomous vehicle with no steering wheel in 2021.

While these systems may add $5,000 or more to the BOM for a car, businesses like Uber or Lyft would stand to see huge net savings if they can eliminate the cost of drivers. I know this all seems like science fiction, but we are poised on a dramatic precipice. My own thought on the rapid progress in autonomous vehicles is that it stems from the exceptionally heavy traffic found in Silicon Valley. Nowhere else will you find the motivation and the talent together to accomplish such a difficult task.

After Linley’s keynote there were two days of detailed presentations on a wide range of topics, including those above. For more information about this and other Linley conferences follow this link.

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Of distant dreams and violent delights

Of distant dreams and violent delights
by Don Dingee on 10-05-2016 at 4:00 pm
Categories: Mobile

Another report today of a Samsung Galaxy Note 7 catching fire, this time an allegedly refurbished unit, takes us back to the turning point in Samsung mobile phone history. It’s not the first time a defective Samsung phone – or a pile of thousands of them – has been on fire.

Samsung Chairman Lee Kun-Hee issued a powerful edict to his mobile phone team in 1993: “Produce mobile phones comparable to Motorola’s by 1994 or Samsung will disengage itself from the mobile phone business.” Samsung engineers had been struggling with a multipath problem and inferior signal quality, and set out to completely redesign their SH-700 phone and its SH-770 successor. Quality is a combination of design and manufacturing efforts, however. From “Mobile Unleashed”, p. 139:

What most consumers didn’t see, but Samsung employees felt, was the real quality story. Individual phone screening at the factory reduced problems before shipment, but a massive bone pile of dead phones developed. Lee sent some of the first SH-770s as holiday gifts, getting back reports of some of them not working. Embarrassed by quality escapees, he investigated further – and discovered the bone pile.

In March 1995, Lee visited the Gumi facility where the SH-770 was manufactured. Two thousand employees were invited to a rally in the courtyard, complete with “Quality First” headbands for all. Under a “Quality is My Pride” banner was the bone pile with phones and fax machines from the plant – some say numbering 150,000 units. A handful of workers smashed the defective devices with hammers, threw them into a bonfire, and bulldozed the ashes. Many of those who saw the spectacle wept openly. It was a lesson never forgotten.

I should know better by now: never say never.

A robot with a nervous breakdown, from HBO’s Westworld

There is no such thing as “good” quality, or “poor” quality. Quality exists, or it is absent, and the judge is the end user, not the manufacturer. We take the existence of quality in electronics for granted these days, after decades of advances in semiconductor, printed circuit board, and packaging and assembly technology. The era where electronic hardware used to fail dramatically mostly succumbed to reliability science years ago.

Failures today are far usually subtler. Software types invented the phrase, “It’s not a bug; it’s a feature.” Fixes are often quietly executed by reloading a new version of code, or perhaps walking back a change gone haywire. Devices magically get well, or at least quit misbehaving to the point where we don’t notice.

Phones catching on fire are hard to not notice. How Samsung has managed to produce a device, and follow up with a hardware fix, and still not solve the problem is absolutely baffling. Maybe there’s a Wells Fargo mentality at work here – ship phones, meet goals, worry later. I’ve found over the course of my career that idiotic behavior is almost always directly correlated to a compensation incentive lurking behind it. What looks dumb to you and me makes perfect sense to someone who has real money at stake.

Quality is a difficult, unforgiving master. Earlier this year when Huawei’s Richard Yu suggested they would pass Apple in smartphones within two to three years, and Samsung in five, many snorted. Now, that once seemingly locked door seems to be opening, inviting Huawei to execute on product and channel strategies. All those concerns about Huawei’s business ethics and intellectual property appropriation may be a distant dream.

Our violent delights – a compulsive need for mobile connectivity and content – now demand satisfaction. If Apple and Samsung can’t fill them, someone else will. There is no access to a previous configuration.

Putting on my black suit and heading back to work …

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You’re Going to Want to Attend the Cadence Photonics Summit Workshop, October 19-20

You’re Going to Want to Attend the Cadence Photonics Summit Workshop, October 19-20
by Tom Dillinger on 10-05-2016 at 12:00 pm
Categories: Cadence, EDA, Events

Photonics IC’s (PIC’s) are used to transmit and receive data through a (single-mode or multi-mode) optical fiber carrier, and provide the requisite electro-optical conversion for system integration. The architecture of the PIC spans the full characteristics of data transmission and reception:

  • light generation

Typically, an external source is used, either a separate module or combined with the PIC in a system-in-package configuration. Active research is underway to utilize silicon-based materials as an integrated light source.

  • injecting the data sequence onto the optical carrier

Optical waveguides patterned on the PIC are subjected to electrical (or potentially, thermal) stimulus to alter the characteristics of the waveguide propagation, modulating the phase or amplitude of the optical waveform. The difference in refractive index in the waveguide materials confines the light propagation.

  • splitting, multiplexing, and filtering of the optical power, to provide the target optical wave
  • coupling of the PIC optical data from the PIC to the fiber for data transmission

and, subsequently

  • coupling from the fiber to a (demux and) photo-detection structure – e.g., a photodiode – for the data receiver

Although fiber optics technology has been utilized for long distance communication for some time, new short-haul applications are emerging. Fiber-to-the-home will experience growing demand. Increasingly, data center server communications will employ fiber connectivity. The signal losses and power dissipation of traditional copper backplane technology used in rack servers are imposing limits on the available bandwidth between systems. (Advanced signal methods, such as the multi-bit encoded signal levels of PAM-4, are extending the effective data rates using the same unit interval. Yet, signal losses, and especially, signal noise impose difficult design constraints.) As a result, the market for PIC’s is forecasted to grow significantly, from $190M in 2013 to $1.3B in 2022, according to Transparency Market Research.

To date, PIC’s have been the epitome of “full custom” design. PIC designers have covered both optical structure and electronic circuit implementation and verification. These engineers work closely with fabrication suppliers, for detailed technical background on the waveguide material properties, mask making, and photolithographic capabilities. Specific photonic structures are typically added to shuttle testsites and characterized, providing a fixed IP library consisting of basic cells. (With regards to mask making, of specific concern is the discretization of the arcs that are prevalent in photonic structures, as discontinuities in the curvature result in adverse impact to propagation.)

To support the growing demand for PIC components, the current custom design methodology will need to scale – an integrated environment will be required, to support design capture, simulation, layout automation, parameter extraction, and post-layout validation. Cadence has partnered with Lumerical Solutions and PhoeniX Software to provide such a design environment, building upon the familiar Virtuoso tool suite.

The general design flow steps of this methodology are:

  • capture the optical and electronic “circuits” in the Virtuoso Schematic Editor
  • co-simulate the photonic and electronic elements with Cadence Spectre and Lumerical’s INTERCONNECT simulators
  • run circuit optimizations in the co-simulation environment
  • implement the layout in the Virtuoso Layout Suite XL, using the PhoeniX Software OptoDesigner algorithms for waveguide routing and photonic pCell generation
  • run in-design DRC using PhoeniX Software’s curvilinear DRC engine
  • extract photonic simulation parameters, re-simulate for final validation
  • generate masks, tapeout release to foundry

The architecture of the simulation tools is illustrated in the figure below.


Of specific note is that Cadence and Lumerical have developed a co-simulation solution – designers no longer have to deal with the accuracy and productivity issues of attempting to manually interface testcases between separate photonic and electronic simulators.

Referring to the Analog Design Environment box in the center of the figure, Cadence Spectre manages the overall simulation timestep. Lumerical’s INTERCONNECT simulator communicates with Spectre through an interface provided by INTERCONNECT’s dynamic link libraries, part of a Verilog-A module. The Verilog-A ports represent the electrical/optical partition interface. INTERCONNECT maintains a distinct optical simulation timebase, with appropriate interpolation to return results back to the Spectre time step.

The figures below illustrate the overall flow:

  • the Cadence schematic, combining electrical and optical components
  • the Verilog-A view, incorporating the Lumerical interface
  • the expanded optical model used by INTERCONNECT
  • simulation results, showing a ‘sweep’ of component parameters – in this case, the phase shift of the top branch of the waveguide in the optical model

(1) Cadence Virtuoso XL schematic

(2) INTERCONNECT optical model (expansion of the optical block in the parent schematic)

(3) Verilog-A view, integrating INTERCONNECT optical simulation

(4) simulation results, illustrating a parameter sweep

Note that this is indeed true co-simulation, with data exchange between simulators. (Verilog-A is not used as the optical model representation, as the semantics available are not well-suited to the unique characteristics of optical propagation.)

A key feature of INTERCONNECT is the use of compact models (an approach familiar to electronic designers), with S-parameter representations that span both time and frequency domains. These models have the specific advantage of enabling photonic structure parameterization through external variables, maintaining the underlying protection of IP designs.

Another productive feature of the co-simulation methodology is that familiar Spectre simulation capabilities are supported, enabling the designer to perform parameter sweeps and statistical analysis for optimization.

The integrated methodology flow for physical implementation involved the following steps:

  • Virtuoso Layout XL provides support for schematic-driven layout
  • PhoeniX Software’s integrated OptoDesigner provides pCell generators, specifically supporting advanced curvilinear shapes
  • co-floorplanning of electronic and photonic components (including Cadence support for SiP hybrid package designs)
  • layout-to-schematic back-annotation of waveguide parameters supports layout-accurate optical re-simulation

The PhoeniX pCells utilize PDK-like technology information from the foundry, to ensure that layout parameters are realizable (e.g., min/max waveguide bend radius).

An emphasis of this flow is the generation of compact model parameters from the PhoeniX pCells, for post-layout optical simulation. For example, the centerline of the waveguide is represented mathematically, which can subsequently be represented as an S-parameter matrix model.

Cadence is offering a two-day Photonics Summit and Workshop on October 19th and 20th, to provide an update on photonics technology, as well as hands-on experience with the new integrated PIC design methodology. The first day is the Summit, with an exceptional set of presentations from eminent speakers. The second Workshop day offers a set of hands-on experiences with the schematic capture, layout automation, and simulation tool flow.

Design engineers who will be expanding their scope of responsibilities to include photonic structures should attend this free summit and workshop. CAD and PDK technology engineers will also find the material extremely insightful. The link for registration on the Cadence Events site is here.

A link to the Cadence site that serves as the portal to photonics methodology development is here.

See you at the summit + workshop!

-chipguy

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The Unreasonable Effectiveness of Neural Nets

The Unreasonable Effectiveness of Neural Nets
by Bernard Murphy on 10-05-2016 at 7:00 am
Categories: General

In 1960, the Nobel-winning theoretical physicist Eugene Wigner published an article titled “The unreasonable effectiveness of Mathematics in the Natural Sciences”. His point was that, at least in the physical and chemical worlds, mathematics is able to describe the behavior of nature to an uncannily accurate degree, which leads to foundational debates on whether nature arises out of mathematics. Of course there are counter-views which I’ll get to later.

A similar argument was proposed recently for the surprising effectiveness of neural nets, though this time founded on physics rather than mathematics. (But if you accept that physics arises out of mathematics, perhaps it is a part of the same argument after all.)

First a quick review of how a neural net (NN) works and how effective they have become. An NN is a stacked layer of networks in which each layer is a plane of simple elements, where each element takes a small part of an input (an image, or speech or some other complex stimulus) and calculates a simple function based on that input. In image recognition for example, elements in the first plane would recognize simple characteristics like edges, each in a small segment of the image. Those are passed on to a second plane to recognize slightly more complex structures based on those edges, and so on. These systems are not programmed in a conventional sense; they must be trained to recognize objects but once sufficiently trained, they have proven able to beat humans at differentiating characteristics in images as closely related as different breeds of dog.

Deep neural nets/learning have proven to be more than an incremental refinement to existing methods – these methods radically improve accuracy and that in turn has led to an explosion in applications in image, speech and text recognition. Which naturally leads to improved applications for voice-based control, car safety and autonomous cars, medical advances and more. Sufficiently accurate voice-based control alone is likely to dramatically change the way we interact with automation, witness Amazon’s Alexa and similar systems.

An article in Fortune details the activity in this area, particularly investment activity, both internal and VC-funded. We all know about work that Google, Facebook, IBM, Microsoft and others are doing. What you may not know is that equity funding of AI startups reached $1B last quarter. Apparently VCs are now wary of any startup that doesn’t have such an angle, if only because they are losing interest in devices or software controlled through menus and clicks. Their view is that natural language (eg. speech) interfaces are now the hot direction.

So there’s definitely money to be made, but of course VCs don’t give a hoot about the fundamentals of physics, mathematics or the ontology of those domains. But debate in those areas might have something to say about how long-lived this direction could be, so let’s get back to that topic. Henry Lin at Harvard and Max Tegmark at MIT, both physicists, have proposed a reason why neural nets should be so effective and their claim is grounded in physics.

Their reasoning works like this. The physics of the universe can be modeled extremely well with low-order equations and with a small handful of relatively simple functions, much smaller certainly than the range of all possible functions. They attribute this to causal sequences in the evolution of the universe. The universe started from a completely ordered state (the big bang) but is still nowhere near an entropic death, as evidenced by structure in the cosmic microwave background (CMB), for example. This, they assert, is why we see significant structure and why we are able to explain physics with a limited set of equations and functions – evolution through causal sequences leads to relatively simple behavior, at least up to the current era.

So, they argue, the effectively hierarchical structure of recognition in deep neural nets is sufficient to recognize the complexity of systems we encounter in nature, whether the CMB or galaxies, or dog breeds or speech, because they need not model arbitrarily complex systems. The hierarchical structure of how systems evolve in nature, whether cosmological or biological, as evidenced in quite universal characteristics like symmetry and locality ensures they can be modeled with excellent accuracy by neural nets. (In fairness, I am greatly oversimplifying their argument – you can follow a link to an arXiv paper in one of the links below.)

This steers closer to philosophy than science, which doesn’t necessarily make it uninteresting to the more grounded among us, but it does open the floor to counter-arguments. In fact, there were early counters to Wigner’s position. One (interestingly from Hamming) was that humans see what they look for, another that we often find it essential to create new mathematics to fit a requirement (the simple equations and functions we construct are perhaps more to fit within our limited mental capacity than they are a characteristic of nature). The same arguments could be made about the neural net/physics connection. Still, physics (and engineering even more so) is about approximation. If, to sufficient accuracy, a simple model will work, then the deeper “reality” (whatever that might be) may be unimportant for practical applications, though still important for deeper understanding.


To wrap up, since I’m in a philosophical mood, Tegmark and others have written a paper on a concept started (I think) by Roger Penrose on the relationship between Mathematics, Matter and the Mind – a sort of Penrose triangle. A question here is whether one of these three is most fundamental or one most derived, or whether one or more is unrelated and simply an artefact of our attempt to model. Wigner’s position was that matter derives from mathematics. One of Hamming’s positions was that we create mathematics to model what we want to see – that Mind is fundamental, Mathematics derives from the Mind and perhaps our view of Matter is just our way to reduce the natural world into this framework. But for neural nets, who cares – it seems they may already have the power to model with the accuracy we need, at least for now.

The Wigner article can be found HERE, the Harvard/MIT article HERE and the Fortune article HERE. The mathematics, matter, mind paper can be found HERE.

More articles by Bernard…

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Free Copy of Mobile Unleashed: The History of ARM!

Free Copy of Mobile Unleashed: The History of ARM!
by Daniel Nenni on 10-04-2016 at 4:00 pm
Categories: Arm, IP, Mobile

As most of you know SemiWiki published a book which is a really nice history of ARM. We have received many compliments on it and we are very proud. As a thank you to all SemiWiki members I would like to offer a free electronic version of the book (PDF). You can access it via the attachment at the bottom of this wiki:

SemiWiki Book Download:Mobile Unleashed: The History of ARM

This is the origin story of technology super heroes: the creators and founders of ARM, the company that is responsible for the processors found inside 95% of the world’s mobile devices today. This is also the evolution story of how three companies – Apple, Samsung, and Qualcomm – put ARM technology in the hands of billions of people through smartphones, tablets, music players, and more.

It was anything but a straight line from idea to success for ARM. The story starts with the triumph of BBC Micro engineers Steve Furber and Sophie Wilson, who make the audacious decision to design their own microprocessor – and it works the first time. The question becomes, how to sell it? Part I follows ARM as its founders launch their own company, select a new leader, a new strategy, and find themselves partnered with Apple, TI, Nokia, and other companies just as digital technology starts to unleash mobile devices. ARM grows rapidly, even as other semiconductor firms struggle in the dot com meltdown, and establishes itself as a standard for embedded RISC processors.

Apple aficionados will find the opening of Part II of interest the moment Steve Jobs returns and changes the direction toward fulfilling consumer dreams. Samsung devotees will see how that firm evolved from its earliest days in consumer electronics and semiconductors through a philosophical shift to innovation. Qualcomm followers will learn much of their history as it plays out from satellite communications to development of a mobile phone standard and emergence as a leading fabless semiconductor company.

If ARM could be summarized in one word, it would be “collaboration.” Throughout this story, from Foreword to Epilogue, efforts to develop an ecosystem are highlighted. Familiar names such as Google, Intel, Mediatek, Microsoft, Motorola, TSMC, and others are interwoven throughout. The evolution of ARM’s first 25 years as a company wraps up with a shift to its next strategy: the Internet of Things, the ultimate connector for people and devices.

Research for this story is extensive, simplifying a complex mobile industry timeline and uncovering critical points where ARM and other companies made fateful and sometimes surprising decisions. Rare photos, summary diagrams and tables, and unique perspectives from insiders add insight to this important telling of technology history.

The forward by Sir Robin Saxby alone is worth the price of admission, not to mention the picture of Simon Segar as a young engineer when he first joined ARM… There is also a cameo by Wally Rhines from his TI days.

I truly believe you need to fully understand, as a semiconductor professional, how we got to where we are today to better understand where we are going tomorrow and that is what this book is all about. On a personal note, writing books like this is a lot like giving birth (although my wife may disagree). It was nine months of hard work but let me tell you one thing, Don Dingee made this whole process a lot easier. Don is the most dedicated, thorough, and hardworking researcher I have ever worked with, absolutely!

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"Rigid-Flex Design is Coming"

"Rigid-Flex Design is Coming"
by Tom Dillinger on 10-04-2016 at 12:00 pm
Categories: Cadence, EDA

Printed circuit boards that incorporate a combination of traditional PCB technology with flexible substrates, aka rigid-flex designs, have enabled an increasing variety of product designs, that leverage the unique physical form factor and lightweight options that rigid-flex technology offers. Yet, this technology requires unique CAD tool features and enhancements, when compared to traditional PCB design flows.

Cadence recently published a whitepaper and a corresponding site with a video demonstration that highlights the unique rigid-flex capabilities that have been incorporated into a recent release of the Allegro PCB design tool suite (Release 17.2, SPD17.2-2016). I had an opportunity to chat briefly with the author of that whitepaper, Ed Hickey, Product Engineering Director.

Ed described some of the features of this recent release, covering both design and verification requirements.

Stack-up definition for rigid-flex “zones”
The stack-up material definition is the fundamental fabrication technology description used by PCB placement, routing, and analysis tools. For rigid-flex designs, the stack-up support needs to be expanded to accommodate the various “zones” of the total design. The figure below illustrates how the traditional “rigid” FR-4 based layers, the (polyimide and copper) “flex” layers, and the transition “stiffener” zones are defined for stack-up identification.


Component placement
Component placement (and pin-attach padstack) rules are dramatically different on flex – moving a component across a rigid-flex boundary needs to automatically ensure a correct layer + padstack definition.

Routing
Signal routing on the flex layers presents very unique considerations. Ed highlighted, “The flex outline typically utilizes aggressive contours. Routing must support detailed arc definitions to the contour outline – this includes bus route(group mode) definitions. Routers need to be compliant to teardrop requirements at pins and vias, and tapering rules at trace width transitions. And, designers need editing support to be contour-aware, as well.”

The Cadence site corresponding to this whitepaper includes an illustrative demo, showing how a new signal inserted interactively leverages push-and-shove capabilities that are also fully compliant to the flex contour.

In-Design Checking
Rigid-flex technology has several unique verification requirements, enabled in Allegro PCB:

  • restrictions on component placement on the flex, relative to bend areas (“the bend line and bend radius”)
  • restrictions on multi-layer via placement on the flex
  • routes must cross perpendicularly to a flex bend line
  • signal routes on different flex layers need to be offset, to avoid a flex cross-section that is mechanically stiff (“the I-beam effect”, according to Ed)
  • unique rules are needed for vias and material dimensions in the transition zone

The Cadence Allegro release incorporates a new user-interface to create rules for rigid-flex design, as illustrated below for various layer-to-layer interfaces (including non-electrical surface and flex layers, such as the polyimide coverlay).


Rigid-flex electrical analysis requirements
“Cadence tools for electrical analysis also support the unique characteristics of rigid-flex designs.”, Ed indicated. “Specifically, there may be cross-hatched copper areas. Field-solver technology has been enhanced to provide accurate impedance modeling for non-solid geometries.”

MCAD-ECAD data interchange, manufacturing release
Ed emphasized the need for robust exchange of rigid-flex design data with mechanical CAD tools for product enclosure co-design and structural reliability analysis.

“Mechanical analysis requires accurate data on the material stackup in each zone, to evaluate the overall bend performance. The IDX standard data format is replacing the legacy IDF standard.”, Ed pointed out. “We have qualified the Allegro design export flow for rigid-flex with MCAD analysis tools.”

And, to be sure, the export of the rigid-flex design to fabricators requires exact representation. “There has been a tremendous amount of dollars and time wasted, due to issues with the lack of accuracy in design data provided to manufacturers. Cadence is committed to the new intelligent format standard for data exchange, known as IPC-2581.”

Ed summarized the emphasis that Cadence is putting into Allegro features for rigid-flex design in a succinct manner, stating, “The growth of this technology is accelerating. Traditional PCB designers should be aware that rigid-flex is coming.”

A link to the Cadence whitepaper is here.

A link to the Cadence site with additional detail (and video demo) is here.

-chipguy