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Market Trends Motivate a Shift-Left in Functional Verification

Market Trends Motivate a Shift-Left in Functional Verification
by Jean-Marie Brunet on 09-15-2016 at 4:00 pm
Categories: EDA, Siemens EDA

Today, in the context of functional verification, industry trends are based on the needs of prominent vertical markets. There is some overlap in what these markets need, but there are some use models that are very specific to each market.

We assert this because we have a lot of customers asking about emulation solutions not from the standpoint of methodology, but from the needs of their specific vertical market. These include networking, storage, mobile multimedia, and automotive.

We’re excited about the new things Veloce has to offer these customers. A primary force behind these is a shift-left in the verification flow. We provide the means for that shift-left to become a reality.

A shift-left means that a lot of things companies used to do late in the verification flow cycle they now do much earlier. It also means that hardware and software verification is done at the same time, using either a software stack or script to generate the traffic flow. This way it’s clear very early on that the hardware being implemented behaves correctly with the software being provided.

A shift-left greatly reduces the risk of designing very large systems and ICs. So this is obviously an overlapping need and advantage for all the vertical markets. In addition, we have other new solutions for these markets.

Let’s start with networking. The biggest networking companies in the world need greater capacity to emulate their designs. Their chips are very big, so they need an emulator like Veloce, which is still the only emulator that can do a billion-gate design in a single monolithic box. Our competitors need a couple of boxes connected together to do that. Further, because of Veloce’s capacity, performance, and flexible use models, it is the industry’s leading networking emulation solution.

Most networking companies validate their chips in the lab using an Ethernet tester. This involves a lot of connections and a lot of cables to make those connections. Traffic is applied to the silicon to verify that the behavior of that particular design is running at-speed and the traffic is generated and behaving correctly. But, the verification process cannot begin until silicon is available. And if there is a problem at this stage, it takes a great deal of work, time, and money to fix…if you can fix it at all.

In response to requests from networking companies, our R&D team collaborated with Ixia to create an emulator-friendly network verification solution that is fully integrated with Ixia‘s number one Ethernet tester. Rather than creating a testbench for a particular networking chip and compiling it along with the design on the emulator, we use, directly, the Ixia script. The result is a cleaner setup for verifying Ethernet traffic and a shift-left in the design cycle using a solution that puts together the two leaders in the networking verification space.

In the storage market, the trend is toward bigger die sizes. So again, there’s a need for capacity and virtualization. There’s also more and more software content on storage devices that needs to be verified. ICE is still extremely important for the storage vertical market because of all the external connections to physical memory, and so on. But they need an ICE environment that is deterministic (i.e., repeatable) so that thorough debug can be completed.

This is why we launched our Veloce Deterministic ICE App in early 2016. With Veloce Deterministic ICE we have provided something in the ICE environment that is far better than anything our competitors can do. We made the ICE environment deterministic, so you can repeat the behavior of what you are verifying and therefore fix any bugs.

For the mobile multimedia market, we see two recent trends. Power is extremely important. They want to know if the chip is using what they are predicting in terms of power, rather than finding that problem on the board, which is way too late to fix. The Veloce Power App that was launch in 2015 has been very successful as a solution to this problem, including earning an EDA industry award.

The second trend for mobile multimedia companies is the need to verify hardware within the full software context of the application. Their end customers evaluate their chips by running something like an AnTuTu Benchmark. Based on the performance and metrics report they get on that benchmark, they’ll know if their chip performed correctly. So a shift-left is called for again because mobile multimedia companies want to validate their chip, not only from a testbench perspective, but within the full software context.

Finally, another big story in 2016 is the automotive market. Mentor has been very strong in the automotive market for system and ICs, so we have a lot of customer experience and knowledge and methodology and IP in this domain, and we are now seeing how emulation fits into the total solution. For example, advanced driver assistance systems (ADAS) must adhere to specific methodology requirements to verify that the chip is ISO 26262 Compliance. This requires a lot of full-system simulation and a lot of coverage performed on the chip. And this requires the capacity and performance of emulation and a shift-left in the verification flow.

To find out how your company can benefit from a shift-left emulation flow powered by the Veloce emulation platform and Veloce Apps, check out mentor.com. A good place to start is our whitepaper focusing on the networking market, Accelerating Networking Products to Market Using Ethernet VirtuaLAB.

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GlobalFoundries Roadmap Update 2016!

GlobalFoundries Roadmap Update 2016!
by Daniel Nenni on 09-15-2016 at 11:00 am
Categories: Foundries, GlobalFoundries

I attended a lunch yesterday with GlobalFoundries CEO Sanjay Jha (formerly of Qualcomm), SVP Gregg Barltlett (Motorola/GF), and CTO Gary Patton (IBM). Having followed GF from the very beginning I can tell you without a shadow of a doubt that GF has transformed from a collection of companies (AMD, Chartered, IBM) to a fully integrated pure-play foundry.

There were a dozen other media people in attendance who will cover the bullet points presented so let me comment on the leadership aspect. Having met Sanjay, Gregg, and Gary multiple times separately, I found it very interesting to see them interact as a team.

You have to remember these gentlemen come from very different backgrounds and experiences but one thing I can tell you is that they truly worked in harmony during this event which is not always the case with other companies. In my opinion the credit goes to Sanjay as he is an exceptional leader and knows the semiconductor industry from the very top (end product) down to the very bottom (device level), absolutely.

In fact, I would put Sanjay in my current top 10 Semiconductor CEOs list with Hock Tan, Jen-Hsun Huang, MK Tsai, Morris Chang, Amit Gupta, Joe Costello, Lip-Bu Tan, Wally Rhines, and Aart de Geus.

In my opinion, under Sanjay’s leadership GF will become an industry leader versus follower. The FDX family of processes is a clear example. GF will be the only pure-play foundry to deliver leading edge processes using both FinFET and FD-SOI technology which I think is astounding. So, while the other foundries are trying to fit every design into a FinFET, GF gives us a choice between high performance and lower power and lower cost.

Okay, back to the presentation, GF is rolling out their 22FDX (FD-SOI) process and announced a 12FDX process. 22FDX is competitive with 14nm and 12FDX is targeted at 10nm FinFET processes. As we all know, FD-SOI enables lower cost and lower power chips and GF will be the only pure-play foundry with sub 28nm FD-SOI process technologies.

In regards to FinFETS, the good news is that GlobalFoundries and AMD are scheduled to start 7nm production in 2018 which means AMD could have 7nm chips a full year before Intel. The bad news is that TSMC will start 7nm production in 2017 which means other fabless companies (ARM based server chips for example) will have 7nm chips 6 months before AMD. TSMC and Intel also have the advantage of a 10nm process yield learning experience that GF and AMD do not since they skipped 10nm, so there is an additional risk of delay.

It will be interesting to see how TSMC and Samsung respond to this. The TSMC OIP Ecosystem Forum is next week so we will find out then but today I saw a new and improved GlobalFoundries (GF 2.0) and am quite impressed with their progress.

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Intel Stratix 10 MX FPGA Highlights

Intel Stratix 10 MX FPGA Highlights
by Claudio Avi Chami on 09-15-2016 at 7:00 am
Categories: FPGA, Intel Foundry

These days, FPGAs are fairly complex pieces of silicon. Being that the case, it would take several articles even to put a summary of the features embedded in high-end FPGA devices. Hence, in this article, I will concentrate in just one feature, namely, the new embedded memory blocks of the recently released Intel-Altera Stratix 10([SUP]1[/SUP]).

Even medium sized FPGAs include quite a big quantity of memory blocks. For example, Altera’s Cyclone V family includes memory blocks in the range of 1.4 to 12.2 Mbits ([SUP]2[/SUP]). These memory blocks are not concentrated in a single spot but distributed over all the FPGA silicon, to reduce routing complexity when connecting the memories to the FPGA logic blocks. These memory blocks find plenty of uses: buffers, FIFOs, filters, fast memory/cache for embedded processors, register banks, etc.

As useful as these banks are, they are light-years away, size-related, compared to today’s DDR memory banks. Well, this has changed completely with the release of Stratix 10 MX, since these devices embed DDR memory banks. Intel’s acquisition of Altera has had many consequences, one of them being the merging of technologies from both firms. The Stratix 10 MX includes Intel’s Embedded Multi-die Interconnect Bridge (EMIB) technology, to interconnect between the FPGA fabric and the DDR memory blocks.

The DDR memory blocks used on the FPGA are 3D stacked blocks, integrating high speed data channels, dubbed HMB2 – High Memory Bandwidth. The HMB2 3D memory is connected to the FPGA core through parallel channels. Each channel can provide a bandwidth of 16Gbps, multiplied by 16 channels, give a total bandwidth of 256Gbps.

Moreover, the memory is separated in up to 4 “tiles”, each one connected with its own 16 data channels. The total bandwith for four tiles is of 1Tbps. Compare this number with current BW from a DDR1600 memory bank, which is in the order of 100Gbps, or even DDR2133, which provides around 140Gbps.

Currently available Stratix devices have embedded memory banks ranging from 4 to 16 GByte. In case you were wondering, these new memories do not replace the aforementioned static memory banks. Stratix MX 10 devices have between 86 to 127 Mbit in static memory blocks.

Other advantages of the integrated memory blocks, compared to current distributed solutions ([SUP]3[/SUP]), include lower power consumption and reduction of the real estate on board, as well as a reduction in PCB interconnection complexity.

The availability of these new devices promises to change the architecture for solutions that are currently dominated by CPUs and/or GPUs, like database management, cyber security, genetic algorithms and deep machine learning. For an example regarding this last category, please refer to my article: FPGAs and Deep Machine Learning

My blog: FPGA Site

References:
Stratix 10 MX Devices Solve the Memory Bandwidth Challenge
Altera’s 3D System-in-Package Technology
Stratix 10 MX Product Overview Table

Image Source:
Stratix MX10 blocks – Intel/Altera

Notes:
(1) – Altera and Xilinx are the major players on the FPGA arena. Last year (2015) Altera was acquired by Intel.
(2) – These numbers can be increased a bit more, around 15%, by converting some of the ALM logic blocks onto memory blocks.
(3) – A typical distributed solution is based on separated CPU, FPGA and memory SODIMM cards, compared to the Stratix MX10 solution that includes CPU (ARM Cortex), FPGA, and memory on a single package.

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Organizing Data is First Step in Managing AMS Designs

Organizing Data is First Step in Managing AMS Designs
by Don Dingee on 09-14-2016 at 4:00 pm
Categories: Cliosoft, EDA

Efficient collaboration is essential to meeting tight chip design schedules. In analog and mixed signal (AMS) design, collaboration has many facets. Design tools are usually specific to roles, and handoffs are numerous, especially when moving a design to a foundry. Continue reading “Organizing Data is First Step in Managing AMS Designs”

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IOT Security – Ongoing Challenge

IOT Security – Ongoing Challenge
by Bill McCabe on 09-14-2016 at 12:00 pm
Categories: IoT, Security

It is near impossible to read or have a conversation about IoT, without security becoming a major topic. For IT professionals involved with IoT projects, security needs to be a major consideration, starting with planning and design, and continuing all the way through to deployment, implementation, and maintenance. Security is not just essential to protect the integrity of systems, but also to safeguard corporate and personal data and privacy. In many cases, the viability and acceptance of emerging IoT technologies will be largely dependent on how innovators are able to gain confidence from potential users, which means that security and privacy must be as much of a priority as innovation and functionality.

The Complex Nature of IoT
The Internet of Things is often described in simple terms, with simple networks, and logical infrastructure. In the real world, this is not always the case. Consider a smart city where traffic management uses aggregate data from a number of sensors and devices, to help track and manage traffic flow. This example could include parking sensors, vehicle counters on roads and highways, traffic cameras, and even license plate scanners. Potentially, all of these devices would use different technologies, they would collect different types of data, and most importantly, they would all connect through varying types of network infrastructure. Some systems could be wireless, while others might piggyback off of existing networks. Some state of the art networks that were implemented at the time that sensors were installed, while some could run on legacy solutions. The point is that for one main function – collecting aggregate data – there would be numerous networks, devices, sensors, and even network protocols, all in use at the same time. Implementing security on such a system means that not only must the individual devices be secure, but the networks, interconnecting devices, and servers, all need to be secured as well.

Without developing networks that are secure by design, the vulnerabilities in such a system would be too numerous and too complex to identify and patch, without significant investment in time and expertise.

Secure by Design – The Most Efficient Philosophy
Every individual device and sensor is vulnerable to attack. This is something that must be assumed from the beginning of any IoT project. Security analysts must look at each individual device, every piece of running software, every network element, all network protocols, and the servers that collect and manage data, and only then is it possible to determine the potential vulnerabilities, and the best strategy for securing the entire network. Some devices will have embedded security, whereas others might have none at all. Network architects and security professionals will need to make important decisions, such as whether they will use public or private infrastructure, which type of encryption they will apply to data streams, and they will even have to determine who has access to data, where that data is stored, and where it can be accessed from. Most systems will eventually interface with public networks, especially if those systems are consumer facing, and this means that design needs to take into account the increased vulnerability that exists when third party networks and hardware are introduced into the equation.

To put it quite simply, ensuring security by design will be a significant challenge, even on smaller projects. However, when security is done right, the rewards will be significant.

Security Benefits IoT Growth and Adoption Rates
A recent Gigya survey revealed that consumers want more robust authentication options when using sensitive software and services. When it comes to IoT, or any large interconnected network, users want the confidence that their data is secure, and without that confidence, there will be no buy-in for new technologies.

Technology companies already recognize the challenge and importance of security in the digital age, but with IoT, connected networks are being built outside of traditional industries. Healthcare, production, retail, and even entertainment, are all industries that are incorporating elements of the Internet of Things, into their operations and offerings. Companies in these industries will face technological hurdles that they’ve never had to deal with before, which is why architects, developers, and security professionals, are all going to be in high demand in the coming years.

The winning companies will be those that are able to recognize the challenges of incorporating IoT into their business models, and then proactively seek the leading talent that will help them to achieve their goals.

For More Information and Posts Check out our new website at www.internetofthingsrecruiting.com

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Mentor Functional Verification Study 2016

Mentor Functional Verification Study 2016
by Bernard Murphy on 09-14-2016 at 7:00 am
Categories: EDA, FPGA, Siemens EDA

Periodically, Mentor commissions a user/usage survey on Functional Verification, conducted by the Wilson Research Group, then they publish the results to all of us, an act of industry good-citizenship for which I think we owe them a round of thanks. Harry Foster at Mentor is breaking down the report into a series of 15 blogs. He’s also going to host a webinar on September 20[SUP]th[/SUP] at 8am Pacific to talk through the results.

REGISTER FOR THE WEBINAR

One especially interesting conclusion to come out of this survey is the rapid growth in verification investment and sophistication in methodology for FPGA-based designs. For those of us who still struggle to understand why anyone even bothers with functional verification for FPGA, this may come as a surprise. One view might be that you design, do a bit of sanity-checking, program the device and test at speed in-system, fix any problems you find then repeat, an approach generally known as “burn and churn”.

For simple designs this may still be common practice, but it no longer represents a practical methodology for the bulk of FPGA design. To understand why, look first at who is using FPGAs today. About half the dollar volume (per Gartner) is in communications. Industrial and mil/aero together take about half of what’s left and the rest is divided up between consumer, automotive and data-processing. In many of these markets, FPGA-based design dominates either because device volumes can’t justify ASIC NREs or because designs must be built to be adaptable to rapidly evolving standards.

When FPGAs carry the bulk of functionality those designs become significantly more complex. 59% have at least one embedded processor and 32% contain 2 or more embedded processors. These are programmable SoCs, not general-purpose programmable logic. A Zynq-7000 SoC (not the most complex SoC offered by Xilinx) provides a dual ARM9 MPcore, multiple DDR interfaces, USB, Gigabit Ethernet and SD/SDIO interfaces and a full range of security features. Verifying a design built around all of this, together with the software running on those cores, is every bit as complex as verifying a full-ASIC SoC.

At this complexity, it’s really irrelevant that burn and churn doesn’t cost you $$ in fab costs and fab cycle-time. There is no possible way you could ever converge on a working design through trial and error – you have to follow the same disciplined verification methodologies used for ASIC designs. This is partly a function of the intrinsic complexity of the verification task – interoperating CPUs, memory, peripherals and security, plus your own programmed logic – and partly a result of extremely limited controllability and observability in the programmed device. The debug options you have are limited to external pins and debugger access to memory and state registers, which may be OK for software debug but is definitely not OK for hardware debug.

This means that FPGA verification teams find they must debug designs as comprehensively as possible before committing to burn. The survey shows there is growing use of coverage metrics and assertions, and constrained-random simulation to help get to higher levels of coverage. And, hold onto your hats, 15-20% of projects are using formal methods, spread among property-checking and automated formal checks. Take a moment to let that sink in – a non-trivial percentage of FPGA design teams find it essential to do some level of formal-proving before they burn a design. How times have changed – for FPGA design and for formal verification.

In fact, the evidence shows that FPGA verification investment (in engineers and in advanced verification methodologies) is maturing quite rapidly, much more so that in ASIC/IC design where maturity seems to have flattened out. This isn’t to say that ASIC/IC teams are laggards; per Harry they just got to the (current) peak faster and are now having to throw more bodies at the problem as the verification task grows.

Looking at design overall, the survey measured, among other factors, demand for design engineers and for verification engineers. The Wilson study shows compound annual growth-rate (CAGR) for design engineers more or less steady at 3.6%, which Harry attributes to improvements in automation and IP reuse. But the CAGR for verification engineers is 10.4%, a much, much faster rate of growth reflecting (my conclusion) less rapid progress in automation and reuse in verification.

In the webinar, Harry will provide detailed stats for FPGA and ASIC/IC design. This should be a very useful benchmark for verification teams who want to understand how they stack up against industry norms. It’s certainly an eye-opener on how much verification methods have evolved for FPGA-based design.

REGISTER FOR THE WEBINAR

You can access Harry’s blogs HERE. As of this post he has published 7 of the series of 15. Links to additional blogs should appear under this link as they are posted.

More articles by Bernard…

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TSMC 16nm, 10nm, 7nm, and 5nm Update!

TSMC 16nm, 10nm, 7nm, and 5nm Update!
by Daniel Nenni on 09-13-2016 at 4:00 pm
Categories: Foundries, GlobalFoundries, Intel Foundry, Samsung Foundry, TSMC

Word on the street is that TSMC is on schedule with 16FFC, 10nm and 7nm, which is a very big deal for the fabless semiconductor ecosystem. As Scotten Jones has illustrated in the graphic below, for the first time in the history of the semiconductor industry a pure-play foundry (TSMC) will have the process lead over Intel. And this is not just about TSMC, this is about the fabless semiconductor ecosystem delivering 10nm chips in the first quarter of 2017 and 7nm in the first quarter of 2018, absolutely.



Also read: The 2016 Leading Edge Semiconductor Landscape

To be clear, our smartphones will be powered by the fastest silicon the semiconductor industry has to offer and that my friends is simply incredible! Super computing power at the tips of our fingers, literally.

A complete 16FFC, 10nm, and 7nm process update will be made available via the TSMC OIP Ecosystem Forumat the San Jose Convention Center on September 22[SUP]nd[/SUP] from 8am to 6:30pm and I can tell you from my conversations inside the fabless semiconductor ecosystem it will definitely be worth your time.

SemiWiki bloggers: Tom Simon, Tom Dillinger, Bernard Murphy, and myself will be there as well as more than 1,000 semiconductor professionals from around the world. If you are attending let us know as it would be a pleasure to meet you.

Just in case you missed it here is the TSMC OIP overview and agenda:

The TSMC OIP Ecosystem Forum brings together TSMC’s design ecosystem companies and our customers to share practical, tested solutions to today’s design challenges. Success stories that illustrate TSMC’s design ecosystem best practices highlight the event.

More than 90% of last year’s attendees said that, “the forum helped me better understand TSMC’s Open Innovation Platform” and that “I found it effective to hear directly from TSMC OIP member companies.”

This year’s event will prove equally valuable as you hear directly from TSMC OIP companies about how to apply their technologies to address your design challenges!


This year, the forum is a day-long conference kicking-off with trend-setting addresses and announcements from TSMC and leading IC design company executives.

The technical sessions are dedicated to30 selected technical papers from TSMC’s EDA, IP, Design Center Alliance and Value Chain Aggregator member companies. And the Ecosystem Pavilion feature up to 60 member companies showcasing their products and services.

Learn About:

Attendees will discover:

  • Emerging advanced node design challenges including 7nm, 10nm, 16FFC, 16nm FinFET+, 28nm, and ultra-low power process technologies
  • Updated design solutions for specialty technologies supporting Internet-of-Thing (IoT) applications
  • Successful, real-life applications of design technologies and IP from ecosystem members and TSMC customers
  • Ecosystem-specific TSMC reference flow implementations
  • New innovations for next generation product designs

Hear directly from ecosystem companies about their TSMC-specific design solutions.

Network with your peers and more than 1,000 industry experts and end users.

The TSMC Open Innovation Platform Ecosystem Forum is an “invitation-only” event. Please register to attend. The views expressed in the presentations made at this event are those of the speaker and are not necessarily those of TSMC.

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Apple, Google Go Home

Apple, Google Go Home
by Roger C. Lanctot on 09-13-2016 at 12:00 pm
Categories: Automotive

For some marketers the operative mantra is go big or go home. It looks like Apple and Google are both taking a harder look at the automotive industry and have decided to go home.

The media is rife with reports of Apple hemorrhaging automotive engineers while senior executives on Google’s automated driving team have been skipping off to more intriguing or lucrative or less problematic ventures. The problem: The inability to locate the high volume, high revenue pony in the pile of high cost development, regulatory redtape and loathsome liability that constitutes the automotive industry.

The first hint of trouble was Google’s decision to jump out of the car insurance business nearly as soon as it jumped in. Google Compare Auto Insurance entered the market in 2012 in the United Kingdom, an attractive market for insurers because of the existence of a single regulator for a large homogeneous marketplace.

Google followed the UK launch with a U.S. launch late last year in California, but the morass of state-by-state regulatory hurdles and slow-footed insurance partners sent Google to the exits in both the U.S. and U.K. It was clear to those involved that the slow path to a profitable and eventually dominant enterprise in the car insurance market was intolerable in the context of internal expectations of high growth and a rapid ramp.

Shift gears to self-driving cars and both Google and Apple are confronting extreme technical challenges, prying eyes, Federal and state regulatory oversight and increasing competition from incumbents. Swizzle into this cocktail of conflict an ill-defined marketplace where mobility as a service is already being adequately served by cheap ride-hailing services and increasingly driverless public transportation – and the market prospects dim rapidly.

Ford is in the midst of convincing its own investors of the volume market prospects for driverless cars as its stock swoons in the midst of its own aggressive self-driving car announcements and investments. So if you are big and taking on the self-driving car opportunity, you have everything to lose and it’s pure risk. If you are a tiny start-up – like Otto (to which Anthony Lewandowski decamped from the Google self-driving car team) or Cruise Automation, it’s all opportunity and upside.

Google and Apple are not prepared to suffer the blowback in the manner of Tesla Motors Chairman and CEO Elon Musk should anyone lose their life or be severely injured in a Google or Apple self-driving car. Those crusty old car companies are actually better equipped to establish the standards and safety protocols and withstand the liability exposure of self-driving technology.

But the more fundamental challenge is the reality that a self-driving car is not likely to be owned, which means getting into the transportation business – the public transportation business. That’s a very different market from mobile devices and downloading content and selling cloud services. Apple and Google likely both perceive opportunities from enabling the systems, services and software that bring these applications to life – but would rather not take responsibility for creating and selling the hardware.
So, if you can’t go big, you go home. Or, if you currently work for Apple’s or Google’s self-driving car programs, you polish up that resume. It’s time to turn all that hard work into a real opportunity outside of those organizations. Your path to a profitable exit will be far shorter on the outside than by remaining inside these two large, newly-timid organizations. Investors are waiting and whatever you create will be your own.

Roger C. Lanctot is Associate Director in the Global Automotive Practice at Strategy Analytics. More details about Strategy Analytics can be found here: https://www.strategyanalytics.com/access-services/automotive#.VuGdXfkrKUk

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Zero Tolerance = Vision Zero

Zero Tolerance = Vision Zero
by Roger C. Lanctot on 09-13-2016 at 7:00 am
Categories: Automotive

Just returning from Sweden where the highway fatality rate is a marvel of modern transportation policy. Long before Sweden adopted a Vision Zero approach to reducing highway fatalities the country set itself apart from most others with a 0.02 blood alcohol limit for drivers. There is no question that this has contributed significantly to Sweden’s annual highway fatality rate per 100,000 population: 2.8.

The only country with a lower fatality rate than Sweden, according to the World Health Organization, is Iceland. I swear I detected a slight lip curl and eyebrow twitch on the part of my Swedish colleagues at the reminder that some other country was surpassing their admirable highway fatality reduction performance.

By comparison, the highway fatality rate in the U.S. is more than three times Sweden’s rate – 10.6. How has Sweden achieved this? Is there something in the water?

The allowable blood alcohol level for drivers in Sweden is 0.02. Sweden has, in effect, adopted a zero tolerance policy for alcohol consumption prior to driving. An “allowable” legal level of 0.02 leaves no wiggle room whatsoever.

Just a few weeks ago, Sweden’s minister for Higher Education, Aida Hadzialic, was breathalyzed while returning from a concert in Copenhagen at 0.02. She was charged with driving while under the influence of alcohol and subsequently resigned. (It’s worth noting that the “allowable” blood alcohol level in Denmark is 0.05 – so as the minister crossed the bridge from Denmark to Sweden she became an outlaw.)

Swedes will tell you that this driving restriction is deeply embedded in the culture and no one tests its bounds. This contrasts mightily with the U.S., as an example, where the 0.08 allowable blood alcohol level has drinkers in bars checking their watches to see if they can sneak in one more drink. In fact, state-level Department of Motor Vehicle communications warn that 0.08 means only one drink per hour.
By comparison to Sweden, the US DMV mentality practically recommends or advises one drink per hour. A 0.08 “allowable” blood alcohol level creates an unbearable temptation for many – while vaguely equating all drinks as equally deleterious – not if you’re getting the 20+-ouncer at the football game!

The Swedes are different. They enter navigation destination information by hand while driving because it would be more dangerous to pull over to do so – right? But the zero tolerance for alcohol in the blood while driving is serious business that has produced an admirable outcome.

Sweden, of course, hasn’t stopped there and the announcement this week that Autoliv was partnering with Volvo Cars to create an automated driving joint venture was just the latest indication that the country will remain a nexus for safe driving technology for the foreseeable future. A notable postscript is the burgeoning collaboration with Chinese car makers in the form of Geely’s ownership of Volvo Cars, the emergence of NEVS (National Electric Vehicle Sweden AB) from the ashes of Saab and the arrival of China Euro Vehicle Technology AB (2000 employees and growing).

The collaboration of the country with the safest roads and the country with the largest and fastest growing auto market with the most dangerous roads in the world is intriguing. It’s hardly a coincidence that Volvo’s market prospects are on the rise.

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Can it ever be game over in tech?

Can it ever be game over in tech?
by Don Dingee on 09-12-2016 at 4:00 pm
Categories: Mobile

The opening line of a recent Benedict Evans piece makes a bold statement: “The smartphone platform wars are pretty much over, and Apple and Google won.” Reading that line reminded me of the William Shatner scene in Airplane 2; let’s just shut it down and go home. That’s not the point Evans is making, however, Continue reading “Can it ever be game over in tech?”