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Intel’s Commitment to Corporate Responsibility: Driving Innovation and Sustainability

Intel’s Commitment to Corporate Responsibility: Driving Innovation and Sustainability
by Admin on 09-07-2025 at 6:00 am

Intel Corporate Responsibility Report 2025

Introduction by Lip-BU Tan:

I’m an engineer at heart. Nothing motivates me more than solving hard problems. Our teams across Intel are driven by this same mindset—inspired by the power of technology to enable new solutions to our customers’ toughest challenges.

I fundamentally believe this will be a catalyst for innovation throughout our company for years to come—and every day brings new opportunities for us to improve.

In our 2024-2025 Corporate Responsibility Report, you will see we have made important progress in many areas. We are driving greater compute performance in our products while improving their power efficiency. Our water conservation and use of renewable energy is supporting a resilient and sustainable manufacturing footprint. And our close collaboration with partners across our value chain is helping customers to achieve their own sustainability goals.

But this work is never done—and we have a lot of hard work ahead as we take actions to reshape our company, strengthen our culture, and empower our engineers to do what they do best.

Underpinning this work is a consistent focus on technology, sustainability, and talent investments aligned with our long-term goals. At the end of the day, our work in these areas drives innovation and growth—because when great people engineer great products to delight our customers, we strengthen our business and help meet the needs of a changing world.

I am looking forward to the work ahead as we build a new Intel. Thank you for your feedback and your partnership

Lip-Bu Tan

Chief Executive Officer

In the 2024-25 Corporate Responsibility Report, Intel outlines a refreshed strategy under new CEO Lip-Bu Tan, emphasizing transformation amid global challenges. Founded on principles of transparency, ethics, and human rights, the report highlights Intel’s integrated approach to corporate responsibility, aligning with frameworks like the UN Sustainable Development Goals and Global Reporting Initiative. With a targeted workforce of 75,000 employees worldwide, Intel’s efforts span people, sustainability, and technology, demonstrating how a tech giant can balance business growth with societal impact.

Central to Intel’s people-focused initiatives is fostering an inclusive, safe culture. The company invests in talent development, aiming to retain top performers through consistent indicators across talent systems. In 2024, Intel’s undesired turnover rate was 5.9%, reflecting ongoing economic pressures but also progress in employee engagement. Programs like Inclusive Leaders delivered 120 workshops to 2,271 participants, promoting dignity and respect, with 91% of employees reporting respectful treatment. Safety remains paramount, with a recordable injury rate of 0.71 per 100 employees, below the industry average. Intel’s global volunteer program, Intel Involved, saw employees contribute over 830,000 hours, amplified by $7.8 million in Foundation matches. Philanthropy totaled $79.5 million, supporting STEM education and humanitarian relief. Respecting human rights, Intel conducted 252 supplier audits, addressing forced labor and returning over $200,000 in fees to workers. Responsible minerals sourcing achieved 99% conformance, expanding to include aluminum and copper.

Sustainability efforts underscore Intel’s environmental stewardship. Achieving 98% renewable electricity globally, Intel reduced Scope 1 and 2 GHG emissions by 24% from 2019, avoiding 84% of cumulative emissions over the decade. The Climate Transition Action Plan targets net-zero Scope 1 and 2 by 2040. Energy conservation saved 2.4 billion kWh since 2020, with $104 million invested yielding $150 million in savings. Water stewardship restored net positive water in the US, India, Costa Rica, and Mexico, conserving 10.5 billion gallons and restoring 2.9 billion through projects like Oregon’s McKenzie River enhancement. Waste management upcycled 66% of manufacturing streams, diverting 74,000 tons from landfills via circular economy practices. Supply chain sustainability engaged 140 suppliers on GHG reductions, with 99% responding to CDP questionnaires. Responsible chemistry addressed PFAS through collaborations like the NSTC’s PRISM program, promoting safer alternatives.

Technology initiatives leverage Intel’s expertise for societal good. Product energy efficiency improved 4.0X for clients and 2.7X/3.0X for servers from 2019 baselines, reducing Scope 3 emissions. Responsible AI evolved with a new “Protect the Environment” principle, operationalizing governance for risks like bias. Intel’s Digital Readiness Programs trained 8 million in AI skills across 29 countries, emphasizing inclusion. The Intel Responsible Technology Initiative funded 465 projects in 42 countries, addressing health, education, and climate via solutions like AI for veterans’ transitions and water monitoring in mining.

Intel’s report reflects resilience amid challenges like economic pressures and geopolitical risks. By integrating responsibility into operations, Intel not only mitigates risks but also drives innovation, as seen in CHIPS Act awards bolstering US manufacturing. Looking ahead, Intel’s ambitions—net-zero emissions, inclusive AI, and resilient supply chains—position it as a leader in sustainable tech. This holistic approach ensures Intel enriches lives while building a stronger future for all stakeholders.

See the full report here.

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RANiX Employs CAST’s TSN IP Core in Revolutionary Automotive Antenna System

RANiX Employs CAST’s TSN IP Core in Revolutionary Automotive Antenna System
by Daniel Nenni on 09-06-2025 at 8:00 am

ranix TSN SW antenna array figure

This press release from CAST announces a significant collaboration with RANiX Inc., highlighting the integration of CAST’s TSN Switch IP core into RANiX’s new Integrated Micro Flat Antenna System (IMFAS) SoC. This development underscores the growing adoption of Time-Sensitive Networking (TSN) in the automotive sector, particularly for enhancing in-vehicle communication efficiency. As someone tracking advancements in automotive electronics and IP cores, I find this release both timely and insightful, though it leans heavily on promotional language typical of industry announcements.

At its core, the release details how RANiX, a South Korean leader in automotive and IoT communication chips, has leveraged CAST’s TSN technology to synchronize and route signals from a multi-protocol antenna array. The IMFAS SoC handles diverse protocols like 5G, WiFi, GNSS/GPS, BLE, and UWB, funneling them through an Ethernet backbone to the vehicle’s Telematics Control Unit (TCU). By replacing lengthy RF cable runs with TSN-enabled Ethernet, the system promises reduced complexity, lower costs, improved signal integrity, and seamless integration into Software-Defined Vehicles (SDVs). This is a smart evolution, aligning with the industry’s shift toward zonal architectures where centralized processing dominates.

CAST’s TSN-SW Multiport Ethernet Switch IP core is positioned as the enabler here, boasting ultra-low latency, standards compliance (e.g., IEEE 802.1Q), and configurability for applications beyond antennas, such as sensor fusion in automated parking or environmental sensing. The release quotes RANiX’s CTO, No Hyoung Lee, praising CAST’s forward-thinking approach to evolving TSN standards and their Functional Safety features, crucial for ISO 26262 compliance in automotive designs. Alexander Mozgovenko, CAST’s TSN Product Manager, reciprocates by lauding RANiX’s innovative use of the core, noting their long-standing partnership since 2011. This mutual endorsement adds credibility, but it also feels somewhat scripted, as press releases often do.

From a technical standpoint, the announcement is compelling. TSN’s ability to ensure deterministic timing and prioritization in Ethernet networks addresses a key pain point in modern vehicles, where real-time data from multiple sources must coexist without interference. RANiX’s IMFAS exemplifies this by creating a “flat” antenna system that minimizes physical cabling, potentially slashing weight and assembly costs—vital for electric vehicles aiming for efficiency. Moreover, CAST’s broader IP portfolio, including CAN-FD, LIN, and ASIL-D ready cores, positions them as a one-stop shop for automotive bus controllers, which could appeal to designers seeking integrated solutions.

However, the release has limitations. It lacks quantitative data, such as specific latency figures, cost savings percentages, or performance benchmarks, which would strengthen its claims. While it mentions “proven reliability” and “cost-effectiveness,” these are vague without metrics or third-party validations. Additionally, the focus on RANiX’s 80% market share in South Korean tolling chipsets feels tangential, perhaps included to bolster their credentials but not directly tied to IMFAS. In a broader context, with TSN still emerging in automotive (as the release notes some firms are “still contemplating” adoption), this could be a bellwether for wider implementation, especially amid the push for autonomous driving.

Overall, this press release showcases a practical TSN application, signaling progress in Ethernet-based vehicle networks. It’s well-structured, with clear sections on the technology, quotes, and company backgrounds, making it accessible to both technical audiences and investors. For CAST, it reinforces their expertise in IP cores since 1993; for RANiX, it highlights their innovation in a competitive field. If executed as described, the IMFAS could indeed simplify in-vehicle communications, paving the way for smarter, more efficient cars. That said, I’d love to see follow-up data on real-world deployments to gauge its impact. In an era of rapid automotive electrification and connectivity, announcements like this are exciting harbingers of what’s next.

Link to Press Release

Also Read:

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WEBINAR Unpacking System Performance: Supercharge Your Systems with Lossless Compression IPs

Podcast EP273: An Overview of the RISC-V Market and CAST’s unique Abilities to Grow the Market with Evan Price

CAST Advances Lossless Data Compression Speed with a New IP Core


Podcast EP306: The Challenges of Advanced AI Data Center Design with Josue Navarro

Podcast EP306: The Challenges of Advanced AI Data Center Design with Josue Navarro
by Daniel Nenni on 09-05-2025 at 10:00 am

Dan is joined by Josue Navarro, product marketing engineer for Microchip’s dsPIC business unit. He began his career as a process engineer at Intel and has since transitioned into product marketing with Microchip Technology where he supports customers developing system designs utilizing Microchip’s Digital Signal Controllers.

Dan explores AI-focused data centers and the associated challenges they present with Josue. What is needed to address energy and thermal efficiency, reliability, and sustainability are some of the topics covered in this broad and informative discussion. Josue discusses where technologies such as liquid cooling and real-time thermal monitoring fit. He explains that next generation AI data centers present a 3X power density increase. Josue provides an overview of the far-reaching environmental impacts that must be addressed and how Microchip is working with the industry to help address these challenges.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.


Cadence’s Strategic Leap: Acquiring Hexagon’s Design & Engineering Business

Cadence’s Strategic Leap: Acquiring Hexagon’s Design & Engineering Business
by Admin on 09-05-2025 at 8:00 am

Cadence Hexagon

In a bold move that underscores the accelerating convergence of electronic design automation (EDA) and mechanical engineering, Cadence Design Systems announced its agreement to acquire Hexagon AB’s Design & Engineering (D&E) business for approximately €2.7 billion, equivalent to about $3.16 billion. This transaction, expected to close in the first quarter of 2026, represents a significant expansion for Cadence, integrating advanced simulation technologies into its portfolio and positioning the company at the forefront of physical AI and complex system design.

Cadence Design Systems, headquartered in San Jose, California, is a global leader in EDA software, providing tools essential for designing integrated circuits, systems-on-chips, and printed circuit boards. The company has long been a staple in the semiconductor industry, aiding giants like Intel and NVIDIA in bringing cutting-edge chips to market. Over the years, Cadence has pursued aggressive growth through acquisitions, such as its 2023 purchase of Intrinsix for aerospace and defense expertise, and the 2024 integration of BETA CAE Systems to bolster its multiphysics simulation capabilities. This latest deal with Hexagon fits seamlessly into that strategy, enhancing Cadence’s offerings in system-level analysis where electronic and mechanical domains intersect.

Hexagon AB, a Stockholm-based multinational technology group, specializes in digital reality solutions that combine sensor, software, and autonomous technologies. Its D&E business, which generated around €500 million in revenue in 2024, includes flagship products like MSC Software, a pioneer in computer-aided engineering (CAE) simulations. MSC’s tools excel in structural analysis, multibody dynamics, and acoustics, serving industries from automotive to aerospace. By divesting this unit, Hexagon aims to streamline its portfolio, focusing on its core strengths in metrology, geospatial software, and manufacturing intelligence. The sale aligns with Hexagon’s ongoing efforts to optimize operations, as stated in their press release, allowing them to invest more heavily in high-growth areas like smart manufacturing and sustainability solutions.

Under the terms of the agreement, Cadence will fund 70% of the purchase price in cash and the remaining 30% in stock, providing Hexagon with a stake in Cadence’s future success. This hybrid payment structure not only mitigates immediate cash outflow for Cadence but also signals confidence in the synergies ahead. The acquisition is poised to accelerate Cadence’s Intelligent System Design strategy, which emphasizes AI-driven workflows for faster, more efficient product development. By incorporating Hexagon’s mechanical simulation expertise, Cadence can offer end-to-end solutions for multidomain systems—think electric vehicles where battery electronics must integrate flawlessly with structural components, or drones requiring precise aerodynamics alongside embedded software.

The strategic implications are profound. In an era where products are increasingly “smart” and interconnected, the boundaries between hardware disciplines are blurring. Cadence’s CEO, Anirudh Devgan, highlighted in the announcement that this move will “accelerate our expansion in physical AI and system design and analysis,” enabling customers to tackle unprecedented complexity in product engineering. For instance, automotive manufacturers could simulate vehicle crashes with integrated electronics behavior, reducing prototyping costs and time-to-market. Aerospace firms might optimize aircraft designs for fuel efficiency while ensuring electronic systems withstand vibrations. This integration is particularly timely amid the rise of Industry 4.0, where digital twins—virtual replicas of physical assets—demand sophisticated multiphysics modeling.

Market analysts have reacted positively, viewing the deal as a catalyst for Cadence’s growth in non-traditional EDA sectors. Shares of Cadence rose modestly in after-hours trading following the announcement, reflecting investor optimism about revenue diversification. Hexagon’s stock also saw gains, as the divestiture is seen as unlocking value for shareholders. However, challenges loom: integrating Hexagon’s 2,000+ employees and ensuring cultural alignment will be key. Regulatory approvals, especially in Europe and the U.S., could pose hurdles given the deal’s size and the strategic importance of simulation technologies in defense applications.

Looking ahead, this acquisition could reshape the CAE landscape, intensifying competition with rivals like Ansys (recently acquired by Synopsys) and Siemens Digital Industries Software. Cadence’s enhanced portfolio might spur innovation in emerging fields like sustainable energy systems and biomedical devices, where precise engineering simulations are critical.

Bottom line: Cadence’s acquisition of Hexagon’s D&E business is more than a financial transaction—it’s a visionary step toward unified engineering platforms in a hyper-connected world. As industries demand faster iteration and greater reliability, this union promises to deliver tools that bridge electronic and mechanical worlds, fostering breakthroughs that could define the next decade of technological advancement.

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Streamlining Functional Verification for Multi-Die and Chiplet Designs


TSMC 2025 Update: Riding the AI Wave Amid Global Expansion

TSMC 2025 Update: Riding the AI Wave Amid Global Expansion
by Daniel Nenni on 09-05-2025 at 6:00 am

CC Wei Donold Trump Handshake

Welcome to the second half of a very exciting year in semiconductors. While Intel and Samsung Foundry have made quite a few headlines, TSMC continues to execute flawlessly at 3nm and 2nm. With the TSMC OIP Ecosystem Forums starting later this month let’s take a look at how we got to where we are today.

The TSMC OIP Ecosystem Forum is the second series of events. At the previous TSMC Technology Symposium last April we were told that N2 design starts were exceeding N3 which was quite a statement. From what I have learned from the ecosystem over the last few months, that may have been an understatement. TSMC N2 is absolutely dominating the foundry business and for good reasons, but most importantly it is trust. TSMC’s market share at 3nm and 2nm is upwards of 90% while their total market share is now between 60-70%. Simply amazing but well deserved.

Financially, TSMC has delivered stellar results. In the second quarter of 2025, revenue reached a record $30.1 billion, marking a 44% year-over-year increase. Gross margins climbed to 59%, up 5 percentage points from the previous year, reflecting strong pricing power and efficiency gains from previous nodes. Net profit surged, with earnings per share hitting NT$15.36, beating analyst forecasts. For the first half of the year, total sales hit $60.5 billion, a 40% jump from 2024. Buoyed by this momentum, TSMC raised its full-year 2025 revenue growth guidance to approximately 30%, up from 25%. Personally I believe TSMC is once again being conservative. My guess would be 35% revenue growth but that depends on China business (Nvidia) which seems to be constrained.  Either way it will be another great year for TSMC.

My optimism stems from unrelenting AI-related demand with revenue from AI accelerators expected to double in 2025. TSMC capital expenditures for the year are projected at $38 billion to $42 billion, focusing on advanced process technologies and overall capacity expansion.

On the technology front TSMC is still pushing boundaries. The company plans to start high volume manufacturing of its N2 chips in the fourth quarter of 2025 which is earlier than anticipated, meaning yield is higher than anticipated. Trial production at its Kaohsiung and Hsinchu fabs has already begun with Apple, Nvidia, AMD, Qualcomm, and MediaTek leading customer demand. Looking further ahead, TSMC broke ground on a 1.4nm facility in Taiwan, with mass production targeted for the second half of 2028, promising 15% performance gains and 30% power savings. Additionally, advanced packaging capacity (CoWoS) has already doubled to 75,000 WPM six months ahead of schedule through partnerships with ASE and Amkor.

Expansion remains a key strategy amid geopolitical tensions. TSMC’s Arizona subsidiary turned profitable in the first half of 2025, reporting a $150.1 million net profit after initial losses. The company is also advancing fabs in Europe and Japan to strengthen supply chains. In Taiwan, new facilities like Fab 25 in the Central Taiwan Science Park will house 1.4nm and 1nm plants with trial production starting in 2027. A new Taiwanese law ensures cutting-edge tech stays on the island, keeping overseas fabs one generation (N-1) behind. This move addresses U.S.-China trade frictions and potential tariffs, which TSMC has flagged as potential risks.

Despite headwinds like currency fluctuations and rising operational costs, TSMC’s outlook is bullish. Third-quarter revenue is forecasted at $31.8 billion to $33 billion, supported by AI and high-performance computing demand. Monthly revenues through June 2025 showed consistent growth, with June alone up 39.6% year-over-year. Analysts maintain a “Buy” rating, citing sustained AI momentum and even Jensen Huang (Nvidia CEO) has a “Buy” rating on TSMC (“anybody who wants to buy TSMC stock is a very smart person”). Never in the 30+ year history of Nvidia and TSMC have I ever seen Jensen so complimentary of TSMC and that will tell you how closely they are working together.

From 2025 to 2030, TSMC’s investments will reshape sectors like AI, automotive, and consumer electronics, reinforcing its ecosystem for a competitive landscape. As my semiconductor bellwether, TSMC’s trajectory signals a thriving semiconductor industry though vigilance on geopolitics remains essential. Dr. C.C. Wei has proven to be a politically savvy leader so I have no concerns here at this point in time. Go TSMC and GO semiconductor industry, $1 trillion dollars by 2030, absolutely!

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Alchip’s 3DIC Test Chip: A Leap Forward for AI and HPC Innovation

Alchip’s 3DIC Test Chip: A Leap Forward for AI and HPC Innovation
by Daniel Nenni on 09-04-2025 at 10:00 am

Alchip 3D IC Test Chip TSMC N2

Today Alchip Technologies, a Taipei-based leader in high-performance and AI computing ASICs, announced a significant milestone with the successful tape-out of its 3D IC test chip. This achievement not only validates Alchip’s advanced 3D IC ecosystem but also positions the company as a frontrunner in the rapidly evolving field of three-dimensional integrated circuits. By proving the readiness of an integrated 3DIC solution, including critical components like CPU/NPU cores, UCIe and PCIe PHY, Lite-IO infrastructure, and third-party IP, Alchip is paving the way for faster, more efficient designs in artificial intelligence (AI) and high-performance computing (HPC).

The importance of this test chip lies in its validation of Alchip’s comprehensive 3DIC ecosystem, which is tailored to meet the demands of complex ASIC designs. Unlike traditional 2D ICs, 3DICs involve stacking multiple dies vertically, introducing unique challenges in power density, thermal dissipation, and interconnectivity. Alchip’s test chip, integrating a 3nm top die and a 5nm base die using TSMC’s SoIC-X packaging technology, was designed to tackle these challenges head-on. The successful tape-out confirms the company’s ability to deliver a robust design flow, die-to-die IP, and interconnect solutions, ensuring accuracy and reduced time-to-market for AI and HPC developers.

“What these test chip results should tell hyperscalers and other AI/HPC designers is that don’t have to settle for less-than design-optimal advanced packaging solutions.   We’ve just proven an advanced packaging ecosystem that can meet the most precise 3DIC requirements,” explained Dr. Dave Hwang, Sr. Vice President and North America General Manager, Alchip Technologies.

A key aspect of the test chip is its demonstration of advanced 3DIC capabilities. The top die incorporates a CPU, NPU core, and high-power logic, while the base die features a network-on-chip, L3 cache, and interface IP. These components are connected via APLink-3D Lite IO, enabling seamless communication between dies. The tape-out validated critical features, including cross-die synchronous IP, design-for-test strategies with redundancy and repair, signal and power integrity analysis, thermal and mechanical simulations, and 3D physical design implementation. These validations are crucial, as 3DIC designs require precise coordination to ensure performance and reliability across stacked dies.

Alchip’s achievement is particularly noteworthy due to the complexity of 3DIC design. Unlike 2D counterparts, 3DICs demand new approaches to physical and logical integration. Alchip updated its electronic design automation (EDA) tools and methodologies to support co-design across both dies, ensuring electrical, timing, and mechanical integrity. The company also tested custom interface IP tailored for 3DICs, addressing interoperability challenges for protocols like UCIe and PCIe. A standout feature is the 3DI/O timing, which limits die-to-die latency to just 40 picoseconds. This low latency, combined with a fully integrated 3D clocking structure, minimizes timing skew and ensures coherent operation across layers, a critical factor for high-performance applications.

The test chip program also highlighted Alchip’s collaborative approach. Four IP vendors participated, with two providing proven hard macros and two others testing new IP on the platform. An EDA flow vendor ensured tool and methodology readiness, reinforcing the ecosystem’s strength. This collaboration underscores the scarcity of 3DIC-proven IP, making Alchip’s validated solutions highly valuable for developers seeking reliable components for next-generation ASICs.

The implications of this tape-out extend beyond the test chip itself. By stress-testing power density and thermal dissipation, Alchip has gathered insights that will inform future 3DIC designs, including those using TSMC N2, N3 and N5 stacked chiplets.

Bottom line: Alchip’s 3DIC test chip tape-out marks a pivotal moment for the semiconductor industry. By validating its 3DIC ecosystem, Alchip not only demonstrates technical prowess but also provides a reliable pathway for AI and HPC innovation. This milestone sets a new standard for 3DIC design, promising faster, more efficient, and scalable solutions for the future of computing.

The official news release is here.

About Alchip

Alchip Technologies Ltd., founded in 2003 and headquartered in Taipei, Taiwan, is a leading global High-Performance Computing and AI infrastructure ASIC provider of IC and packaging design, and production services for system companies developing complex and high-volume ASICs and SoCs. Alchip provides faster time-to-market and cost-effective solutions for SoC design at mainstream and advanced process technology. Alchip has built its reputation as a high-performance ASIC leader through its advanced 2.5D/3D CoWoS packaging, chiplet design, and manufacturing management. Customers include global leaders in artificial intelligence, high-performance computing, supercomputing, mobile communications, entertainment devices, networking equipment, and other electronic product categories.

Also Read:

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WEBINAR: Functional ECO Solution for Mixed-Signal ASIC Design

WEBINAR: Functional ECO Solution for Mixed-Signal ASIC Design
by Daniel Nenni on 09-04-2025 at 8:00 am

Blog image

This webinar, in partnership with Easy-Logic Technology, is to address the complexities and challenges associated with functional ECO (Engineering Change Order) in ASIC design, with a particular focus on mixed-signal designs.

The webinar begins by highlighting the critical role of mixed-signal chips in modern applications, then explores the various ECO needs that arise when these chips are part of complex system environments combining diverse analog measurement protocols and digital communication methods.  The discussion then focuses on the technical challenges faced by design teams and the solutions provided by Easy-Logic.  This segment takes center stage in the webinar, emphasizing the importance of efficient and effective ECO processes in overcoming these challenges within mixed-signal ASIC design.

WATCH THE REPLAY HERE

Mixed-signal ASIC applications

Mixed-signal ASICs are essential in systems that need to process real-world analog signals and perform digital computation or control. These designs are crucial for a wide range of applications, including:

  • Smartphones and tablets: Many mixed-signal ASICs, such as power management chips and LCD drivers, are used
  • Medical devices: Examples include biosensors and other medical electronics.
  • Automotive electronics: These ASICs are used in sensors (image, radar, temperature, etc.) and control units.
  • Industrial automation: Mixed-signal ASICs play a role in various motion control applications.
  • IoT devices: These designs are integral to the functionality of IoT devices.

Mixed-signal ASICs typically include a combination of analog blocks and digital blocks, and interface circuits for communication protocols like USB, SPI, and I2C.

What causes the high number of functional ECO requests? 

Mixed-signal ASICs drive the rapid evolution of everyday applications. While analog circuitry dominates these designs, the digital components introduce a unique set of complex ECO challenges.

The webinar discussion highlights several technical challenges, including:
  1. Short project cycle (i.e., 6 months per chip) and tight ECO windows
  2. Multiple successive ECO operations on the same digital block
  3. RTL design with ECOs performed manually
  4. ECOs in mixed-level designs that combine both RTL and netlist
  5. Frequent changes to analog circuitry affect input timing to the digital block
  6. Customer system specifications require modifications to peripheral blocks
  7. Scan chain repairs required when the ECO operation disrupts the chain
  8. ECO logic modifications with limited spare resources available
  9. ECO requests requested after the test chip release

Easy-Logic’s Proven Expertise

Mixed-signal applications demand tailored ECO solutions—not a traditional one-size-fits-all approach.   Easy-Logic provides an innovative approach designed to address these specific challenges.

With over 10 years of experience in solving functional ECO challenges, Easy-Logic offers a comprehensive solution that addresses ECO issues across a wide spectrum of ASIC design.  Its technology has been widely deployed across a broad range of customer projects and design segments.

Mixed-signal ASIC design, positioned at one end of the spectrum, represents a diverse range of ECO requirements.  This webinar will draw upon Easy-Logic’s extensive ECO expertise and feature the following:

  • Practical solutions and methodologies to simplify the ECO process in mixed-signal design
  • Specialized tool algorithms developed to significantly optimize logic patch size
  • An overview of the underlying technology used to address various ECO challenges

WATCH THE REPLAY HERE

About Easy-Logic Technology

Easy-Logic Technology is a leading provider of cutting-edge functional ECO solutions in the semiconductor industry. With a focus on innovation and customer satisfaction, Easy-Logic Technology delivers advanced tools and technologies that enable its customers to achieve excellence in ASIC design.

Also Read:

Perforce Webinar: Can You Trust GenAI for Your Next Chip Design?

Unlocking Efficiency and Performance with Simultaneous Multi-Threading

DAC TechTalk – A Siemens and NVIDIA Perspective on Unlocking the Power of AI in EDA


Beyond Von Neumann: Toward a Unified Deterministic Architecture

Beyond Von Neumann: Toward a Unified Deterministic Architecture
by Admin on 09-04-2025 at 6:00 am

Beyond Von Neumann

By Thang Tran

For more than half a century, the foundations of computing have stood on a single architecture: the Von Neumann or Harvard model. Nearly all modern chips—CPUs, GPUs, and even many specialized accelerators—rely on some variant of this design. Over time, the industry has layered on complexity and specialization to keep up with new demands. Very Long Instruction Word (VLIW) architectures, dataflow chips, and GPUs were each introduced as point solutions to specific bottlenecks, but none offered a holistic alternative. Until now.

Simplex Micro has developed what may be the most significant departure from the traditional paradigm in over half a century—enabling unified scalar, vector, and matrix compute in a single deterministic pipeline. At its core is a revolutionary concept: Predictive Execution. Unlike dynamic execution—which guesses what will happen next—Predictive Execution statically schedules each operation with cycle-level precision, transforming the processor into a deterministic machine with a known execution timeline. This allows a single chip architecture to handle both general-purpose tasks and high-throughput AI workloads without the need for separate accelerators.

The End of Guesswork

Deterministic execution eliminates the inefficiencies and vulnerabilities of dynamic execution. Instead of dynamically dispatching instructions and rolling back incorrect paths, Predictive Execution ensures that every instruction is issued at exactly the right time with the right resources. It’s not just more efficient—it’s predictable, scalable, and inherently more secure.

The breakthrough lies in what Simplex calls the Time-Resource Matrix: a novel patented scheduling mechanism that allocates compute, memory, and control resources across time. Each instruction has a designated time slot and access window, ensuring zero-overlap and eliminating pipeline stalls. Think of it as a train schedule—except the trains are scalar, vector, and matrix operations moving across a synchronized compute fabric.

A Unified Architecture

This innovation allows a single processor to act as both CPU and accelerator, with no switching overhead, no mismatched memory hierarchies, and no need for costly data transfers between heterogeneous units. It’s a general-purpose architecture that matches—and in many cases exceeds—the performance of dedicated AI engines.

This unification is made possible through a suite of patented innovations shown to have no direct relevant prior art. The Time-Resource Matrix provides the foundational execution schedule, but other breakthroughs extend it into new domains: Phantom Registers allow the system to pipeline instructions beyond physical register file limits, Vector Data Buffers, and Extended Vector Register Sets enable seamless scaling of parallel compute for AI operations. Instruction Replay Buffers ensure that even variable-latency memory or branch events can be resolved predictably without dynamic execution guesswork.

Together, these inventions form the building blocks of a compute engine that behaves like a CPU in its flexibility but delivers the sustained throughput of an accelerator—without needing two separate chips. Whether it’s matrix-heavy AI inference or control-heavy real-time decision making, the same processor handles both efficiently, synchronously, and without architectural switching. This represents not just an evolution, but a true reinvention of general-purpose computing.

Real-World Relevance

As AI workloads grow in size and complexity, conventional architectures are buckling under the weight. GPUs require massive power budgets and still struggle with memory bottlenecks. CPUs lack the parallelism needed for modern inference and training tasks. Meanwhile, multi-chip solutions suffer from latency, synchronization, and software fragmentation.

With Predictive Execution, Simplex delivers a unified, time-driven machine that’s already being implemented in RISC-V Vector processors and is ready for integration in next-generation AI infrastructure. It’s not a theoretical concept—it’s working RTL with simulation results, on track to run production code.

For chip architects, this means simpler system design with lower silicon footprint. For software developers, it means programming a unified, predictable target with consistent timing behavior—ideal for safety-critical and performance-sensitive applications alike.

The Path Forward

This is not just a performance story. It’s a return to architectural elegance, where one chip can serve many roles without compromise. By eliminating dynamic execution and grounding execution in deterministic time windows, Simplex has created a platform that can scale with the needs of future AI, edge computing, and cloud applications.

As we enter a new era of AI-driven applications, the need for scalable, unified, and deterministic compute has never been greater. Predictive Execution lays the foundation—and we invite the research and engineering community to build on it.

Selected Patents

  1. US-11829762-B2 – Time-resource matrix for a microprocessor with time counter
  2. US 12,001,848 B2 – Phantom Registers for Pipelined Vector Execution
  3. US 12,282,772 B2 – Vector Data Buffer for Scalable Parallel Processing
  4. US 12,124,849 B2 – Extended Vector Register Architecture for AI Compute
  5. US 12,190,116 B2 – Instruction Replay Buffer with Deterministic Scheduling

About the Author

Dr. Thang Minh Tran is CTO and Founder of Simplex Micro and UT Austin Alumni. He is an inventor of over 180 issued patents in microprocessor design, including pioneering work at AMD, Texas Instruments, Freescale, Analog Devices, and Andes Technology, where he created the first RISC-V with Vector extensions now designed into Meta’s MTIA chip.

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Intel Unveils Clearwater Forest: Power-Efficient Xeon for the Next Generation of Data Centers

Intel Unveils Clearwater Forest: Power-Efficient Xeon for the Next Generation of Data Centers
by Kalar Rajendiran on 09-03-2025 at 10:00 am

Hot Chips Logo 2025

At the recent Hot Chips conference, Intel® unveiled Clearwater Forest, its next-generation Xeon® 6 processor with efficiency cores (E-cores). The unveiling was made by Don Soltis, Xeon Processor Architect and Intel Fellow with over four decades of processor design experience and a long-standing contributor to the Xeon roadmap. Built to deliver density and energy efficiency for large-scale data centers, Clearwater Forest reflects years of architectural refinement and cutting-edge process innovation.

Efficiency at the Heart of Xeon 6

The Xeon 6 family has been designed to address a wide range of customer needs. P-core series processors target compute-intensive and AI workloads, while E-core series processors like Clearwater Forest are optimized for scale-out, high-density deployments where performance per watt and total cost of ownership are critical. Sharing a common platform foundation and software stack, the two series allow customers to mix and match without redesigning their infrastructure.

Clearwater Forest is built on Intel’s 18A process technology, which combines backside power delivery and gate-all-around transistors for better efficiency and higher density. The design reduces RC delays, lowers IR drop, and improves signal integrity, all while enabling over 90% cell utilization. Together, these advances allow Clearwater Forest to deliver more compute capability in less space with reduced power consumption.

Inside Clearwater Forest

 

Architectural Advancements

At the microarchitectural level, Clearwater Forest introduces significant leaps over Sierra Forest, Intel’s first-generation E-core Xeon. The front end features a 64 KB instruction cache with an on-demand length decoder for large code footprints, nine instructions per cycle via three 3-wide decoders, and deeper, more accurate branch prediction.

The out-of-order engine expands to eight-wide allocation and sixteen-wide retire, with a 416-entry window to uncover more data parallelism. Execution resources have been widened to 26 ports, while the execution engine itself doubles the throughput of both integer and vector operations. Load address generation improves by 1.5×, and store address generation doubles.

Memory handling is also more advanced. The subsystem supports three loads per cycle, 128 outstanding L2 misses, and sophisticated prefetchers across all cache levels. Each module consists of four cores sharing a 4 MB unified L2 cache with 17-cycle latency and twice the bandwidth of the previous generation, delivering up to 400 GB/s. Collectively, these changes result in an estimated 17% IPC uplift on SPECintRate 2017 benchmarks.

3D Chiplet Construction

Clearwater Forest makes extensive use of Intel’s Foveros Direct 3D chiplet technology, optimizing each function for the most suitable process node. The design integrates twelve CPU chiplets on Intel 18A, three base chiplets on Intel 3 for fabric, LLC, and memory controllers, and two I/O chiplets on Intel 7 for high-speed connectivity and accelerators. A monolithic mesh fabric ties everything together, with shorter interconnect routes improving both performance and power efficiency.

Performance

In a dual-socket configuration, Clearwater Forest supports 576 E-cores and 1152 MB of last-level cache. System bandwidth is equally impressive, with two sets of twelve DDR5-8000 channels delivering around 1300 GB/s read bandwidth, along with dual 96-lane PCIe 5.0 connections and 64 CXL lanes for device scalability. In addition, 144 lanes of UPI coherency provide low-latency remote memory access.

Designed for TCO and Scalability

The guiding principle behind Clearwater Forest is efficiency at scale. By enabling higher vCPU density per rack and reducing power draw, the processor allows data center operators to optimize both capital and operational expenditures. With innovations spanning process technology, microarchitecture, 3D packaging, and system-level bandwidth, Clearwater Forest sets a new benchmark for performance per watt in high-density compute deployments.

Summary

As Intel’s latest entry in the Xeon 6 family, Clearwater Forest demonstrates how architectural ingenuity and manufacturing advances can combine to deliver sustainable scaling for the most demanding cloud and enterprise workloads.

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EUV Resist Degradation with Outgassing at Higher Doses

EUV Resist Degradation with Outgassing at Higher Doses
by Fred Chen on 09-03-2025 at 8:00 am

EUV Resist Degradation with Outgassing at Higher Doses

Dosing for EUV lithography walks a fine line between productivity and defectivity. Fabs can choose higher-dose exposures to suppress photon shot noise [1]. However, higher doses require EUV machines to scan the wafer at slower speeds, degrading throughput [2].

On the other hand, there is the threat of resist thickness loss that increases with dose, due to correspondingly increased exposure to the EUV-induced hydrogen plasma [3-5]. Now, there is accumulated data indicating that, even without considering the EUV-induced plasma, the EUV exposure itself degrades the resist, as evidenced by outgassing, even before the resist is developed.

IMEC studied the outgassing for an environmentally stable chemically amplified photoresist (ESCAP) as a function of dose using photoemission spectroscopy (PES) [6]. At a dose as high as 200 mJ/cm2, the PES spectra shows a visible difference from the unexposed case. X-ray photoelectron spectroscopy (XPS) measurements showed that the photoacid generator (PAG) contains a fluorine-containing anion that outgasses significantly during EUV exposure, increasing as a function of dose (Figure 1).

Figure 1. Loss of fluorine from ESCAP as a function of exposure dose, as measured by XPS [6].

30% of the fluorine was lost at a popularly targeted dose of 60 mJ/cm2. This represents significant PAG degradation that occurs during EUV exposure. This degradation is known to cause an increase in line edge roughness with higher dose, because acid generator concentration decreases with higher dose, decreasing the acid image contrast [7].

The outgassing increase with higher dose has also been observed in other resist platforms targeting higher EUV absorption as well. In particular, again using XPS, more than 20% carbon loss was detected at 100 mJ/cm2 in tin-based EUV photoresists studied by a group headed by the University of Amsterdam (Figure 2).

Figure 2. Loss of carbon from tin-based EUV resists as a function of exposure dose, as measured by XPS [8].

Even at a moderate dose of 50 mJ/cm2, the carbon loss in these tin-based resists is already at least 10%! The carbon loss or displacement could correspond to losses in solubility in developer [8]. Therefore, resist degradation by EUV exposure is a fundamental issue that must be considered carefully in the context of increasing absorbed dose to control EUV stochastics [1].

Exposing EUV

References

[1] C. Mack, Stochastics: Yield-Killing Gap No One Wants to Talk About.

[2] I. Fomenkov et al., Adv. Opt. Techn. 6, 173–186 (2017).

[3] Y-H. Huang, C-J. Lin, and Y-C. King, A study of hydrogen plasma-induced charging effect in EUV lithography systems (2023).

[4] F. Chen, Resist Loss Prohibits Elevated EUV Doses (2025).

[5] F. Chen, Resist Loss Model for the EUV Stochastic Defectivity Cliffs (2025).

[6] L. Galleni et al., Proc. SPIE 13428, 134281D (2025).

[7] T. Kozawa, Jap. J. Appl. Phys. 51, 06FC01 (2012).

[8] Q. Evrard et al., Proc. SPIE 12498, 124980Z (2023).

This article originally appeared in Substack: EUV Resist Degradation with Outgassing at Higher Doses

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Edge Roughness Differences Among EUV Resists

Edge Roughness Differences Among EUV Resists