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Semiconductor Expert Forum

Podcast EP292: The Expanding Worldwide Focus of the 83rd Device Research Conference with Dr. Tania Roy

Podcast EP292: The Expanding Worldwide Focus of the 83rd Device Research Conference with Dr. Tania Roy
by Daniel Nenni on 06-20-2025 at 6:00 am

Dan is joined by Dr. Tania Roy, Associate Professor in Electrical and Computer Engineering at Duke University. She focuses on developing innovative hardware for artificial intelligence using advanced materials beyond silicon. Her research explores reliable gallium nitride (GaN) devices and new materials to move beyond traditional silicon, aiming to power the next generation of chips. As the Technical Program Chair for the 83rd Device Research Conference or DRC 2025, she is shaping a dynamic program featuring breakthroughs in areas like quantum devices and chip integration. The conference is set for June 22–25 at Duke University in Durham, North Carolina. She also organizes other semiconductor device conferences, such as IEDM and SISC.

Tania provides some history for Dan about the incredible 83 years of DRC, the longest-running device research meeting in the world. Tania explains that DRC attendance has traditionally focused on academia and students working on device and circuit research. Industry is now beginning to attend the event, to both present work and learn about advanced material research that goes beyond silicon. Tania is actively working to expand the focus of the conference toward more industry participation.

You can learn more about this important event and register to attend here.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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Keysight at the 2025 Design Automation Conference #62DAC

Keysight at the 2025 Design Automation Conference #62DAC
by Daniel Nenni on 06-19-2025 at 10:00 am
Categories: EDA, Events, Keysight EDA

62nd DAC SemiWiki

Keysight Showcases AI-Ready EDA and Multi-Physics Innovation at #62DAC

Design engineers attending #62DAC who focus on Design Data & IP Management, Analog, Mixed-Signal, RFIC, MMIC, or Multi-Physics should make booth #1408 a top destination. I had the opportunity to speak with Simon Rance, General Manager & Business Unit Leader at Keysight, about what’s coming to DAC 2025—and it’s clear Keysight is rethinking the design engineering experience from the ground up.

What stood out immediately is Keysight’s integrated approach to design engineering software. At DAC 2025, they’ll be showcasing innovations in:

  • Multi-Physics Engineering Workflows
  • AI-Ready EDA for RF Design
  • AI-Driven Data Management
  • Unified Software Workflows for CAE, EDA, Data Management, and Optics

The booth will also host presentations from customers and partners who are using Keysight’s tools to tackle real-world design challenges. Hear insights from Alphawave, Fermilab, Intel Foundry, Rice University, Sphere Semi, DuPont, Berkeley Lab, and FILPAL, along with technology partners Silvaco and Ansys. The schedule can be found here.

And yes—there’s also entertainment from Comedy Industries and the chance to win some great prizes.

Be sure to stop by Keysight booth #1408 to explore the future of AI-enabled design engineering.

DAC attendees can book suite session in advance with Keysight experts on five different topic areas:

  • Design data management for Chiplets and SoCs
  • Design data management for Analog/Mixed-Signal
  • Design data management for RFIC/MMIC
  • AI-ready workflow automation
  • RF/uW design and simulation
DAC PROGRAM – KEYSIGHT
  • Monday, June 23rd 4:00 pm – 4:45 pm in the DAC Pavilion, Nilesh Kamdar, Design and Verification GM at Keysight will participate in the The CHIPS Act’s Role in Semiconductor Innovation Attendees will learn how this new Act will accelerate next-generation design methodologies, AI-driven automation and cloud-enabled collaboration, while keeping the U.S. semiconductor industry competitive.
  • Monday, June 23rd from 5:00 pm – 6:00 pm, there are three Engineering Track posters from Keysight Generative AI for analog mixed-signal during documentation and traceability, modern database replication methods for cloud migration, smart caching to manage data from AI-powered EDA flows.
  • Monday, June 23rd from 5:28 pm – 5:35 pm in the DAC Pavilion, Prathna Sekar, manager for Data and IP Management Products will compete in the Annual Poster Gladiator Completion. All invited to attend, audience votes for the best gladiator to win.
  • Monday, June 23rd from 2:30 pm – 3:00 PM in the Exhibitor Forum on Level 1, Pedros Pires, Product Manager for Data and IP Management Products will present how to master data management, using his insights and case studies. Keysight’s Design Data Management (SOS) helps design teams to streamline the management of design and engineering data. SOS integrates with third-party Source Code Management (SCM) tools like Git to help automate workflows and speed time to market.
Summary

Visit Keysight at DAC in booth #1408, on the first level of Moscone West, from June 23 – 25. In case you cannot view one of the theatre presentations live, there will be an opportunity to view archived videos after DAC concludes on their YouTube channel.

Keysight is both a DAC Silver Sponsor and an I LOVE DAC Sponsor this year, so there’s no excuse to not attend DAC in San Francisco.

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Infinisim at the 2025 Design Automation Design Conference #62DAC

Infinisim at the 2025 Design Automation Design Conference #62DAC
by Daniel Nenni on 06-19-2025 at 8:00 am
Categories: EDA, Events, Infinisim

62nd DAC SemiWiki

Clock Matters: What Infinisim Is Showcasing at DAC 2025
Optimize by Finding and Fixing Errors Across the Entire Clock Domain

The clock domain is the heartbeat of every high-performance SoC—and at DAC 2025, Infinisim is redefining how design teams approach clock optimization with speed, precision, and confidence.

If you’re attending the show, be sure to stop by booth 2426 to explore how they are helping leading chipmakers push PPA limits without compromising reliability. Here’s what they will be showcasing:

Clock ECO with Immediate Impact Analysis

Tired of black-box timing adjustments and blind-side clock edits? Infinisim’s ECO solution puts real-time control in your hands. Engineers can now apply targeted changes to their design and immediately assess timing, aging, and power impact across the entire clock domain. No more wait cycles. No more guesswork. Just fast, SPICE-accurate answers.

Whether you’re implementing last-minute fixes or refining clock balance at signoff, Infinisim’s platform will help you move with agility—without risking margin.

High-Impact Power Optimization

Clock trees account for a significant share of total dynamic power. Infinisim’s advanced optimization engine finds and eliminates hidden inefficiencies by simulating realistic switching activity and analyzing the resulting power distribution.

Using their tools, customers have seen measurable power reductions without degrading performance – especially valuable in designs with tight thermal budgets or aggressive energy targets.

Jitter Risk Detection—Before It’s Too Late

Most signoff flows catch jitter too late. By then, it’s costly—or impossible—to fix. Infinisim’s platform enables early detection of jitter-inducing conditions, whether due to clock path asymmetry, noise coupling, or aging effects. With high-fidelity waveform-level analysis, Infinisim helps design teams catch hidden failures before they make it to tape-out.

Designed for the Entire Clock Domain

Infinisim solutions don’t just optimize individual paths – they analyze and optimize timing behavior across the entire clock domain, including interconnects and complex mesh structures. That means no surprises when your design hits silicon.

About Infinisim

Infinisim is the definitive leader in SoC clock verification. Our technology powers the most advanced semiconductor designs in the world, enabling customers to achieve breakthrough clock performance at the most challenging process nodes—where timing margins are razor-thin and nanometer effects can no longer be ignored.

With SPICE-accurate analysis of timing, aging, and jitter, Infinisim enables designers to detect clock-related failures early, optimize performance, and—most importantly—tighten design margins without excessive guard banding. This allows for significant improvements in power, performance, and area (PPA), all while reducing the risk of silicon re-spins.

Trusted by top semiconductor companies and foundries, Infinisim helps accelerate design schedules, improve product yield and quality, and deliver robust, high-performance SoCs with confidence before tape-out.

Contact Infinisim

DAC registration is open

Also Read:

Infinisim Enables a Path to Greater Profitability and a Competitive Edge

Video EP2: A Detailed Look at the Most Effective Way to Conquer Clock Jitter with Samia Rashid

2025 Outlook with Samia Rashid of Infinisim

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The Siemens Questa plus AI Story Gathers Momentum

The Siemens Questa plus AI Story Gathers Momentum
by Bernard Murphy on 06-19-2025 at 6:00 am
Categories: EDA, Siemens EDA

Questa One plus AI min

I wrote recently about a Siemens pre-announcement at DVCon on their directions in simulation+AI. On May 13th they officially announced a full spectrum of capabilities under the brand Questa One. Abhi Kolpekwar (VP/GM at Siemens EDA) more fully fleshed out the story for me. I asked why Siemens is late to this simulation+AI party. In fairness their first product in this space, Verification IQ, appeared in 2023. For the more complete story he says they have been very conservative, aiming not just to be fully ready but also to build a string of high-profile endorsements. I get it; customers want supplier options in simulation and three options is better than two. If those customers see Questa One measuring up then it is reasonable to assume that Siemens, if late to the party, is surely now making an entrance.

The complete story

Abhi stressed that Questa has undergone an extensive rewrite, first for significant upgrades in performance, and second to unify functional, fault, RTL, gate-level simulation, coverage, acceleration, parallel processing and design/simulation profiling, all through a single install, common user interface and debug. Hence the name – Questa One. This is complemented by Questa One SFV (stimulus free verification, essentially a merge of static and formal methods), Questa One Verification IQ linking Questa One to the earlier released Verification IQ, and Questa One Avery VIP for VIPs and testbench automation.

I’m primarily interested in AI applications through the suite. GenAI plays a role in Property Assist, a method to autogenerate assertions from natural language prompts (I saw a demo of this), Docs assist which I remember from DVCon is intended to autogenerate docs based on current design collateral (perhaps a feature unique to this platform?). We didn’t talk about PSS Assist, Testplan Assist or Code Assist but I can guess that these features help respectively with generating PSS scenarios, mapping from a natural language testplan to executable tests, and RTL code snippet generation (similar intent to CoPilot).

Smart Regression capabilities in ViQ provide the intelligent control of regression ordering and resource utilization we would expect. This will accelerate likely failures in testing, optimize use of the compute grid, and provide regression schedule insight.

Questa One ViQ provides many of the AI-based capabilities in this release. This includes analysis to predict patterns and holes in coverage, provide root cause analysis and suggest solutions. ViQ seems to be well established. For debug, they have early adopter engagements in bad commit prediction, root cause prediction and signature prediction. And in regression navigation they have early adopters in smoke test prediction.

QCX (coverage acceleration) is a capability I would like to understand better. This is listed under predictive AI and appear to be about regression optimization, that is removing tests from the suite when they contribute little to increasing coverage. This is a hot topic and certainly should have a major impact on time to coverage closure. Siemens claim they have seen cases up to 50X faster than for unoptimized suites.

Smart Debug is another hot area and more challenging than it might appear. There is no silver bullet I know of, but rather a collection of methods to attempt to isolate a root cause. Questa One here looks for correlation of failures with immediately preceding commits or design changes and creating failure signatures around similar or repetitive issues. This is a good area for use of AI methods against regression history (using the ViQ regression navigator). Siemens also mentions here a Protocol Assist to track down protocol errors, perhaps based on the Questa One Avery capabilities.

Smart Analysis leverages unsupervised learning to identify coverage holes, present cross-hole analysis to highlight potential weaknesses in the testplan, also to identify pattern correlations against the RTL.

Endorsements and availability

Siemens EDA have gathered a top tier set of endorsements for this product. As Abhi mentioned, they have been running largely in silent mode until they had these in place. Among those they can share so far are the following:

Karima Dridi, Head of Productivity Engineering, Arm says: “As an early adopter of running large EDA workloads using the high-performance Questa One Sim advanced functional simulator, we’ve observed improvements in performance, cost-efficiency, and reduction in regression time on the latest AArch64 architecture.”

Chienlin Huang, senior technical manager of Connectivity Technology Department, MediaTek, notes: “Questa One Property Assist utilizes generative AI to save us weeks of engineering time, and Questa One Regression Navigator predicts which simulation tests are most likely to fail, runs them first, and saves days of regression and debugging time.”

Susheel Tadikonda, vice president of Engineering, Silicon IP at Rambus, adds: “Siemens’ Questa One smart verification solution has improved and streamlined our verification process, enabling us to address new-era data center workloads like generative AI with state-of-the-art silicon IP solutions for PCIe, CXL and HBM interfaces. Leveraging the complete Questa One solution, including simulation, static and formal analysis, and verification IP technologies, brings increased confidence to our customers through comprehensive verification of IP solutions for their SoC and chiplet designs.”

And from Microsoft: “Questa One DFT (QDX) simulation utilizes advanced DFT-centric simulation capabilities to deliver faster performance than existing simulation solutions, slashing our verification time from weeks to days,” said Selim Bilgin, corporate vice president, Silicon Engineering at Microsoft. “In addition to these impressive speed ups, on Microsoft’s Azure Cobalt 100 platform QDX delivers up to 20 percent further performance jump unlocking even greater efficiency for our EDA workloads.”

Altogether, Siemens now looks more interesting in this space. The Questa One smart verification solution will be available in June 2025. You can learn more HERE.

Also Read:

Siemens EDA Outlines Strategic Direction for an AI-Powered, Software-Defined, Silicon-Enabled Future

EDA AI agents will come in three waves and usher us into the next era of electronic design

Safeguard power domain compatibility by finding missing level shifters

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Empyrean at the 2025 Design Automation Conference #62DAC

Empyrean at the 2025 Design Automation Conference #62DAC
by Daniel Nenni on 06-18-2025 at 10:00 am
Categories: EDA, Empyrean, Events

62nd DAC SemiWiki

Empyrean at DAC 2025: Full-Flow AMS/PMIC, SPICE Simulation, and AI-Accelerated Library Characterization

Empyrean returns to DAC 2025, showcasing our most advanced EDA solutions that power next-generation chip designs. This year, we spotlight three critical innovation areas:

AMS & PMIC Design Solutions

Empyrean offers a comprehensive full-flow custom design platform for analog, mixed-signal, and power IC development. Our solution provides:

  • Complete AMS design flow from initial specification to tape-out
  • Support for complex PMIC designs
  • Seamless simulation and debugging across corners and modes using ALPS®, our high-performance circuit simulator
ALPS® – Ultra-Fast, SPICE-Accurate Simulation

Empyrean ALPS® is a high-capacity, parallel SPICE simulator designed for advanced process nodes and large-scale designs. It delivers:

  • Proven SPICE-level accuracy with superior scalability
  • High performance through distributed and multithreaded simulation engines
  • Seamless integration across analog, digital, and RF verification flows
Liberal™ – AI-Accelerated Comprehensive Library Characterization

Empyrean Liberal™ offers a fast, reliable solution for comprehensive library characterization. It supports:

  • Characterization of all standard cells, I/O cells, IPs, and memory instances
  • Cross-library comparison and constraint checking to ensure data consistency
  • AI-accelerated corner predictions
Visit our booth at DAC 2025

Experience Empyrean’s latest technologies in action and connect with our experts.

We look forward to collaborating with you in San Francisco!

Empyrean Technology

Empyrean Technology, founded in 2009, is an EDA and services provider to the global semiconductor industry. The company strives to be the world’s leading EDA provider, delivering a comprehensive front-to-back design flow across all industries.

In the EDA domain, Empyrean Technology offers complete solutions for analog design, complete solutions for memory IC design, complete solutions for RF IC design, digital SoC design solutions, complete solutions for flat panel display design, foundry EDA solutions, and advanced packaging design solutions. Additionally, the company provides EDA-related services, including foundry design enablement services.

EDA and services find applications mainly in the fields of IC design, foundry, and packaging. Empyrean is headquartered in Beijing, with major R&D centers in Nanjing, Chengdu, Shenzhen, Shanghai, Hong Kong, Guangzhou, Beijing E-Town, Xi’an, Wuhan, and Xiamen in China.

The Design Automation Conference (DAC)—often referred to as “Chips to Systems”—is the premier annual event in the field of electronic design automation (EDA). It’s a hybrid technical conference and trade show where industry leaders, researchers, and practitioners converge to explore innovations in semiconductor and electronic system design

 DAC 2025 at a Glance

  • Dates: June 22–25, 2025

  • Location: Moscone West, San Francisco, CA, USA.

  • Host: Organized by ACM‑SIGDA and IEEE‑CEDA.

  • Scale: Around 6,000 attendees, featuring ~100 exhibitors, hundreds of technical papers, engineering tracks, poster sessions, student forums, hackathons, and career development events.

Also Read:

Aniah at the 2025 Design Automation Conference #62DAC

Altair at the 2025 Design Automation Conference #62DAC

Tuple Technologies at the 2025 Design Automation Conference #62DAC

Perforce at the 2025 Design Automation Conference #62DAC

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Aniah at the 2025 Design Automation Conference #62DAC

Aniah at the 2025 Design Automation Conference #62DAC
by Daniel Nenni on 06-18-2025 at 8:00 am
Categories: Aniah, EDA, Events

62nd DAC SemiWiki

For its 3rd DAC, Aniah comes to the show with a special treat for its customer : its new Analog Design Assistant, Amigo, makes analog and mixed-signal design engineers more productive every day. This product complements Aniah’s widely deployed, transistor-level verification solution, OneCheck.

Aniah is an EDA startup founded in 2020 with a mission to make transistor-level formal verification (ERC), accessible for every designer in a continuous integration mode. The focus of the company has been on ease-of-use with no compromise on accuracy and coverage, or scale. Aniah runs ESD analysis on billion-devices SoC in under half an hour.

And because its clients use Virtuoso or Custom Explorer as their everyday design tool, Aniah has massively invested in its integration with advanced schematic annotation that makes debug even more efficient.

Here is, in a nutshell, the key benefits of Aniah OneCheck.

Come to our Booth (1427#) and request a demo of:
  • How to setup and ERC analysis on a SoC in under 20 seconds
  • How OneCheck reduces False Errors by a 100x factor
  • Why Amigo is an instant hit with all analog designers

About Aniah: Aniah is a French company specializing in design assistance and verification software for semiconductors. We bring to the market an innovative solution that guarantees our customers 100% detection of electrical errors in transistors. https://aniah.fr

Also Read:

Aniah and Electrical Rule Checking (ERC) #61DAC

Electrical Rule Checking and Exhaustive Classification of Errors

CEO Interview: Vincent Bligny of Aniah

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Arteris Expands Their Multi-Die Support

Arteris Expands Their Multi-Die Support
by Bernard Murphy on 06-18-2025 at 6:00 am
Categories: 3D IC, AI, Arteris, IP

multi die use cases min

I am tracking the shift to multi-die design, so it’s good to see Arteris extend their NoC expertise, connecting chiplets across an interposer. After all, network connectivity needs don’t stop at the boundaries of chiplets. A multi-die package is at a logical level just a scaled-up SoC for which you still need traffic routing and management between those subsystem chiplets. Arteris just took the covers off their Multi-Die Solution response: complete coherent and non-coherent connectivity support, on-chiplet and between chiplets, Magillem Connectivity for system partitioning and Magillem Registers for memory map integration between chiplets. This is what I wanted to see.

The Market

Arteris (Ashley Stevens, Director PM at Arteris, and Andy Nightingale, VP PM) shared some interesting stats on growth in the global chiplets market, estimated at between $107B and $373B by 2033 with compound annual growth rates of between 76% and 95%. It should be obvious from these numbers that extrapolating from current few $B numbers involves a good deal of guess work, but what is clear is that the chiplet market is anticipated to grow fast. Andy has seen numbers suggesting the current $ volume is around 2% of the conventional semiconductor volume, tiny today but lots of headroom to grow.

Clearly the drivers for this growth will be the big semi/system houses, the hyperscalers with their in-house development (many-core servers, AI servers, advanced networking, storage, etc), automotive/transportation, wireless infrastructure, even maybe robotics. Each connecting multiple subsystems through a network in a multi-die package. I’m guessing not edge consumer applications anytime soon, but who knows in these fast-moving times.

Connectivity

Again, any multi-die design is just a giant design which happens to be partitioned into chiplets, with such traffic communication between chiplets as is demanded by the application. An example might be a many-core server split across say 4 chiplets, each chiplet hosting perhaps 32 CPUs on a mesh network. That mesh communication must continue up to the inter-chiplet level, crossing from chiplet to chiplet through connections on the interposer. The mechanism to cross between chiplets requires some special buffering to accommodate inter-die transitions but otherwise can continue the same logical mesh connectivity.

Arteris has been the leading commercial provider for on-chip non-coherent and coherent connectivity IP for many years now and have built a very respectable list of customers across all major markets. Those same product lines (FlexNoC for non-coherent and Ncore for coherent) have been extended to provide multi-die support. The technology offers significant flexibility in inter-chiplet connections, supporting multiple options, from point to point, to mesh, even IO hub.

These NoCs are proven against industry standards for inter-die communication, especially the UCIe interfaces from Cadence and Synopsys. Arteris add gateway interface units (GIUs) to front-end network communication prior to UCIe.

Partitioning and multi-die memory map

Ashley and Andy made a big deal about the role the Magillem Connectivity and Magillem Register tools play in the development flow and at first I was confused. Surely all or most of the chiplets are pre-defined so the partitioning is already fixed? However Arteris are already seeing customers want to do something different. They’ll start with a prior design and want to scale that out by replication of big functional blocks into one mega design (in RTL), ignoring manufacturing constraints. They use this to experiment to find an optimum partitioning (throughput, etc.) before implementing the partitioning. Which on reflection makes complete sense today. Today’s commercial chiplet market is very nascent and much of the value in chip makers designs is proprietary. Of course many of their chiplets will be built on their own design IP, replicated as needed in their scale out architectures.

The re-partitioning step I remember from my previous life. Sounds simple in principle but it proves to be amazingly fiddly and full of potholes if you aren’t careful. The Magillem Connectivity solution has been in production for a long time and provides exactly this capability.

Need for the Magillem Register solution is immediately obvious. A multi-die implementation must combine multiple chiplets, each with its own register interfaces and memory map, consolidating into one big memory map for the full multi-die system. This isn’t just a question of HW/SW interface documentation, test and other collateral. The NoC itself is configured by the memory offsets determined for each chiplet, intimately tied with the ultimate memory map. These hardware and software factors can and should be managed together.

It’s good to see these connectivity and register capabilities fold so neatly into multi-die design!

Takeaway

I was expecting/hoping for this advance and now it’s here. Arteris are already claiming success in partnering with Rebellions, Tenstorrent, and Menta as early adopters of their multi-die non-coherent solution. They are also saying that both coherent and non-coherent solutions are now available.

You can read more HERE.

Also Read:

How Arteris is Revolutionizing SoC Design with Smart NoC IP

Podcast EP277: How Arteris FlexGen Smart NoC IP Democratizes Advanced Chip Design with Rick Bye

Is Arteris Poised to Enable Next Generation System Design?

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Agile Analog at the 2025 Design Automation Conference #26DAC

Agile Analog at the 2025 Design Automation Conference #26DAC
by Daniel Nenni on 06-17-2025 at 10:00 am
Categories: Agile Analog, IP

62nd DAC SemiWiki

See Agile Analog at DAC in the EE Times Chiplet Pavilion (Booth 2308, Level 2)

Learn how to enhance security and performance with our customizable analog IP

Agile Analog is delighted to announce that we will be back exhibiting at the Design Automation Conference (DAC). Come join us in the EE Times Chiplet Pavilion (booth 2308) to learn how our innovative, customizable analog IP solutions are addressing the demands of chip design across a vast range of domains.

Visitors will have the opportunity to dive deep into our expanding portfolio of analog IP, covering essential areas including data conversion, power management, IC monitoring, security and always-on IP. We will be explaining how our IP can empower your designs with optimized performance and efficiency, whether you are looking for precision ADCs, efficient LDOs or robust on-chip PVT monitoring capabilities.

Of particular interest is our anti-tamper security IP. In an ever increasingly connected world protecting sensitive data is critical. Our anti-tamper solutions are designed to provide robust, on-chip security against a wide variety of physical and non-physical attacks, including voltage and clock attacks, safeguarding your devices from malicious intrusions. We will be discussing how our anti-tamper IP can seamlessly integrate with existing Root of Trust (RoT) solutions, enhancing their capabilities to help you meet the latest security standards. This integration offers formidable protection, with a multi-layered approach to chip security that is both flexible and powerful.

What truly sets Agile Analog apart is our groundbreaking Composa™ technology. Composa enables us to automatically generate and customize our analog IP for any process node from any foundry. We have proven this methodology across our IP portfolio on nodes from 180nm to 3nm. This means that we can quickly deliver highly optimized IP that precisely matches your exact specifications, whilst ensuring the best possible Power, Performance and Area (PPA) for your application. No more porting or costly and time-consuming analog re-engineering when moving to a new process or foundry. This unparalleled flexibility extends to our anti-tamper IP as well, allowing for tailored security solutions, delivered fast, regardless of your chosen process node.

We invite attendees to stop by to see us in the EE Times Chiplet Pavilion (booth 2308) at DAC. Our experts will be on hand to discuss your specific design challenges and demonstrate how Agile Analog’s customizable multi-process IP, especially our advanced anti-tamper solutions, can help you achieve your design goals and stay ahead in a competitive landscape. We look forward to seeing you there!

To arrange a meeting to talk with the Agile Analog team at DAC please email info@agileanalog.com

Find out more about Agile Analog at www.agileanalog.com

DAC registration is open.

Also Read:

CEO Interview with Krishna Anne of Agile Analog

Overcoming obstacles with mixed-signal and analog design integration

Podcast EP241: A Look at Agile Analog IP with Chris Morrison

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Altair at the 2025 Design Automation Conference #62DAC

Altair at the 2025 Design Automation Conference #62DAC
by Daniel Nenni on 06-17-2025 at 8:00 am
Categories: 3D IC, Altair, Chiplet, EDA, Events

62nd DAC SemiWiki

Design Perfection from Concept to Tape-out Booth #1617 at DAC25 – June 23-25, 2025

Join us to learn how Altair’s world-class solutions are powering perfect semiconductor design.

The semiconductor industry operates at an accelerated pace, in which every second saved is a competitive advantage. You must rely on solutions that complement each other at every step in the semiconductor design process to beat others to market.

Altair’s solutions empower organizations to design perfection from concept to tapeout. From silicon debugging tools for integrated circuit (IC) designs to multiphysics analysis of 3D IC and chiplet design simulations, Altair offers the complete solutions set. With the fastest high-throughput workload manager available and an advanced workflow analysis tool, designers can trust Altair with every challenge.

Speak with an expert at DAC

Book meeting

Live Presentations

Transform the semiconductor industry

Design perfection from the start with advanced silicon debugging, rapid 3D IC electrothermal-mechanical simulations, and the industry’s only on-demand digital simulator for semiconductor electronic functional verification. Avoid costly dependencies and optimize infrastructure utilization with HPC workload and workflow optimization and bring reliable designs to market faster.

Join us for live presentations throughout the conference featuring industry leaders and technology experts.

 

11:30 am – 12:00 pm | Altair SimLab: Integrated Environment for Multiphysics Modeling and AI-Driven Reliability Prediction in 3D IC Systems

Iyad Rayane, Senior Technical Specialist ESD, Altair

This solution provides a comprehensive environment for modeling and pre/post-processing of 3D Integrated Circuit (3D IC) structures, enabling robust multiphysics analysis including thermal, mechanical, and electrical domains. It interfaces with advanced AI-driven physics capabilities to predict system lifespan rapidly and accurately, significantly reducing simulation runtime. Additionally, the environment supports thermal-aware chiplet floorplanning, optimizing thermal dissipation at the system level to enhance reliability and performance. This integrated approach facilitates early design exploration and informed decision-making for next-generation heterogeneous 3D ICs.

01:00 pm – 01:30 pm | Altair NavOps: Bursting Workload demand to the cloud!

Yohan Bouvron, Support Engineer, Enterprise Computing, Altair

Engineers want as little wait time as possible to run their workloads and management wants the highest possible utilization of the systems. Altair’s NavOps + Accelerator can provide an optimal solution for both.

02:00 pm – 02:30 pm | FlowTracer Refresh – A new era of vendor-agnostic design automation platform

Dee Lin, Lead Principal Solution Architect, Altiar

Since its inception, FlowTracer has become a popular commercial ASIC/SoC design automation platform among the top semiconductor companies. This year, Altair is launching 2025 release with major GUI and feature-rich modernization. We will go through these major features and improvements in this presentation.

DAC registration is open.

About Altair

Altair is a global leader in computational intelligence that provides software and cloud solutions in simulation, high-performance computing, data analytics and AI. Altair enables organizations across all industries to compete more effectively and drive smarter decisions in an increasingly connected world – all while creating a greener, more sustainable future. To learn more, please visit https://www.altair.com.

Also Read:

Tuple Technologies at the 2025 Design Automation Conference #62DAC

Perforce at the 2025 Design Automation Conference #62DAC

Silvaco at the 2025 Design Automation Conference #62DAC

Silicon Creations at the 2025 Design Automation Conference #62DAC

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Tuple Technologies at the 2025 Design Automation Conference #62DAC

Tuple Technologies at the 2025 Design Automation Conference #62DAC
by Daniel Nenni on 06-17-2025 at 6:00 am
Categories: Semiconductor Services, Tuple Technologies

62nd DAC SemiWiki

Tuple Technologies delivers Tropos, a platform automating IT infrastructure across Cloud, Hybrid or On-prem and DevSecOps for semiconductor IC, FPGA, and system design, optimizing costs and cybersecurity.

Attendees who step into the Tuple Technologies booth during DAC (Booth #1237) will see demonstrations of its Tropos Platform and launch of a new product, Omni, that empowers Semiconductor design teams to optimize their budgets to run CPU & GPU workloads.

Tuple Technologies has developed a specialized platform called Tropos, designed specifically to address the needs of semiconductor designers working on integrated circuits (IC), field-programmable gate arrays (FPGA), and system design workloads. The Tropos platform is tailored to optimize semiconductor development processes through automation, cost efficiency, and robust infrastructure management. Below are the key features and solutions provided by Tropos for the semiconductor industry:

  1. Infrastructure-as-Code (IaC) for Customized Setup:

    • Tropos uses IaC techniques to provide out-of-the-box infrastructure setups tailored for IC, FPGA, and system development needs. This allows semiconductor startups and designers to quickly establish optimized environments without extensive manual configuration.

  2. Automation for Workload Management:

    • The platform automates the spawning of IC workload jobs to cost-optimized compute resources across major cloud providers like AWS, GCP and Azure. This ensures efficient resource allocation, reducing operational costs while maintaining performance for compute-intensive semiconductor design tasks.

  3. ECAD Administration and License Management:

    • Tropos includes tools for Electronic Computer-Aided Design (ECAD) license administration, streamlining the management of design software critical to semiconductor development. It also provides license usage analytics, helping companies optimize their software licensing costs and avoid vendor lock-in with CAD tools.

  4. Multi-Cloud Cost Optimization:

    • The platform is designed to optimize semiconductor workloads across multiple cloud environments, ensuring cost efficiency by leveraging the most suitable cloud resources for specific tasks. This is particularly valuable for semiconductor companies managing complex, resource-heavy design processes.

  5. Cybersecurity for Semiconductor Workloads:

    • Tropos incorporates cybersecurity measures to protect sensitive semiconductor design data, ensuring compliance and safeguarding intellectual property during development and deployment. This is critical for semiconductor companies handling proprietary designs.

  6. IT Operations and DevSecOps:

    • Tuple provides comprehensive IT operations (ITOps) and DevSecOps solutions tailored for semiconductor startups. These include Cloud, On-prem or Hybrid environments, ensuring seamless integration of development pipelines with secure, automated workflows.

  7. Scalable and Affordable Solutions:

    • Built on an open-source stack, Tropos is designed to be both scalable and cost-effective, making it accessible for small to medium-sized semiconductor companies. The platform automates cloud infrastructure provisioning (Platform-as-a-Service) and management, simplifying the configuration and operation of cloud resources for semiconductor workloads.

Semiwiki readers are invited to arrange demonstrations or private meetings by sending email to info@tupletechnologies.net or stopping by Booth #1237

DAC Registration is Open

About Tuple Technologies

Tuple Technologies, founded in 2017, is a cloud automation and managed services provider headquartered in New York with offices in New Jersey and San Francisco. The company specializes in delivering solutions, with a strong focus on cloud migration, cybersecurity, DevSecOps, and IT operations, particularly for small to medium-sized businesses in industries like Semiconductors. Tuple employs a team of AWS-certified engineers and has products and services offering a suite of tools built on open-source stacks to ensure affordability and scalability.

Tuple Technologies emphasizes its expertise in supporting semiconductor startups by providing infrastructure setups that avoid the complexities and gaps often found in traditional CAD vendor solutions. The company’s participation in industry events like the Design Automation Conference (DAC) in 2025 highlights its commitment to engaging with the semiconductor community and showcasing its Tropos platform.

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