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If the thought of a silicon respin keeps you awake at night, you’re not alone. Re-fabricating a chip can cost tens of millions of dollars. An unplanned respin also risks a delay in getting a product to market, which adds tremendous costs in terms of lost business.
Undoubtedly, adding to your sleep loss is the recent rise in respins. What’s causing this increase of failures when the design gets to silicon? As electronics products add increasing numbers of features and faster performance, things have gotten complicated. A patchwork of silicon IP, 100s of millions or billions of transistors, and the challenge of getting analog and digital to play in the same sandbox, has resulted in Byzantine sprawls across the die. Meanwhile, the growth of electronic components needed in AI solutions, automotive, 5G connectivity, gaming, medical IoT, and more continues to mushroom. For instance, contrast the abundance of electronics in today’s self-driving cars with your uncle’s Buick.
Complexity gone wild
As they race to satisfy this demand, companies are trying to fit all circuitry on the same substrate or on a single technology node. The latest process technologies plus cost-effective innovations in transistors, such as gate-all-around (GAA), further enable engineers to pack previously unfathomable numbers of transistors onto a die. Apple’s ARM-based dual-die M2 Ultra SoC, which is fabricated using TSMC’s 5 nm semiconductor manufacturing process, packs 134 billion transistors. And TSMC is charting a course for manufacturing one-trillion-transistor chips in 1nm.
This kind of complexity can cause everything from power issues to analog circuitry failing or falling out of operable range. And chipmakers are pushing into smaller and smaller nodes, which creates more challenges to success in manufacturing. For example, “The data suggest smaller node size and larger gate count are a contributing factor to power-related respins,” according to a recent article on Siliconengineering.com. “That means power could be the number one cause of respins for the biggest designs at the latest nodes, and that is before adding in the failures that are not recorded as ‘power-related’.”
Compounding the challenges of finding and fixing bugs or functional defects early in a design is the shortage of experienced designers. Complex SoC is a complex endeavor, which requires, for example, the ability to interpret design intentions from the schematics and understand arcane topics like transistor matching, noise tolerance, and parasitics.
Advanced device modeling to the rescue
So, how can you get your sleep back and avoid costly respins? Join a comprehensive webinar focused on enhancing device reliability and preventing silicon respins through innovative noise and binning modeling technologies. Keysight Technology engineers will give you deep dives into two combinations of tools and techniques that will reduce your chances of a chip failing in silicon.
The first speaker covers enhancing reliability with accurate noise measurement and modeling. Precise noise data in device modeling is critical to design and manufacturing success. In the massively complex devices we just described, accurately accounting for noise is essential for ensuring reliability. You will learn how noise data across the wafer can serve as an early indicator of device performance, particularly in low-signal applications such as communications circuits, quantum computing, and image processing. Keysight will walk you through using the company’s Advanced Low-Frequency Noise Analysis (ALFNA). And you will get a first-hand look at how easy it is to use the system to measure and analyze 1/f and Random Telegraph Noise from DC to 100MHz, enabling you to refine designs and boost overall reliability. Key takeaways include:
The impact of precise noise modeling on device reliability and performance
How Keysight’s ALFNA system can improve noise data integration and analysis
Next, you’ll learn how to streamline your device modeling workflow to help you avoid respins with automated binning model extraction. As devices become smaller and more complex, traditional global models often fall short in accuracy. You’ll see how binning models offer improved precision—which is critical to the success of your complex designs—and how you can streamline the difficult and time-consuming process of developing them. A Keysight engineer will conduct a live demonstration of an automated extraction flow that enhances binning model efficiency. This will include showing you how Keysight automation techniques and fast QA methods simplify and accelerate the binning process. Key takeaways include:
Techniques for automating binning model extraction to avoid costly respins and enhance modeling efficiency
Strategies to streamline the QA process and accelerate model development
So, if rising device complexity and shrinking process nodes make you anxious about functional flaws or bugs getting away and causing re-spins, this webinar will hopefully lower your stress levels. The advanced device modeling tools and techniques covered by Keysight experts are not only easy-to-use but can also significantly improve device reliability and prevent costly design errors.
Many of you are already familiar with Silicon Catalyst and the value it brings to semiconductor startups, the industry and the electronics industry at large. Silicon Catalyst is an organization that supports early-stage semiconductor startups with an ecosystem that provides tools and resources needed to design, create, and market semiconductor solutions. It is the only incubator + accelerator focused on the Global Semiconductor Industry and operates with the motto “It’s about what’s next.”
Overall Tech Trends: Inspiration for Quantum and beyond
In keeping up with its motto, Silicon Catalyst invited Dr. Mena Issler from McKinsey and Company to talk about Frontier Technology Trends, at its recent Q3 Advisor & Investor meeting. Mena is an Associate Partner at McKinsey & Company and is one of the authors of “
Some Highlights from Mena’s talk
In 2023, technology equity investments fell by 30-40% to around $570 billion due to rising financing costs and cautious growth outlooks. Despite this, investors are focusing on technologies with high revenue potential, recognizing the long-term value in diversifying investments across multiple tech trends.
Generative AI (gen AI) has emerged as a standout trend, seeing a sevenfold increase in investments since 2022. Its capabilities have expanded dramatically, with large language models (LLMs) now able to process up to two million tokens, powering advancements in text, image, video, and audio generation. Gen AI is being integrated into enterprise tools for diverse applications such as customer service, advertising, and drug discovery, fueling a broader AI revolution and spurring innovations in applied AI and machine learning.
Gen AI’s rapid evolution is also driving advancements in robotics, with AI-powered robots becoming more capable and widely deployed across industries. Robotics was added to McKinsey’s 2023 tech trend analysis, reflecting its growing significance as AI technologies improve and expand robotic capabilities, making automation smarter and more efficient.
Job postings for tech-related roles declined by 26% in 2023, largely due to layoffs in the sector. However, trends like Gen AI continued to see demand for talent, with overall tech job postings up 8% from 2021, indicating long-term growth potential. Interest and innovation across 15 key tech trends remain strong, with AI and renewable energy leading the charge in Investment growth and overall investment, respectively.
This is all food for thought as we start to build and prepare for quantum and semiconductor’s future. To learn more about the latest tech trends, check out the McKinsey report.
Quantum Technologies
With the bulk of technology news these days centered around Artificial Intelligence (AI), it is easy to lose sight of other fast advancing technologies and trends. One such space is the field of quantum technologies. Silicon Catalyst stays on top of things through various means with the incubator’s annual Silicon Startups Contest conducted in partnership with Arm – being one. The overall top winner of the 2023 Contest, conducted by Silicon Catalyst in partnership with Arm, is Equal1, a quantum computing company from Ireland. Over the last two quarters, Silicon Catalyst has received a flurry of quantum space applicants to its incubator program. A couple of recent applicants are currently going through the review process for consideration for admittance into the incubator.
Quantum Computing utilizes quantum properties to process information and perform simulations, offering exponential performance improvements over classical computers in specific applications.
Quantum Communication involves the secure transfer of quantum information over distances, using optical fiber or satellites, with potential to ensure secure communication even against quantum computing attacks. Quantum Key Distribution (QKD) is a secure communication method using quantum technology to protect data against potential attacks by quantum computers.
Quantum Sensing enables ultra-sensitive measurements of physical quantities, surpassing classical sensors in accuracy, with applications in navigation, bio-imaging, and semiconductor manufacturing.
Recent Developments
Recent developments in quantum technologies include significant progress in error correction, full-stack integration, information security, and partnerships. Harvard, MIT, QuEra, and NIST demonstrated algorithms on 48 logical units with error rates below 0.5%, and Microsoft and Quantinuum achieved four reliable qubits with an error rate below 0.01%. IBM and Google also advanced in logical qubit storage and error reduction. These steps push the field toward higher-quality, scalable qubits.
In cybersecurity, companies are strengthening encryption systems to counter potential quantum threats, particularly “harvest now, decrypt later” attacks. Postquantum cryptography is being deployed as a proactive defense.
Bridging Quantum Technology and Real-world
Start-up partnerships with conventional enterprises are also expanding, such as Rolls-Royce’s collaboration with Riverlane to develop quantum algorithms for material discovery in hostile environments. Such partnerships aim to bridge the gap between quantum technology and real-world applications.
Quantum Ecosystem Required to Accelerate Market Growth
While investments into quantum technology startups, the number of such startups and the total governmental investments toward quantum all increased year-on-year, there are still many challenges to overcome. An elaborate and strong ecosystem is needed to catalyze growth and market adoption of quantum technologies. The chart from McKinsey & Company, below identifies the various partner categories required of such a quantum ecosystem.
Summary
For any entrepreneur with a groundbreaking idea in semiconductor technology, Silicon Catalyst offers the ideal environment to turn that idea into reality. Through its extensive network of partners, advisors, mentors, and industry resources, it provides startups with a unique advantage in navigating the complexities of semiconductor development. By joining Silicon Catalyst, startups not only gain access to essential tools and expertise but also become part of a global network that is driving the future of technology.
As for what is next, Silicon Catalyst is looking to build out an ecosystem of design tools, refrigeration systems and cryostat equipment to support and nurture early stage startups in the quantum space.
To learn more, visit SiliconCatalyst.com. You can meet Silicon Catalyst Partners at the Quantum to Business (Q2B) conference, December 10-12, 2024 at the Santa Clara Convention Center. Those interested in further information about Silicon Catalyst-Quantum activity, please send a note to quantum@sicatalyst.com to receive a special Q2B conference registration discount from Silicon Catalyst.
Silicon Carbide (SiC) is the superhero EV converters need, boosting efficiency, shrinking component sizes, and letting your car charge faster while handling heat like a pro. Even Tesla’s like, “Yep, we’re using it,” because who doesn’t want more range and less sweating under the hood?
Get ready for an electric ride in 2024! Global EV sales are set to zoom to between 15-17.5 million units, a 27% surge over last year. Leading the pack, China’s cranking out 9.1 million EVs—nearly 52% of all car sales—thanks to their battery tech wizardry and slick charging infrastructure. Europe’s sparking up too, with 3.9 million EVs projected, as the region shifts from government push to consumer pull. North America’s jumping in with 2.2 million units sold 1, expanding its charging grid and adding more SUVs and trucks to the mix. Buckle up—it’s going to be electrifying!
But, with all the excitement about clean driving and cutting emissions, there’s still one thing holding everyone back—range anxiety. Yes, the dreaded fear that your battery will fizzle out right when you’re miles from a charging station. Don’t worry, though; the solution isn’t about making bigger batteries or building more chargers (although that helps); it’s actually all about… a meteorite and a French chemist who thought he discovered a huge diamond deposit. Yes you heard me well: a meteorite 2… We are not in a movie but in the real world and the hero is called SiC.
EVs and SiC: A Love Story Who started in a Galaxy far, far away
Meet silicon carbide (SiC), a material that’s older than our solar system 3, literally. It’s not just space rock bling; it’s also a superhero when it comes to semiconductors. This stuff has been quietly sitting in the background while we were all obsessed with silicon devices, but now it’s finally stepping into the limelight. And SiC couldn’t have picked a better co-star than EVs. Together, they make the perfect power couple—like electric peanut butter and jelly.
So, why is SiC such a game-changer? Unlike widespread silicon, which is kind of basic at this point, SiC can handle electrical fields up to ten times stronger. That means it’s ideal for handling the high-powered energy demands of EVs. Think of it as silicon’s stronger, more resilient cousin. Plus, SiC doesn’t break a sweat when it comes to heat dissipation or power conduction. It’s like the superhero who shows up to save the day and doesn’t even get its cape dirty.
Faster, Lighter, Stronger: SiC to the Rescue!
By plugging SiC into an EV’s inverter, you can actually squeeze up to 10% more range 4 out of that battery. You know what that means: fewer panicked searches for charging stations! SiC is also a big fan of going small. It allows engineers to shrink the size and weight of power systems, which then results in a lighter car. A lighter EV means a longer driving range and, let’s be honest, nobody likes a chunky car. So, SiC trims the EV down, making it leaner and more efficient on the road.
Representation of a smaller and sleeker charger using SiC
But wait, there’s more! SiC also speeds up charging, allowing for that sweet switch from 400V to 800V battery systems. Faster charging means more time zooming around and less time staring at a charger while sipping overpriced coffee. Silicon Carbide (SiC) in fast chargers is like giving your EV a turbocharged energy drink! It boosts efficiency by reducing power loss, meaning more juice goes to your car instead of heating up the charger. SiC has many aces up its sleeve, enabling higher voltage operation that chops down charging times and making your EV ready to go in record time. And the bonus? It lets chargers be smaller and sleeker, fitting more power in a compact package.
Sure, SiC parts are pricier than regular silicon, but the trade-off is worth it: fewer cooling headaches, smaller components, and chargers that are both lighter and more powerful.
In the world of EV fast charging, where every minute counts, SiC technology is the ultimate power move. When you are charging up for a road trip, SiC makes sure your charger runs faster, cooler, and smarter—because nobody’s got time to wait around when there’s a road ahead! So yes, SiC is basically EV magic dust.
EV Converters: SiC steals the Show
Not only is SiC great at pumping miles fast into the battery, but it’s also the MVP when it comes to take those miles out though the power converters 5—the unsung heroes that turn battery juice (DC) into motor power (AC), giving them superpowers compared to boring old silicon (Si). Why? Because SiC is the overachiever in the classroom—it’s more efficient, tougher, and just plain cooler.
Tesla is the first high-class car manufacturer to integrate a full SiC power module, in its Model 3 (Yole Group)
First off, SiC is great at making sure your EV’s battery power actually gets to the motor, instead of being wasted as heat. This means more range, which every EV driver loves. Plus, the magic of SiC is that you can shrink the inverters down because power losses are lower, and devices are smaller than IGBT, allowing for more compact power converters, saving EV weight. Think of it as putting your car on a sleek, tech-savvy diet!
SiC can also handle higher temperatures without throwing a tantrum, which means your EV doesn’t need a complicated cooling system. It’s like having a car that doesn’t sweat the small stuff—literally. This makes everything simpler, cheaper, and more reliable.
Tesla got the memo way back in 2018 when they slapped SiC into the converter of their Model 3, and since then, the EV industry has been on board. By 2033, SiC MOSFETs are expected to dominate the EV inverter market 6. Prepare for a world where “SiC” becomes as well-known as “Wi-Fi”!
Soitec’s SmartSiC™: The Shiny New Superstar in Town
While SiC is amazing, Soitec’s SmartSiC™ is like SiC with a PhD. Soitec didn’t just take SiC and slap it into EVs; they gave it a makeover, making SiC still more powerful and skillful. Their SmartSiC™ substrate uses ten times less material than regular SiC, which is great news because SiC isn’t exactly lying around in abundance. But here’s the kicker: SmartSiC™ boosts performance by over 20%. So, less material, better performance—it’s like upgrading from dial-up internet to fiber optics, but for your car.
SmartSiC™ also plays a big role in the sustainability game. For every million wafers produced, it saves 40,000 tons of CO2 emissions 7. That’s like planting a tree every time you roll out a batch (25 wafers) of SmartSiC chips. Using SmartSiC™ equals fewer emissions, and higher efficiency. That’s more than win-win!
The Future of EVs and SiC: Saving the Planet, One Charge at a Time
As EVs continue their meteoric rise, SiC is going to be their trusty sidekick. And with innovations like Soitec’s SmartSiC™, we’re not just talking about more efficient EVs; we’re talking about a greener, more sustainable planet. SiC and SmartSiC™ are poised to revolutionize the EV industry, with longer ranges, faster charging, and lighter cars all in the cards.
In the race to decarbonize, SiC might just be the little bit of stardust we need to keep us on track. So, next time you plug in your EV, just remember: it’s powered by stars and some pretty smart engineering. And if you’re lucky, maybe Soitec’s SmartSiC™ is behind the wheel, giving your car a boost and saving the world one charge at a time.
Sources:
1 Canalys – Global EV market forecasted to reach 17.5 million units with solid growth of 27% in 2024 2 Wikipedia – Moissanite 3 Jim Kelly – The Astrophysical Nature of Silicon Carbide 4 Frost & Sullivan – The transition of Electric Mobility from 400V to 800V Architecture – An Inevitable move towards WBG semiconductors. 5 Electronic Office Systems – Are all EVs equipped with an on-board AC/DC Converter, or does this depend on the vehicle model? 6 IDTechEx – Power Electronics for Electric Vehicles 2023-2033: Technologies, Markets, and Forecasts 7 Medium – Vehicles of The Future: Emmanuel Sabonnadiere Of Soitec On The Leading Edge Technologies That Are Making Cars & Trucks Smarter, Safer, and More Sustainable
At the 2024 TSMC OIP Ecosystem Forum, one of the technical talks by TSMC focused on maximizing 3DIC design productivity and rightfully so. With rapid advancements in semiconductor technology, 3DICs have become the next frontier in improving chip performance, energy efficiency, and density. TSMC’s focus on streamlining the design process for these cutting-edge solutions has been critical, and 3DBlox is central to this mission. 3DBlox is an innovative framework inclusive of a standardized design language, introduced by TSMC aimed at addressing the complexities of 3D integrated circuit (3DIC) design. The following is a synthesis of that talk, delivered by Jim Chang, Deputy Director at TSMC for the 3DIC Methodology Group.
Progress from 2022 to 2023: Laying the Foundations for 3DBlox
In 2022, TSMC began exploring how to represent their 3DFabric offerings, particularly CoWoS (Chip-on-Wafer-on-Substrate) and INFO (Integrated Fan-Out), which are critical technologies for 3DIC. CoWoS integrates chips using a silicon interposer, while INFO uses RDL (Redistribution Layer) interposers. TSMC combined these approaches to create CoWoS-R, replacing the silicon interposer with RDL technology, and CoWoS-L, which integrates local silicon interconnects.
With these building blocks in place, TSMC realized that they needed a systematic way to represent their increasingly complex technology offerings. This led to the creation of 3DBlox, which provided a standard structure for representing all possible configurations of TSMC’s 3DFabric technologies. By focusing on three key elements—chiplets, chiplet interfaces, and the connections among interfaces—TSMC was able to efficiently model a wide range of 3DIC configurations.
By 2023, TSMC had honed in on chiplet reuse and design feasibility, introducing a top-down methodology for early design exploration. This methodology allowed TSMC and its customers to conduct early electrical and thermal analysis, even before having all the design details. Through a system that allowed for chiplets to be mirrored, rotated, or flipped while maintaining a master list of chiplet information, TSMC developed a streamlined approach for design rule checking across multiple chiplets.
Innovations in 2024: Conquering Complexity with 3DBlox
By 2024, TSMC faced the growing complexity of 3DIC systems and devised new strategies to address it. The key innovation was breaking down the 3D design challenge into more manageable 2D problems, focusing on the Bus, TSVs (Through-Silicon Vias), and PG (Power/Ground) structures. These elements, once positioned during the 3D floorplanning stage, were transformed into two-dimensional issues, leveraging established 2D design solutions to simplify the overall process.
Key Technology Developments in 2024
TSMC’s focus on maximizing 3DIC design productivity in 2024 revolved around five major areas of development: design planning, implementation, analysis, physical verification, and substrate routing.
Design Planning: Managing Electrical and Physical Constraints
In 3DIC systems, placing the Bus, TSVs, and PG structures requires careful attention to both electrical and physical constraints, especially Electromigration and IR (EMIR) constraints. Power delivery across dies must be precise, with the PG structure sustaining the necessary power while conserving physical resources for other design elements.
One of TSMC’s key innovations was converting individual TSV entities into density values, allowing them to be modeled numerically. By using AI-driven engines like Cadence Cerebrus Intelligent Chip Explorer and Synopsys DSO.ai, TSMC was able to explore the solution space and backward-map the best solutions for bus, TSV, and PG structures. This method allowed designers to choose the best tradeoffs for their specific designs.
Additionally, chip-package co-design was emphasized in 2024. TSMC collaborated with key customers to address the challenges of coordinating between the chip and package teams, which previously operated independently. By utilizing 3DBlox’s common object format and common constraints, teams could collaborate more efficiently, settling design constraints earlier in the process, even before Tech files were available.
Implementation: Enhancing Reuse and Hierarchical Design
As customers pushed for increased chiplet reuse, TSMC developed hierarchical solutions within the 3DBlox language to support growing 3DIC designs. With the increasing number of alignment marks required to align multiple chiplets, TSMC worked closely with EDA partners to identify the four primary types of alignment markers and automate their insertion in the place-and-route flow.
Analysis: Addressing Multi-Physics Interactions
Multi-physics interactions, particularly related to thermal issues, have become more prominent in 3DIC design. TSMC recognized that thermal issues are more pronounced in 3DIC than in traditional 2D designs due to stronger coupling effects between different physical engines. To address this, TSMC developed a common database that allows different engines to interact and converge based on pre-defined criteria, enabling efficient exploration of the design space.
One of the critical analysis tools introduced in 2024 was warpage analysis, crucial as the size of 3DIC fabric grows. TSMC developed the Mech Tech file, defining the necessary information for industry partners to facilitate stress simulation, addressing a gap in warpage solutions within the semiconductor industry.
Physical Verification: Ensuring Integrity in 3DIC Designs
TSMC tackled the antenna effect, a manufacturing issue where metal may accumulate plasma charges that can penetrate gate oxides via TSVs and bumps. By collaborating with EDA partners, TSMC created a design rule checking (DRC) deck that models and captures the antenna effect, ensuring it can be accounted for during the design process.
In 2024, TSMC also introduced enhancements in layout vs. schematic (LVS) verification for 3DIC systems. Previously, LVS decks assumed a one-top-die, one-bottom-die configuration. However, 3DBlox’s new automated generation tools allow for any configuration to be accurately verified, supporting more complex multi-die designs.
Substrate Routing: Tackling the Growing Complexity
As 3DIC integration grows in scale, so does the complexity of substrate routing. Substrate design has traditionally been a manual process. The growing size of substrates, combined with the intricate requirements of modern 3DIC designs, necessitated new innovations in this space.
TSMC’s work on Interposer Substrate Tech file formats began three years ago, and by 2024, they were able to model highly complex structures, such as the inclusion of tear drops in the model. This advancement offers a more accurate and detailed representation of substrates, crucial for the larger and more intricate designs emerging in the 3DIC space. TSMC worked with their OSAT partners through the 3DFabric Alliance to support this format.
Summary: 3DBlox – Paving the Way for 3DIC Innovation
TSMC’s 3DBlox framework has proven to be a crucial step in managing the complexity and scale of 3DIC design. From early exploration and design feasibility in 2023 to breakthroughs in 2024 across design planning, implementation, analysis, physical verification, and substrate routing, TSMC’s innovations are paving the way for more efficient and scalable 3DIC solutions. As the industry moves toward even more advanced 3D integration, the 3DBlox committee announced plans to make the 3DBlox standard publicly available through IEEE. 3DBlox will continue to play a vital role in enabling designers to meet the increasing demands of semiconductor technology for years to come.
– SPIE Photomask -all about High NA and bigger masks
– High NA will ramp very fast & is ramping fast – two already at Intel
– Doubling size of photomask will offset High NA exposure size problem
– Assembling litho tools at customer saves time/money- “Scanner Kits”
Christophe Fouquet of ASML
The new CEO of ASML, Christophe Fouquet gave a great opening/keynote speech which centered around High NA EUV.
Its clear that that High NA EUV will not likely have any of the delays that plagued the original EUV roll out. We should expect a relatively rapid rollout and adoption as High NA is more of an “upgrade” to EUV rather than a whole new product .
Christophe spoke about the new methodology of assembling scanner sub components at the customers site rather than assembling them at ASML only to take them apart and reassemble the tool a second time at the customer site.
This has already been done for less complex dep and etch tools and similar tools for a while now but doing it with a high complex litho tool is another thing entirely. But it will save a ton of time and money. This will add to the acceleration of High NA.
Mix and match lens assemblies in the future
The only real difference between a regular EUV tool and a High NA tool is the lens stack, so if you design a tool where the lens stack is in the middle you could swap in regular EUV lenses, High NA lenses or Hyper NA lenses into the same basic tool.
It makes for a ton of commonality , more cost savings, simplicity etc. The modular approach that ASML is taking is supporting this approach.
It will clearly help costs, margins and install times.
Also mentioned during the presentation is that ASML is up to a solid 740 watt source in San Diego with a clear path to 1000 Watts.
All in all, Christophe did a great job in one of his first major public appearances since taking the reigns. His overall overview was great.
Big masks are a “no brainer”- Christophe Fouquet
The idea of doubling mask size from 6″X6″ to 6″X12″ was started in earnest at last years SPIE by Intel. It picked up a lot of speed and support at this years conference with many companies in the Photomask infrastructure signing on to the effort. Chief among those , and key, was ASML (Chritophe) calling the adoption of double size masks a “no brainer” for the industry throwing ASML’s huge weight behind the change.
It also makes obvious sense for ASML as it helps overcome the die size limitation of High NA. The 40% performance improvement is well worth the switch alone
Mark Phillips of Intel underscored the High NA message
Mark Phillips of Intel followed Christophe Fouquet to continue the High NA theme. Intel now has two installed/working High NA systems in Portland.
Mark showed some very nice images from both of the systems, that show the improvement that High NA brings over standard EUV which may be better than expected. The install of the second system went faster than the first as there has been learning.
Its important to note that all the infrastructure that High NA needs is already in place and working. Actinic mask inspection for High NA is already working. So there is not much ancillary support work to be done to get it into production.
Mark was also asked a question about CAR (chemically amplified resists) versus Metal Oxide resists and he said that CAR is fine for now but that we may need metal oxide some time in the future. This seems to push out significantly the need for metal oxide resists such as Lam’s dry resist , much further into the future . Not good news for JSR or Lam.
The targeted insertion point is the Intel 14A process which will be in about 3 years, which again is likely faster than expected.
(The only glitch we heard about at the conference about High NA was that getting the huge High NA tools off the tractor trailer into the fab in Portland was problematic as the trailer bent under the extreme weight load!)
This near flawless install/turn on is good news for Intel as it is a needed “win” for their execution plans especially after being slow to the original EUV rollout
TSMC playing hard to get on High NA but will be forced to come along
As compared to its quick embrace of the original EUV rollout, TSMC has been slow to embrace High NA citing its cost. In our view, this is a bit of a positioning/negotiating game on the part of TSMC perhaps gaming for better terms from ASML.
We don’t think they will hold out very long especially if Intel starts to get a lead on High NA tools. TSMC will have to cave in and go along. TSMC has also been slow on the mask doubling Intel has championed but will also eventually go along as its a free performance increase for them.
Rumors at the conference
We heard that Christophe Fouquet of ASML and Anne Kelleher of Intel got together on Sunday before the conference opened…perhaps to talk about their partnership on the High NA rollout.
We think there may be some good news on the horizon for KLA and its long delayed Actinic mask inspection program, which is well needed.
The Stocks
We would view the conference as obviously very positive for the rollout of High NA EUV and the overall technology progress of Moore’s Law.
It was obviously positive for both Intel and ASML. Certainly good for Intel that needs all the technology wins it can get and High NA is perhaps the most critical technology change the industry is currently undergoing.
Its also positive for ASML as the stock has been shaky and under pressure in large part due to the China issue which has overshadowed the larger technology progress on High NA.
On the larger semiconductor market, it remains all about AI, AI and AI….nothing much else matters.
Trailing edge remains weak as everything revolves around AI.
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specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies. We have been covering the space longer and been involved with more transactions than any other financial professional in the space. We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors. We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.
Dan is joined by Dr. Walden Rhines. Wally is a lot of things, CEO of Cornami, board member, advisor to many and friend to all. Today he is the Executive Sponsor of the SEMI Electronic Design Market Data Report.
Wally reviews the latest report with Dan. Overall growth was strong at 18.2% vs. Q2 2023. Employment for the sector was also strong with a 6.8% increase, up 2.5% from the prior quarter. All product categories were at or near double digit growth and all regions saw double digit growth. Wally explains that there have now been 22 consecutive quarters of positive growth for total EDA revenue.
Wally highlights two regions that had the largest growth. Some other regions showed slower growth as well. Dan and Wally explore the possible reasons for these differences in an in-depth and informative discussion. It turns out one region had a 120% growth in IP sales, IP being the growth leader overall worldwide.
The EDA market is currently an $18B business, showing a significantly increased share of total semiconductor industry revenue. Dan and Wally explore some of the reasons for this change as well. The forces that will either slow this growth trend or keep it going are also discussed. The overall impact of AI development is also touched on.
The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.
Dan is joined by Jakob Engblom this year’s vice chair and keynote chair for DVCon Europe. He’s been in the virtual platforms field since 2002, most recently as director of simulation technology ecosystem at Intel. His interests include simulation technologies, software and hardware testing and validation, programming and debug, embedded and low-level software, and computer architecture.
Jakob, who has been attending DVCon since 2016 provides an overview of the upcoming DVCon Europe event in Munich on October 15 and 16, 2024. He explains that this conference is unique in the region since the program is completely user driven. The technical program presents both academic research and practical application results. This year, there is a System C modeling contest as well.
Jakob explains that the agenda has been modified to expand the number of parallel paper tracks to five. Along with this, there is also more time in the agenda to network and visit the exhibit hall. Jakob also comments that the keynote presentations are strong and he expects a lot of interesting and unique presentations of AI technology.
The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.
Dan is joined by Andrea Gallo, Vice President of Technology at RISC-V International. Andrea heads up the Technical Activities in collaboration with RISC-V members across workgroups and committees in growing the adoption of the RISC-V Instruction Set Architecture. Prior to RISC-V International, Andrea held multiple roles at Linaro developing Arm based solutions. Prior to Linaro Andrea was a Fellow at ST-Ericsson for smartphones and application processors and prior to that he spent 12 years at STMicroelectronics.
Andrea explains the structure and operation of the RISC-V International organization. This ambitious effort includes 70 working groups who each meet on a monthly basis. Andrea attends many of these meetings to ensure good collaboration and to maximize the innovation and impact for all the RISC-V members.
Andrea also describes the upcoming RISC-V Summit. The rich program includes tutorials, member meetings, the popular hackathon, exhibits, a large number of presentations and keynotes from industry leaders, and more.
The RISC-V Summit will take place October 21-23, 2024 in Santa Clara. There are still reduced rate registrations available. You can learn more about the conference and register here.
The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.
Dr. Nikhil Balram has over 25 years of experience in the semiconductor and display industries. Past executive roles include CEO of EyeWay Vision Inc., a startup developing immersive AR glasses, Head of the Display Group at Google, responsible for developing display systems for all Google consumer hardware, including AR and VR, CEO of Ricoh Innovations Corporation, VP and GM of Digital Entertainment BU at Marvell and CTO of the Display Group at National Semiconductor.
He has received numerous awards including the Otto Schade Prize from the Society for Information Display (SID) and a Gold Stevie® Award for Executive of the Year in the Electronics category. Dr. Balram is recognized as a Fellow of the SID and was General Chair for Display Week 2021 and Program Chair for Display Week 2019. Dr. Balram received his B.S., M.S. and Ph.D. in electrical engineering from Carnegie Mellon University, and has served on the faculty of three major universities.
Tell us about your company?
Mojo Vision is developing and commercializing high-performance micro-LED display technology for consumer, enterprise, and government applications. The company combines breakthrough technology, leading display and semiconductor expertise, and an advanced 300mm manufacturing process to deliver on the promise of micro-LED displays. Mojo’s proprietary quantum-dot (QD) technology brings full color capability to our display platform and meets the performance demands for all form factors. Mojo Vision developed the world’s smallest, densest dynamic display for the first augmented reality (AR) smart contact lens and is now applying this innovation and expertise to lead the disruption of the $160B+ display industry. Our beachhead market is AR and we are laser focused on supporting big tech companies with our microdisplay development.
What problems are you solving?
There are several problems that we are solving but for conciseness, I will focus on two critical ones for our beachhead AR customers – brightness and efficiency. A big problem today for our customers is efficient generation of light. Only a small % of original light input is transmitted in AR glasses which means that AR requires an extremely high level of brightness, particularly to be effective in sunlight. Brightness levels need to start with one million candelas per square meter (cd/m2); with that amount of light, conventional quantum-dots that are used in TVs degrade significantly. For TV applications, QDs are facing a light flux of 4 to 8 milliwatts per cm squared but in AR applications, QDs are facing between 4 and 8 watts per cm squared, a thousand times more! At Mojo, we created red and green QDs that solve this lifetime issue for micro-LED applications. For example, we published results from testing red QD film using a power density of 4 watts per cm squared—1,000 times more than a TV – and our red QD film showed flat emission with no degradation for 500 hours and took thousands of hours to degrade to the 80 percent emission level that is sometimes used as a measure of lifetime. That meets initial benchmarks from AR customers; it’s worth noting that a conventional red QD film degraded to 60 percent emission in only 80 hours in the same test setup.
What application areas are your strongest?
As a component supplier, we don’t necessarily have end applications; rather, we support our customers who are building products for their customers, i.e. the end-users. We believe our micro-LED technology will be a platform that serves many different market segments – augmented reality, light field displays, smart wearables, smartphones, televisions, laptops, automotive heads-up displays, high-speed data connectivity in data centers, 3D printing, the list abounds! Any application that needs really tiny, highly bright, and incredibly efficient light sources can benefit from our technology. I mentioned earlier that our beachhead market is AR. For AR to truly scale, the form factor needs to look and feel like the eyeglasses most people wear today, and the industry continues to push for smaller, less obtrusive headsets and smart glasses. This is where we think our micro-LED technology adds the most immediate value and offers a significant advantage over current display technologies like OLED and LCoS (Liquid Crystal on Silicon). The 4µm pixel size in Mojo’s current generation of monolithic RGB panels is critical to enabling a lightweight, compact display, which will be key to making glasses fully ‘smart’ without sacrificing visual-appeal and comfort.
What keeps your customers up at night?
It varies depending on the specific market our customer serves. For those in the AR market, the competitive landscape is intense and constantly evolving. These customers are concerned with staying ahead of their tech rivals by integrating cutting-edge technology and offering value to their end-users. Balancing the right tradeoffs of form factor and performance is a critical worry. The market also has some uncertainty, and the AR hype cycle has left many investors and end users cautious. Customers need to ensure their devices are not only innovative and scalable but also reliable and widely accessible to gain a foothold in this nascent market.
For those in the mass display market (e.g. TVs, laptops, etc.), the main factors keeping them up at night are the pressure of strong competition and aggressive cost management. In a sector characterized by thin margins and high volume, the race to offer the best price-performance ratio is always on. These customers are constantly seeking ways to reduce product costs while maintaining the highest standards of display quality. The need to innovate and differentiate their products without significantly increasing cost is a delicate balancing act.
What does the competitive landscape look like and how do you differentiate?
The competitive landscape in the display market is both dynamic and challenging with a number of strong, established incumbents in traditional display technology (e.g. LCD) and a growing number of players in micro-LED display technology. Micro-LED companies are racing to overcome technical hurdles, achieve mass production, and deliver displays that surpass existing technologies in terms of brightness, efficiency, and color accuracy.
Mojo Vision stands out in the field through several key differentiators:
High Performance Quantum Dot (HPQD): We use properietary QD technology to provide vivid color and high brightness with high reliability. We own the entire end-to-end process for QDs – making, integration, testing – and effectively have a QD company nested within Mojo Vision!
Stable Supply Chain: In an industry where supply chain disruptions can significantly impact production timelines and costs, our reliable supply chain offers a distinct advantage. We have established strong partnerships and a geopolitically stable supply chain, which has become a requirement for many large customers in the US and Europe.
Full Display System Expertise: Unlike many competitors who focus solely on certain elements of a display, we have comprehensive expertise in the entire display system. This holistic approach allows us to optimize every aspect of the display system, from CMOS backplanes to tiny LEDs to custom microlens arrays.
Very Tiny, Very Efficient LEDs: Our micro-LEDs are not only incredibly small (much smaller than a red blood cell!) but also highly efficient. This combination results in displays that are more energy-efficient and capable of delivering superior performance in compact form factors.
By focusing on these differentiators, we provide our customers with cutting-edge micro-LED displays that meet the highest standards of quality, performance, and size, helping them stay ahead in a highly competitive market.
What new features/technology are you working on?
As a startup, we must prioritize our resources and not “boil the ocean” so we are very focused on our beachhead market of AR, bringing a suite of microdisplay products to this next year. These microdisplays also have applicability to other markets such as light field displays and Auto head-up-displays (HUD). We just announced a partnership with heads-up display (HUD) company CY Vision to develop HUDs with micro-LED technology for the automotive industry. These HUDs will leverage artificial intelligence and 3D imaging to provide drivers an immersive and personalized driving experience with informative, line-of-sight overlays that promote driver safety and provide essential information.
At the same time, we are working to develop and validate our concept of Red, Green, and Blue (RGB) chiplets. Mojo’s innovation here will enable cost-effective large format display production by significantly increasing the number of LEDs per wafer and simplifying the mass transfer process. Traditional mass transfer process is complex, requiring LEDs from separate red, green, and blue wafers to be transferred to an intermediate substrate, and then to a final substrate. Our single RGB wafer with tiny RGB chiplets results in 3x fewer transfers per display and 10x+ more pixels per wafer, which means much lower costs.
How do customers normally engage with your company?
We engage directly with customers throughout the year through the deep connections established through our individual experiences in the semiconductor, display and AR/XR industries. Our focus is on customers who are leaders in their respective segments, rather than trying to engage with everyone. Also, we do presentations at several industry conferences, including keynotes, tutorial seminars, panel discussions, and invited papers and articles, that keep our customers, partners and competitors informed of our industry-leading progress.
Part 3 of this 4-part series analyzes methods and tools involved in debugging software at different layers of the software stack.
Software debugging involves identifying and resolving issues ranging from functional misbehaviors to crashes. The essential requirement for validating software programs is the ability to monitor code execution on the underlying processor(s).
Software debugging practices and tools vary significantly depending on the layer of the software stack being addressed. As we move up the stack from bare-metal software to operating systems and finally to applications, three key factors undergo significant changes:
Lines of Code (LOC) per Task: The number of lines of code per task increases substantially as we move up the stack.
Computing Power (MIPS) Requirements: The computing power needed to execute software within a feasible timeframe for debugging grows exponentially.
Hardware Dependency: The dependency on underlying hardware decreases as we ascend the software stack. Bare-metal software is highly hardware-dependent, while applications are typically hardware-independent.
Additionally, the skills required of software developers vary considerably depending on the specific software layer they are working on. Lower-level software development often necessitates a deep understanding of hardware interactions, making it well-suited for firmware developers. In contrast, operating system (OS) development demands the expertise of seasoned software engineers who should collaborate closely with the hardware design team to ensure seamless integration. At the application software layer, the focus shifts toward logic, user experience, and interface design, requiring developers to prioritize user interaction and intuitive functionality.
Table I below summarizes these comparisons, highlighting the differences in software debugging requirements across various layers of the software stack.
Table I: Comparison of three key software attributes along the software stack.
Effective software debugging is a multidimensional challenge influenced by a variety of factors. The scale of the software program, the computational resources available for validation, and the specific hardware dependencies all play critical roles in determining the optimal tools and methodologies for the task.
Software Debug at the Bottom of the Software Stack
The bare-metal software layer sits between the hardware and the operating system, allowing direct interaction with the hardware without any operating system intervention. This layer is crucial for systems that demand high performance, low latency, or have specific hardware constraints.
Typically, the bare-metal layer includes the following components:
Bootloader: Responsible for initializing the hardware and setting up the system to ensure that all components are ready for operation.
Hardware Abstraction Layer (HAL): A comprehensive set of APIs that allow the software to interact with hardware components. This layer enables the software to work with the hardware without needing to manage low-level details, providing a simplified and consistent interface.
Device Drivers: These software components initialize, configure, and manage communication between software and hardware peripherals, ensuring seamless interaction between different system parts.
Prerequisites to Perform Software Validation at the Bottom of the Software Stack
When validating software at the lower levels of the software stack, two key prerequisites must be considered.
First, processing software code that goes beyond simple routines requires a substantial number of clock cycles, often numbering in the millions. This can be efficiently handled by virtual prototypes or hardware-assisted platforms, such as emulators or FPGA prototypes.
Second, the close interdependence of hardware and software at this level necessitates a detailed hardware description, typically provided by RTL. This is where hardware-assisted platforms excel. However, for designs modeled at a higher level than RTL, virtual prototypes can still be effective, provided the design is represented accurately at the register level.
Processor Trace for Bare-Metal Software Validation
Processor trace is a widely used method for software debugging that involves capturing the activity of a CPU or multiple CPUs non-intrusively. This includes monitoring memory accesses and data transfers with peripheral registers and sending the captured activity to external storage for analysis, either in real-time or offline, after reconstructing it into a human-readable form.
In essence, processor trace tracks the detailed history of program execution, providing cycle counts for performance analysis and global timestamps for correlating program execution across multiple processors. This capability is essential for debugging software coherency problems. Processor trace offers several advantages over traditional debugging methods like JTAG, including minimal impact on system performance and enhanced scalability.
However, processor trace also presents some challenges, such as accessing DUT (Device Under Test) internal data, storing large amounts of captured data, and the complexity and time-consuming nature of analyzing that data.
DUT Data Retrieval to External Storage
Retrieving DUT internal data in a hardware-assisted platform can be achieved through an interface consisting of a fabric of DPI-based transactors. This mechanism is relatively simple, it does not add overhead and marginally impacts execution speed. The state of any register and net can be monitored and saved to external storage. As the design grows larger and the run-time extends, exponentially more data gets retrieved.
Despite efforts to standardize the format of the collected data, there is currently no universal format, which poses a challenge to performing analysis. However, we must also acknowledge that DUT architectures like x86, RISC-V, ARM are fundamentally different to ever allow standardization.
In summary, even with the challenges, processor trace has been in use for many years and is broadly adopted by most modern processors from major vendors such as Arm, RISC-V, and others. With ARM, since it’s a single vendor – standardization has been easier to come by. On the other hand, RISC-V is open source and multi-vendor.
Arm TARMAC & CoreSight
Arm TARMAC and CoreSight are complementary Arm technologies for debugging and performance analysis.
TARMAC is a post-execution analysis tool capturing detailed instruction traces for in-depth investigations. It records every executed instruction, including register writes, memory reads, interrupts, and exceptions in a textual format. It generates reports and summaries based on the trace data, such as per-function profiling and call trees. This allows developers to replay and analyze the sequence of events that occurred during program execution.
CoreSight is an on-chip solution providing real-time visibility into system behavior without halting execution. It provides real-time access to the processor’s state, including registers, memory, and peripherals, without stopping the CPU. Table II compares Arm TARMAC vs CoreSight.
Table II: Comparison of Arm CoreSight versus TARMAC.
In essence, CoreSight is the hardware backbone that enables the generation of trace data, while Arm Tarmac is the software tool that makes sense of that data.
RISC-V E-Trace
Figure 1: Verdi provides a unified HW/SW views for efficent debug of the interactions between the two domains. Source: Synopsys
E-Trace is a high-compression tracing standard for RISC-V processors. By focusing on branch points rather than every instruction, it significantly reduces data volume, enabling multi-core tracing and larger trace buffers. This is especially beneficial to trace multiple cores simultaneously and store larger trace histories within fixed-size buffers. E-Trace is useful for debugging custom RISC-V cores with multiple extensions and instructions, ensuring that all customizations work correctly. It also supports performance profiling and code coverage analysis.
Synopsys Verdi Hardware/Software Debug
Verdi HW/SW Debug provides a unified view of hardware and software interactions. By synchronizing software elements (C code, assembly, variables, registers) with hardware aspects (waveforms, RTL, assertions), it enables seamless navigation between the two domains. This integrated approach facilitates efficient debugging by correlating software execution with hardware behavior, allowing users to step through code and waveforms simultaneously and pinpoint issues accurately. See Figure 1.
Synopsys ZeBu® Post-Run Debug (zPRD)
ZeBu Post-Run Debug (zPRD) is a comprehensive debugging platform that supports efficient and repeatable analysis. By decoupling the debug session from the original test environment, zPRD accelerates troubleshooting by allowing users to deterministically recreate any system state. It simplifies the debugging process by providing a centralized control center for common debugging tasks like signal forcing, memory access, and waveform generation. Leveraging PC resources, zPRD optimizes waveform creation for faster analysis.
Moving up of the Software Stack: OS Debug
Operating systems consist of a multitude of software programs, libraries, and utilities. While some components are larger than others, collectively they demand billions of execution cycles, with hardware dependencies playing a crucial role.
For debugging an operating system when hardware dependencies are critical, the processor trace method is still helpful. However, this approach, while effective, becomes more complex and time-consuming when dealing with the largest components of an OS.
GNU Debugger
Among the most popular C/C++ software debugging tools in the UNIX environment is GDB (GNU Debugger). GNU is a powerful command-line tool used to inspect and troubleshoot software programs as they execute. It’s invaluable for developers to identify and fix bugs, understand program behavior, and optimize performance.
The GNU key features Include:
Setting breakpoints: Pause program execution at specific points to inspect variables and program state.
Stepping through code: Execute code line by line to understand program flow.
Examining variables: Inspect the values of variables at any point during execution.
Backtracing: Examine the function call stack to understand how the program reached a particular point.
Modifying variables: Change the values of variables on the fly to test different scenarios.
Core dump analysis: Analyze core dumps to determine the cause of program crashes.
Remote Debugging: GDB can debug programs running on a different machine than the one it is running on, which is useful for debugging embedded systems or programs running on remote servers.
GDB can be employed to debug a wide range of issues in various programming languages. Among common use cases are:
Segmentation faults: These occur when a program tries to access memory it doesn’t own. GDB can help pinpoint the exact location where this happens.
Infinite loops: GDB can help you identify code sections that are looping endlessly.
Logical errors: By stepping through code line by line, you can examine variable values and program flow to find incorrect logic.
Memory leaks: While GDB doesn’t have direct tools for memory leak detection, it can help you analyze memory usage patterns.
Core dumps: When a program crashes unexpectedly, a core dump is generated. GDB can analyze this dump to determine the cause of the crash.
Performance bottlenecks: By profiling your code with GDB, you can identify sections that are consuming excessive resources.
Debugging multi-threaded programs: GDB supports debugging multi-threaded applications, allowing you to examine the state of each thread.
GDB is an effective debugging tool for software developers, especially those working with low-level or performance-critical code.
At the Top of the Software Stack: Application Software Debug
Application software spans a wide range of complexity and execution time. Some applications may execute within few millions of cycles, other all the way to billions of cycles. All demand efficient development environments. Virtual prototypes offer a near-silicon execution speed, making them ideal for pre-silicon software development.
A diverse array of debuggers serves different application needs, operating systems, programming languages, and development environments. Popular options include GDB, Google Chrome DevTools, LLDB, Microsoft Visual Studio Debugger, and Valgrind.
To further streamline development, the industry has adopted Integrated Development Environments (IDEs), which provide a comprehensive platform for coding, debugging, and other development tasks.
IDEs: Software Debugger’s Best Friend
An Integrated Development Environment (IDE) is a software application that streamlines software development by combining essential tools into a unified interface. These tools typically include a code editor, compiler, debugger, and often additional features like code completion and version control integration. By consolidating these functionalities, IDEs enhance developer productivity, reduce errors, and simplify project management. Available as both open-source and commercial products, IDEs can be standalone applications or part of larger software suites.
Further Software Debugging Methodology and Processes
Error prevention and detection are integral to software development. While debugging tools are essential, they complement a broader range of strategies and processes aimed at producing error-free code.
Development methodologies such as Agile, Waterfall, Rapid Application Development, and DevOps offer different approaches to project management, each with its own emphasis on quality control.
Specific practices like unit testing, code reviews, and pair programming are effective in identifying and preventing errors. Unit testing isolates code components for verification. Code reviews leverage peer expertise to catch oversights. Pair programming fosters real-time collaboration and knowledge sharing.
By combining these strategies with debugging tools, developers can significantly enhance software quality and reliability.
Conclusion
Debugging is an integral part of the software development process that spans the entire software stack, from low-level firmware to high-level application software. Each layer presents unique challenges and requires specialized tools and techniques.
In low-level debugging, understanding hardware interactions and system calls is crucial. Tools like processor trace help developers trace issues at this foundational level. This is where users tend to be comfortable with register models, address maps, memory maps etc. Moving up the stack, debugging becomes more abstract, involving memory management, API calls, and user interactions. Here, debuggers like GDB and integrated development environments (IDEs) with built-in debugging tools prove invaluable. The user in this space is more comfortable with the APIs provided by the OS or the application. They are dependent on hardware or firmware engineers to identify issues in the lower levels of the stack.
During the pre-silicon phase all software debugging tools all rely on the ability to execute the software on a fast execution target being a virtual prototype, emulation or FPGA-based prototyping. Beside the performance of the underlying pre-silicon target, the flexibility and ease of use to extract different types of debug data for the different software stack levels drive debug productivity. With more and more workloads moving to emulation and prototyping platforms, the user community is placing an even bigger ask to help debug their environments and system issues. However, there is this delicate balance between debuggability and performance of such a platform. There is an inverse relationship between debuggability and performance.
Looking forward, the evolution of debugging tools and methodologies is expected to embrace machine learning and AI to predict potential bugs and offer solutions, thereby transforming the landscape of software debugging.
