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AI RTL Generation versus AI RTL Verification

AI RTL Generation versus AI RTL Verification
by Bernard Murphy on 11-06-2025 at 10:00 am
Categories: AI, Bronco AI, ChipAgents AI, EDA
4 Comments

RTL generation vs RTL Verification

I should admit up front that I don’t have a scientific answer to this comparison, but I do have a reasonably informed gut feel, at least for the near-term. The reason I ask the question is that automated RTL generation grabs headlines with visions of designing chips through natural language prompts, making design widely accessible. No doubt this has a lot of media appeal, an attractive place to invest AI $$. But the realities of chip design today don’t support that bet and are more aligned with investment in AI-assisted verification. Verification may not be as glamorous as design but looks like a much more compelling target for AI investment today.

Where are the real costs in design?

Years of analysis in the semiconductor industry (e.g. this Wilson report) confirm that on average 50% or more of IC/ASIC project time is spent in verification. Projects require as many verification engineers at peak as design engineers (the people building RTL) and even design engineers spend half their time in verification. Verifying RTL is a major time- and resource-consuming sink in chip design.

That verification far outweighs RTL design should not be surprising in an age where IP reuse and design reuse dominate. Few organizations have the luxury to start from a clean sheet on each design. Even startups will use commercial IP. Silicon Catalyst portfolio companies can tap into a wide range of IP, from Arm for example, at no up-front cost. There will always be some differentiating content requiring from-scratch development or extensive redesign but the hard part there is the innovation and making the idea practical in a competitive PPA envelope, not in creating the RTL.

Challenges for RTL creation

I can’t find a definitive “first” paper on using GenAI to create RTL but there are plenty of recent papers. These continue to show progress, at about the same rate as parallel efforts in software generation, intriguing but not up to hands-free usage.

More common is usage as an assistant – think of an extended auto-completion operation. A designer might describe in a comment what a following always block should do and ask the auto-completer to create that block. An emerging measure of how successful that operation is in practice, whether for RTL or software, is the rate at which the designer/programmer accepts the generated logic. Fairly consistently this seems to be around 25%.

25% is not bad for an autocompleter. How often do you accept an MS-Word or text message autocompletion? I don’t most of the time, but sometimes it’s useful. RTL auto-completion is more complex than sentence completion, so hats off to RTL generators for getting this far.

Why isn’t the acceptance rate better? There are multiple reasons. Lack of a sufficiently broad training corpus and ambiguities in the comment prompt are two obvious examples. Another revealing example is that, without additional coaching, a bot will assume the timing depth of an expression depends on the number of terms in the expression, not recognizing that arithmetic expressions are more costly than logic expressions. For some other examples see this paper.

The core problem is that generating quality RTL is a lot more complex than current systems can rise to, even for an always block. Does it support PPA targets? Does it create security or safety holes? Is the implementation intuitively reasonable and is it readily maintainable by an RTL designer?

Could more of these problems be solved in time? Quite possibly, which is why I think RTL creation moonshots are worth supporting. But we shouldn’t confuse those efforts with near-term ROI.

Opportunities in RTL verification

A big opportunity for return should be in debug, representing 47% of verification effort according to the same Wilson report. Despite years of study, in debug we still haven’t advanced far beyond debugger IDEs, which certainly help visualize behavior but do little to triage or root-cause bugs in aid of compressing debug time. (there are some point solutions, e.g. for triaging CDC violations.)

Promising signs can be seen in agentic approaches to debug, from startups like ChipAgents and Bronco AI. Triage – reducing and assigning a pile of bugs from a regression to sub-teams for further analysis – might be the biggest contribution here. As engineers we tend to obsess about how to automate root cause analysis for hard corner cases, but more effort is likely consumed in triage around the bulk of less complex bugs than in a few anomalous cases. Initial root-cause isolation (did this error come from module A or module B) can drill down to approximate fault locations, to avoid wasting engineer time on trying to debug a problem that isn’t in their code after all.

Agentic methods should be ideal for this sort of analysis for two reasons. First they can learn from expert engineers how they would approach triage and rough root-causing. Second, because they are agentic they should be able to run additional trial simulations to confirm or rule-out preliminary guesses.

This approach to debug builds on verification know-how and methods that have been in refinement for years. Success here, even partial success, could show significant ROI. Contrast that with an as-yet unquantified level of investment to improve RTL generation quality, where we also don’t know what value we can assign to partial success.

Food for thought.

Also Read:

Scaling Debug Wisdom with Bronco AI

CEO Interview with David Zhi LuoZhang of Bronco AI

ChipAgents Tackles Debug. This is Important

CEO Interview with Dr. William Wang of Alpha Design AI

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Memory Matters: The State of Embedded NVM (eNVM) 2025

Memory Matters: The State of Embedded NVM (eNVM) 2025
by Daniel Nenni on 11-06-2025 at 6:00 am
Categories: GlobalFoundries, IP, Samsung Foundry, TSMC
1 Comment

NVM Survey 25 Square Banner for SemiWiki 400x400 px

Make a difference and take this short survey. It asks about your experience with embedded non-volatile memory technologies. The survey is anonymous, and the results will be shared in aggregate to help the industry better understand trends: 2025 Embedded Non-Volatile Memory Survey.

We are now in the AI era where data is the lifeblood of innovation, and embedded NVM stands as a cornerstone technology, retaining information without using power and enabling everything from MCUs and IoT SoCs to automotive controllers and secure elements.

As of November 2025, embedded NVM is moving fast. Edge data is surging, AI features are landing on MCUs and SoCs, and power budgets are tighter than ever. Memory is central to the devices we build. This survey looks at where eNVM stands today in terms of markets, technology, and adoption, and where it’s heading next.

Market Overview and Growth

Embedded emerging NVM, including MRAM, RRAM/ReRAM, and PCM, is entering a broader adoption phase across MCUs, connectivity, and edge-AI devices, with momentum building in automotive and industrial markets. Research firm Yole Group indicate the embedded emerging segment should exceed $3B by 2030, reflecting wider availability in mainstream process nodes and stronger pull where eFlash is no longer a good fit at ≤28 nm.

Technological Advancements

Embedded flash remains foundational, but scaling limits at advanced nodes have pushed MRAM, ReRAM, and embedded PCM to the foreground. Foundries and IDMs are extending embedded options beyond 28/22 nm planar CMOS toward 10–12 nm-class platforms, including FinFET. Yole highlights aggressive foundry roadmaps: TSMC has established high-volume MRAM/ReRAM and is preparing 12nm FinFET ReRAM/MRAM for 2025 and beyond. Samsung, GlobalFoundries, UMC, and SMIC are accelerating embedded MRAM/ReRAM/PCM across general-purpose MCUs and high-performance automotive designs. STMicroelectronics stands out as the IDM fully committed to embedded PCM, ramping xMemory solutions for industrial and automotive MCUs, with 18nm FD-SOI extending reach after 2025.

In parallel, BCD and HV-CMOS flows are incorporating embedded NVM as practical replacements for EEPROM/OTP in analog, power management, and mixed-signal designs. On the IP side, suppliers are qualifying embedded NVM technologies for these platforms, giving designers more options where cost, endurance, and retention outweigh legacy choices. Beyond code and data storage, in-/near-memory compute concepts using eNVM are gaining interest for low-power edge AI inference.

Drivers, Challenges, and Use Cases

Automotive remains the center of gravity for embedded emerging NVM, and 2025 brings a noticeable uptick in secure ICs and industrial MCUs as more products reach production. In practice, ReRAM, MRAM, and PCM each have a role: ReRAM is gaining traction in several high-volume categories; MRAM and PCM are attractive where speed and endurance dominate. The mix varies by node, application, and vendor roadmap.

The challenges are familiar: integrating eNVM at advanced logic nodes, trading off endurance and retention, qualifying to automotive-grade reliability, and achieving cost-effective density as embedded code and AI parameters grow. The trend line is positive, with PDK/IP availability growing and capacity ramping, so these issues are being addressed rather than deferred.

Outlook

By 2030, embedded NVM will underpin more on-chip AI features and practical in-/near-memory compute blocks, with broader use in neuromorphic-inspired accelerators at the edge. Yole’s projections indicate that the embedded emerging segment is now the primary engine of growth, led by ReRAM in high-volume MCUs and analog ICs, while MRAM and embedded PCM consolidate in performance-critical niches. As edge data grows, eNVM’s role expands from “just storage” to part of the computing fabric, redefining efficiency and making embedded memory more central than ever to device intelligence.

Bottom line: In 2025, embedded NVM isn’t just memory, it’s the enabler of intelligent, persistent systems on chip. With accelerating adoption across MCUs and edge SoCs, and clear roadmaps from leading foundries and IDMs, the trajectory is set: embedded memory matters more than ever. Let us know your opinion by taking the short survey.

Take the 2025 Embedded Non-Volatile Memory Survey Here.

Also Read:

Chiplets: Powering the Next Generation of AI Systems

Podcast EP312: Approaches to Advance the Use of Non-Volatile Embedded Memory with Dave Eggleston

Podcast EP311: An Overview of how Keysom Optimizes Embedded Applications with Dr. Luca TESTA

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5 Lessons the Semiconductor Industry Can Learn from Gaming

5 Lessons the Semiconductor Industry Can Learn from Gaming
by Admin on 11-05-2025 at 10:00 am
Categories: EDA, Perforce, RISC-V

Perforce 1

By Kamal Khan
The semiconductor world has always been the beating heart of tech innovation, powering everything from our smartphones to the latest AI breakthroughs. However, as chip complexity increases and market demands accelerate, adherence to traditional development cycles may be stagnating design teams and slowing the pace of innovation.

In contrast, the gaming industry has perfected a model of rapid, iterative development and profound user-centricity. Game developers ship products, gather massive amounts of feedback, and iterate at a pace that is often foreign to the more rigid semiconductor world.

For semiconductor design teams, engineers, and executives, the methodologies that drive the fast-paced gaming world offer valuable new perspectives. Here are five key lessons they can learn from gaming:

1. Embrace Iterative Innovation and Agility

The Challenge: Rigid, Waterfall-Style Development Cycles

Semiconductor firms become entrenched in rigid development cycles that feel almost ceremonial. Roadmaps are often planned years in advance, and the design process follows a rigid, waterfall-like progression from specification to tapeout. While this approach supports the careful level of control needed to prevent costly errors, it can also stifle innovation and make it difficult to pivot in response to new market demands or technical challenges.

Lesson: Develop Agility Through Iteration and Feedback.

Game development is a dynamic and often chaotic process. Studios frequently release beta versions of their games only to pivot entire projects after a single weekend of testing. This agile approach allows them to refine the user experience, fix bugs, and ensure the final product resonates with its audience.

Applying It to Semiconductors:

While the physical constraints of chip manufacturing are undeniable, the pre-production and verification stages offer significant room for agility. Semiconductor teams can adopt a more iterative mindset by:

  • Implementing Agile Verification: Instead of waiting for the entire design to be complete, teams can use incremental verification techniques to test and validate smaller blocks of IP as they are developed. This allows for earlier feedback and reduces the risk of discovering major flaws late in the cycle.
  • Leveraging Early Prototypes: Using Field-Programmable Gate Arrays (FPGAs) and emulation platforms allows for earlier software development and system-level testing. This creates a feedback loop that can inform hardware design long before tapeout, much like a game’s beta test.
  • Adopting Spiral Development Models: Rather than a linear progression, a spiral model involves creating successive iterations of a design, with each loop building upon the last and incorporating feedback and new requirements.

By divorcing themselves from long-duration design cycles, semiconductor firms can become more experimental, responsive, and ultimately more innovative.

2. Understand and Prioritize the End-User Experience

The Challenge: A Disconnect from the End-User

Semiconductor companies are engineering-driven and often disconnected from the humans who ultimately use their products. They tend to focus on hitting performance benchmarks, increasing transistor density, and achieving specific power targets. While these metrics are critical, they can lead to a disconnect from the software developers and end consumers who ultimately use the technology.

Lesson: Get to Know Your End-Users.

Game developers are fanatical about the player experience. They invest countless hours in playtesting and user research to ensure that a game not only performs well but also “feels right.” Gameplay mechanics, user interface design, and overall enjoyment are key to success, and developers will often scrap months of work if players don’t find the experience compelling.

Applying It to Semiconductors:
Chip designers can think beyond raw benchmarks and consider how hardware design choices impact the end application.

  • Prioritize Real-World Workloads: Instead of focusing solely on synthetic benchmarks, design and optimize chips for specific, real-world applications like AI inference, high-fidelity gaming, or complex data processing. NVIDIA’s success is a testament to this approach; their GPUs are designed to excel in both gaming and AI, two markets with very specific, high-performance demands.
  • Engage with Software Developers: By actively engaging with the software developers who build applications on your hardware, chipmakers can gain invaluable insights into which features are most important and how to optimize chips for these programmers.

By shifting the focus from theoretical improvements to tangible user benefits, semiconductor firms can create products that offer a superior real-world experience and command greater market loyalty.

3. Implement Real-Time Optimization

The Challenge: Static, Pre-Defined Performance

A chip’s performance parameters are traditionally set during the design phase. While some level of power management exists, the hardware itself cannot adapt its core functionality in real-time in response to changing workloads. This can lead to inefficiencies where a chip may consume more power than necessary or fail to deliver peak performance when it is most needed.

Lesson: Adopt Real-Time, Game Engine-Like Adaptation

Game engines like Unity and Unreal don’t simply set parameters once, they constantly adjust rendering quality, physics calculations, and asset loading to maintain a smooth and consistent frame rate. The result is a perfect balance of visual quality and performance that keeps their users engaged.

Applying It to Semiconductors:
The chips of the future should behave more like game engines by intelligently and dynamically adapting to their workloads.

  • AI-Driven Design and Power Management: The semiconductor industry is exploring AI in electronic design automation (EDA) to optimize chip layouts. The next step is to integrate this intelligence directly into silicon via on-chip AI that predicts future workloads and pre-emptively adjusts clock speeds, voltage, and even processing unit configuration.
  • Adaptive Architectures: Design chips with more flexible and reconfigurable components. A processor that could dynamically reallocate resources between its CPU, GPU, and neural processing units based on the specific demands of an application would always be optimized for the task at hand.

By building chips that can learn and adapt in real-time, the semiconductor industry can elevate performance and efficiency beyond what is possible in static designs.

4. Break Down Ecosystem Walls

The Challenge: Fragmented Architectures and Ecosystems

Fragmented or varied architectures (like x86 and ARM) and proprietary ecosystems force software developers to spend significant time and resources optimizing their code for each specific platform. This lack of interoperability stifles innovation and creates a frustrating experience for developers.

The Lesson: Solve for Cross-Platform Consistency

The gaming industry has largely solved the challenge of cross-platform development. A game developed using an engine like Unity can be deployed across $3,000 PC or a five-year-old smartphone with a relatively unified feel and performance. This is achieved by focusing on tools and APIs that work seamlessly across different hardware.

Applying It to Semiconductors:
There is a significant opportunity for chipmakers to embrace this ecosystem-first mindset.

  • Standardize Software Interfaces: By working together to create more standardized APIs and hardware abstraction layers (HALs), the industry can reduce the burden on software developers. The goal should be to allow developers to write code once and have it run efficiently across a wide range of hardware.
  • Embrace Open Standards: Supporting open standards like RISC-V is a powerful way to break down ecosystem walls. An open and collaborative approach to instruction set architecture (ISA) design encourages broader adoption and innovation.

The days of writing completely different code for different chips should be behind us. Hardware should be designed for seamless interoperability.

5. Build Communities, Not Just Products

The Challenge: Siloed Design Spaces and a B2B Mindset

Many semiconductor firms operate with a traditional B2B mindset, viewing their customers as other businesses rather than a community of developers and end users. This approach leads to siloed design processes and missed opportunities for valuable feedback and co-innovation.

The Lesson: Harness the Power of Community

The most successful game companies treat their communities are their greatest asset. They actively engage with players, streamers, and modders (users who create modifications for games) to obtain invaluable feedback. This symbiotic relationship elevates their products to meet consumer needs, fosters loyalty, and serves as a powerful marketing engine.

Applying It to Semiconductors:
Semiconductor firms can unlock immense value by cultivating genuine communities.

  • Open-Source Collaboration: Actively participating in and contributing to open-source hardware and software projects is a powerful way to engage with the developer community. This fosters goodwill, accelerates innovation, and provides direct insight into the needs of your users.
  • Gamified Learning and Engagement: The industry can draw inspiration from gaming to educate the next generation of engineers. For example, researchers at UC Davis developed “Photolithography,” a game that teaches players how to build virtual semiconductors.

By transforming from closed-off component suppliers into active ecosystem participants, semiconductor companies can build stronger relationships and create products that are more aligned with the needs of their market.

Designing an Adaptive and Collaborative Semiconductor Future

AI and gaming are powerful forces propelling advancements in semiconductor technology. The companies that lead will do so by incorporating agile methodologies, real-time simulations, AI-driven automation, scalability, and user-centric design. However, this shift requires the right tools.

Perforce IPLM provides a unified environment for managing the complexities of semiconductor design, from IP lifecycle management to verification and documentation. By breaking down silos and enabling secure, global collaboration across teams, Perforce IPLM empowers semiconductor companies to adopt the agile principles of the gaming world and accelerate their path to innovation. Learn more today.

Watch the Free Demo

Talk to an Expert

Kamal Khan is Vice President North American Gaming and Hi Tech. He has over 20 years of domestic and international experience, specializing in PLM, Data Management, IP lifecycle management, IoT Security, Semiconductors, Enterprise software, EDA, CAD, 3D Printing, Cloud solutions. 

This article was originally published on Perforce.com. For more information on how Perforce IPLM streamlines semiconductor development , visit https://www.perforce.com/products/helix-iplm
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Podcast EP316: An Introduction to Hardware Security Modules (HSMs) and Marvell’s Unique LiquidSecurity Offering with Bill Hagerstrand

Podcast EP316: An Introduction to Hardware Security Modules (HSMs) and Marvell’s Unique LiquidSecurity Offering with Bill Hagerstrand
by Daniel Nenni on 11-05-2025 at 8:00 am

Daniel is joined by Bill Hagerstrand, director of Security Business at Marvell Technology where he manages the market-leading Marvell LiquidSecurity® HSM business. Bill has more than 20 years of experience in the semiconductor, AI/machine learning, and security markets.

Bill explains what an HSM is, how it is configured and what functions it performs across multiple applications. He explains the key customer needs in this growing market both today and tomorrow. Bill also describes the unique capabilities offered by Marvell’s LiquidSecurity products and how they provide expanded capabilities in the marketplace.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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A Compelling Differentiator in OEM Product Design

A Compelling Differentiator in OEM Product Design
by Bernard Murphy on 11-05-2025 at 6:00 am
Categories: AI, EDA, Siemens EDA

PartQuest

Jennifer, an OEM hardware designer, is planning a product around a microcontroller she thinks will meet her needs and wants to supply power from a 3V coin cell battery which she must connect though a boost controller. Jennifer searches a rough description of the part she needs, generating a long list of component manufacturers who are all anxious to attract her attention. She clicks through the websites, scans the headlines and tries to drill down through white papers and technical datasheets. She ends her day with a headache and still no clear idea of who would be the best fit since tradeoffs in how she builds her design depend on component details that are difficult to extract from multiple dense PDFs.

Suppose instead she started her parts search along a path designed to guide her painlessly to a decision. She can do all the discovery she wants without having to leave her terminal, without needing to read through lengthy datasheets, or committing to a purchase. She can experiment with interactive reference designs, exploring parameter changes that will more closely match her needs. At every step Jennifer becomes more confident that she has found the right component to fit her objectives. This component manufacturer is on track for a design win before sales ever picks up a phone, and she will be drawn naturally to look for her next component from the same supplier.

Redesigning initial component discovery for the OEM engineer

Nobody wants to wade through datasheets and technical specs in the early stages of discovery. This is the age of AI and chatbots. We should be able to ask natural language questions about configurations and operating parameters and expect to get helpful answers — more detailed answers than are available through a generic GPT-like search.

This more effective search might narrow the field perhaps to a couple of options. Our engineer now wants to experiment with the component she thinks might be the best fit, but without having to get into detailed eCAD yet. The manufacturer offers an interactive reference design in which she can experiment with parameters, maybe battery voltage and internal resistance, and directly view impact on behavior, say for load current draw.

The manufacturer also offers exploration tools to view schematics, PCB layout, and BOM for the reference design so she can develop a sense of how this may translate to her product objectives. At the same time, she can check availability, supply chain issues, and regional compliance issues, minimizing time wasted on manufacturing mismatches and forestalling any late-stage manufacturing surprises.

A Siemens white paper has an interesting way of describing this interaction. Unlike traditional marketing-centric web pages and PDFs, this is engineering outreach, not marketing outreach.

Now that she is committed to this path, Jennifer can transition her trial experiments into full eCAD development around her design, through a natively supported tool suite accessible through this interactive design enablement flow or through a preferred in-house flow supported by direct eCAD model downloads based on the parts she’s selected — while continuing to keep an eye on potential manufacturing hiccups as geopolitical realities evolve.

Collaboration, enhancing manufacturer stickiness

Jennifer may have questions which can’t be answered through AI searches or interactive references. Collaborative discussion with an expert application engineer can guide her through these concerns. With permission, the apps experts can review detailed and more open-ended questions in the context of a design example and suggest possibilities through markup, comments or examples — without the need to schedule meetings.

This interaction has obvious benefits both for the designer and for the component manufacturer. The designer has a simple glide path to component selection using the language she speaks: natural language filters, trials against an interactive reference design and schematic and PCB layout to confirm the fit to her objective. The manufacturer gets a prospect already invested in how their components fit her solution without the overhead of meetings. Everyone wins.

Does this vision sound appealing? Read this Siemens white paper for a more detailed understanding of how they have enabled this solution together with Microchip as a component manufacturer.

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Pioneering Engineer Dr. Tsu-Jae King Liu to Receive Semiconductor Industry’s Top Honor

Pioneering Engineer Dr. Tsu-Jae King Liu to Receive Semiconductor Industry’s Top Honor
by Daniel Nenni on 11-04-2025 at 10:00 am
Categories: Events

Dr. Tsu Jae King Liu SemiWiki

In a landmark recognition of trailblazing innovation and leadership, Dr. Tsu-Jae King Liu, the newly elected President of the National Academy of Engineering has been named the 2025 recipient of the Global Semiconductor Alliance’s highest accolade: the Dr. Morris Chang Exemplary Leadership Award. Announced on October 23, 2025, this prestigious honor underscores Liu’s profound influence on semiconductor technology, from groundbreaking inventions that power modern computing to her steadfast advocacy for engineering education and global collaboration. The award, to be presented at GSA’s Annual Awards Celebration on December 4, 2025, in San Jose, California, celebrates individuals whose visionary contributions have reshaped the $662 billion industry.

The Dr. Morris Chang Exemplary Leadership Award, established in 1999 and named after TSMC founder Dr. Morris Chang, honors exceptional figures who drive innovation, growth, and long-term opportunities in semiconductors. It recognizes creativity that yields measurable impacts, such as fostering company growth or advancing the supply chain, and is open to nominees from academia, industry, government, or venture capital. Administered by GSA’s Awards Committee and approved by its Board, the award is selective—sometimes withheld if no candidate meets its rigorous standards. Liu joins an elite cadre of past honorees, including Chang himself, whose leadership at TSMC revolutionized chip manufacturing.

Born in Taiwan and raised in the United States, Liu’s journey exemplifies the fusion of academic rigor and practical ingenuity. She earned her B.S., M.S., and Ph.D. in electrical engineering from Stanford University in 1984, 1986, and 1994, respectively. Her early career at Xerox Palo Alto Research Center (1992–1996) focused on thin-film transistor technology, enabling the high-definition flat-panel displays that dominate consumer electronics today. In 1996, she joined the University of California, Berkeley’s Department of Electrical Engineering and Computer Sciences, where she spent over 25 years as a professor, amassing more than 550 publications and 97 U.S. patents.

Liu’s crowning achievement is her co-invention of the FinFET in collaboration with Berkeley colleagues Chenming Hu and Jeffrey Bokor. Introduced in the early 2000s, this nanoscale design overcame the limitations of traditional planar transistors, allowing chips to shrink dramatically while boosting performance and efficiency. FinFETs underpin advanced processors in smartphones, servers, and AI systems, enabling Moore’s Law to persist amid physical constraints. Her work earned accolades like the DARPA Significant Technical Achievement Award, the IEEE Kiyo Tomiyasu Award for pioneering contributions to electronics engineering, and the Intel Outstanding Researcher in Nanotechnology Award. In 2017, she was elected to the NAE; in 2018, to the National Academy of Inventors. As an IEEE Fellow, Liu also received the IEEE Founders Medal in 2024 for her lifetime of innovation.

Beyond research, Liu’s leadership has amplified her impact. At Berkeley, she chaired the EECS department (2014–2016), served as Vice Provost for Academic and Space Planning (2016–2018), and led the College of Engineering as Dean (2018–2025). In these roles, she championed interdisciplinary initiatives, diversified STEM participation, and forged industry ties to address talent shortages. Her mentorship earned her the EECS EE Division Outstanding Teaching Award in 2003 and UC Berkeley’s Distinguished Teaching Award. Elected NAE President in 2025, Liu now advises on national engineering priorities, including the CHIPS Act’s workforce needs. She has served on boards for Intel and MaxLinear and as a NIST Industrial Advisory Committee member, bridging academia and industry.

“Tsu-Jae King Liu’s leadership and groundbreaking contributions have helped shape the future of semiconductor technology and the talent who power it,” said Jodi Shelton, GSA CEO. “Her influence spans industry and academia, and her example continues to inspire generations of innovators. We are proud to honor her as the first woman in academia to receive the Dr. Morris Chang Exemplary Leadership Award.”

Liu’s Taiwanese heritage adds poignant resonance. “I am deeply honored to have been selected as the 2025 Dr. Morris Chang Exemplary Leadership Award recipient, especially since my ancestral roots are in Taiwan where Dr. Chang’s leadership has had transformative impact,” she stated. “I have been very fortunate to work with – and learn from – many exemplary leaders, and to be part of a vibrant, global community that advances technology for the benefit of people and society.”

This award arrives at a pivotal moment for semiconductors, amid geopolitical tensions and surging demand for AI and clean energy tech. Liu’s holistic approach—merging invention with equitable education—positions her to guide the NAE in tackling these challenges. As GSA’s event draws over 1,500 leaders, her recognition not only celebrates past triumphs but ignites future ones, ensuring the industry’s innovations serve humanity broadly. In an era demanding resilient supply chains and diverse talent, Dr. Liu’s legacy illuminates the path forward, proving that exemplary leadership transcends borders and disciplines.

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PDF Solutions Charts a Course for the Future at Its User Conference and Analyst Day

PDF Solutions Charts a Course for the Future at Its User Conference and Analyst Day
by Mike Gianfagna on 11-04-2025 at 8:19 am
Categories: EDA, Events, PDF Solutions
2 Comments

PDF Solutions Charts a Course for the Future at Its User Conference and Analyst Day

Every major supplier has its user event. This is usually where the latest innovations from the company are revealed and progress over the past year is promoted. While there may be user presentations and exhibits, the primary focus is typically the vendor communicating its messages to the user base. The upcoming PDF Solutions Users Conference & Analyst Day is different. The tagline for the event is Shaping Tomorrow’s Semiconductor Ecosystem— Together.

The last part is key. PDF has assembled a diverse group of senior executives from across the semiconductor ecosystem at this event. The presentations will be compelling, with a primary focus on how the entire group is collaborating with PDF to catalyze a new direction for the semiconductor industry. This focus on collaboration to change the future is unique to PDF and quite potent in its goals. Let’s look at how PDF Solutions charts a course for the future at its User Conference and Analyst Day. That theme was already present in PDF CEO John Kibarian’s keynote at the recent SEMICON West event which I covered a few weeks ago. You can find my perspective on the keynote here and the content of his keynote here.

Event Overview

The graphic at the top of this post provides the dates and location for the event. A registration link is coming, but let’s first look at what’s in store when you attend.

On the event webpage, PDF points out that the semiconductor industry is experiencing accelerated innovation. Further to this point demand has never been higher, complexity never greater, and the opportunities never more exciting. A critical observation is that realizing this expanded potential will require partnerships, shared secure scalable solutions, and a collective commitment to pushing boundaries.

With this backdrop, PDF has assembled a world-class group of industry executives for the featured presentations. Below are the folks currently listed. This is an impressive assembly of visionary leaders.

Featured Event Speakers

After cocktails and dinner on the first day of the event, attendees will be treated to a fireside chat with Tom Caulfield, Jean-Marc Chery and John Kibarian. In my experience, these informal discussions yield significant and actionable information.

PDF promises to demo breakthrough technologies in AI-driven manufacturing, equipment connectivity, and yield optimization at the event. Real case studies will also be presented that showcase measurable impact from technology development to high-volume production. These case studies will span fabless to foundries and assembly and test.

There will also be demo kiosks at the event that cover:

  • Enterprise Integration / Operational Product Costing
  • Exensio Studio AI Solution
  • Next Generation Equipment Control and Connectivity
  • Guided Analytics Solution
  • Remote Equipment Connectivity & Control for PDF eProbe Using secureWISE Solution

A Closer Look at the Event

Dr. Christophe Begue

You can peruse the detailed agenda on the event website. Links are coming. I had the opportunity to chat with Dr. Christophe Begue, VP of corporate strategic marketing at PDF. He provided some additional details about the event.

Christophe explained that he sees PDF Solutions as the convener for the semiconductor industry, bringing companies from the ecosystem together with a shared vision to improve the process. He pointed out that the extensive data engine that PDF has developed becomes a critical tool to allow this work to occur.

He listed three main themes for the 2025 PDF Solutions Users Conference that capture this sentiment:

  1. Cross industry collaboration, execution at scale
  2. Industrial applications of AI, first and foremost, is about data
  3. Connectivity, security and trust are best delivered from a neutral industry platform

He also pointed out that not all the participants at the conference are PDF customers. The footprint that PDF Solutions is creating goes beyond just a customer/supplier relationship.

Christophe provided some details about the presentations that will be part of the two-day event. Beyond the previously mentioned industry keynotes, there will discussions of how to

accelerate digital transformation in semiconductor manufacturing. PDF’s eProbe solution will also be discussed, with details on the technology, adoption, business model, and a real PDF end-to-end solution. There will also be a deep dive on PDF’s technical strategy.

PDF’s equipment and fab integration solutions will be presented, with details of fab data infrastructure and manufacturing analytics solutions. How PDF’s Exensio enables advanced test will also be presented with examples.

This is a bit more detail of a full and robust two-day agenda. No matter what part of the ecosystem you are working in, you’ll find important and actionable information at this event.

More Details and How to Register

I highly recommend you attend this event. This is the future of the semiconductor industry. You can see an overview of the event here. Some more details of the event can be found here.  And you can purchase a ticket for the entire event here. 

The conference will be held at the Santa Clara Marriott. You can find details about the location and reservations here. Do it today! And that’s how PDF Solutions charts a course for the future at its User Conference and Analyst Day.

 

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TCAD Update from Synopsys

TCAD Update from Synopsys
by Daniel Payne on 11-03-2025 at 10:00 am
Categories: EDA, Synopsys

TCAD importance min

We live in an exploding AI world, and this has put pressure on foundries to deliver new products faster than ever before. Any help to accelerate the semiconductor R&D goes a long way to make the life of Fab engineers easier. EDA tools in the TCAD (Technology Computer Aided Design) category are critical for TCAD engineers to accelerating R&D by simulating semiconductor process and devices before anything is manufactured in the Fab. TCAD engineers work with process, integration, and device engineers to provide critical insight into semiconductor manufacturing to reduce R&D cost, optimize the technology node and product faster, and make foundry more profitable.

Synopsys is the industry-leader for TCAD tools, and its Sentaurus suite of TCAD products are considered as the gold standard. One of the main challenges of TCAD engineers is to calibrate the tools to manufacturing data and improve accuracy for their workflows. I recently attended a webinar on Sentaurus Calibration Workbench (SCW), which is one of the recent TCAD tools from Synopsys, that uses ML to help TCAD engineers automate the calibration.

The first time that I heard about Sentaurus it reminded me of the galaxy named Centaurus.

This webinar had three Synopsys people presenting:

  • Saurabh Suryavanshi, Product Manager
  • Youngkwon Cho, Senior Staff Engineer
  • Dipanjan Basu, Principal Engineer

Saurabh explained that TCAD tools provide physics-based directionality and helps engineers perform “what-if” analysis during early stages of R&D. Furthermore, by calibrating the TCAD tools to experimental data the users can improve the accuracy of the models and use the TCAD simulations to supplement wafer-based learning during Technology development and Process Ramp. Calibration of TCAD tools, essentially further elevates the value provided by TCAD tool from “what-if” analysis to improving the efficiency of Fab by reducing R&D cost and time to market.

In the past, TCAD engineers primarily relied on manual methods for calibration, but that approach took too much time and provided sub-optimal results, because it is a complex task and provided little exploration of the parameter space. A newer approach for calibration proposed by Synopsys uses  automation by having re-usable workflows with expert modules, adopting the Python language and a simple GUI to improve ease of use, and shortening the calibration time with gradient-based and Machine Learning (ML) algorithms.

Here is what an end-to-end calibration workflow looks like –

The Sentaurus Calibration Workbench helps a TCAD engineer navigate the end-to-end calibration workflow by helping with set up and execution of the calibration workflow, from data preparation to workflow setup to execution to evaluating the results.

Youngkwon showed how you can prepare a new project from a Sentaurus Workbench (SWB) parent deck in developing a calibration workflow, then use that in SCW. For the calibration workflow setup phase, you can use both the tool GUI and a Python API. SCW provides both gradients based as well as machine learning model for calibration.

Synopsys has adopted and enhanced open-source models for the ML-based workflows. SCW provides support to both expert users as well as new users by supported low-level as well as high level ML models.  In addition, Synopsys provides expert written application notes that provide an end-to-end calibration workflow for critical calibration applications such as CMOS and SIMS. The high-level ML model as well as application notes provide a quick start-up option for users. For expert users, SCW also allows users to bring in their own custom model written either in PyTorch or TensorFlow.

For ML-based workflow, you define the DOE and optimize the number of simulations. Furthermore, the user can run sensitivity analysis to identify most critical parameters. Youngkwon highlighted these two features as most critical for reducing the time to calibration.

The final phase of using SCW is the result evaluation where ML visualization provides interactive graphs for advanced analytics, plus you may create custom tasks with your own ML models. With learning curve analysis, you examine how model scores change with training set size. The DOE map function examines the error distributions, finding areas of low predictive power. On the parallel coordinates plot it shows optimal conditions or finds outliers through the connections between input and output.

Dipanjan shared key use-cases on CMOS calibration, 1D SIMS calibrations, hierarchical model calibration, and mobility calibration in GaN devices. All these applications are available for existing users through SolvNet. The CMOS calibration, which usually involves dozens of parameters, showed the true power of workflow automation provided by SCW. The entire calibration was divided into 5 workflows, where parameters were calibrated one step. The SIMS calibration is a great example of using SCW to not-only handle multiple parameters but also multiple targets and multiple implant species. The final validation step re-runs the TCAD simulation with the calibrated parameters to evaluate the model, showing that the model fits closely with experimental data post-calibration as shown by the figure below.

Dipanjan also shared Hierarchical modeling using the Garand Monte Carlo (GMC) in the Sentaurus Device (S-Device) tool was presented for 3D structures. This was a unique case, where calibration is not done against the experimental data but between two modeling frameworks.  Such calibration allows users to attain accuracy of GMC simulation, while maintaining the speed of continuum modeling in S-Device.

Towards the end, Saurabh shared three customer success stories. In the first story, he showed an order of magnitude improvement in calibration at a memory customer. This was possible by following the right practices throughout the end-to-end calibration workflow and utilizing SCW as prescribed in the workflow. He also shared a success story at an advanced logic customer, where they had a 3X improvement in simulation time by moving from gradient-based calibration to ML-based calibration. Lastly, he shared the success at a mature node customer where the calibration was impossible by manual methods. They used SCW to define an iterative flow and used ML to achieve calibration with mere low hundreds of DOE simulations. All these success stories showed significant quality of result while helping users to reduce the time-to-calibration.

Summary

Device and process development are daunting tasks for foundries to undertake, so any automation is welcomed to speed up TCAD simulations. Synopsys has responded to this challenge by bringing ML technology into the TCAD calibration flow in their Sentaurus Calibration Workbench (SCW) tool, bringing about 10X faster time to results even with more than 50 parameters. This tool is widely application across the industry including memory, logic, as well as specialty device manufacturer.

View the archived webinar online.

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Synopsys and NVIDIA Forge AI Powered Future for Chip Design and Multiphysics Simulation

Synopsys and NVIDIA Forge AI Powered Future for Chip Design and Multiphysics Simulation
by Daniel Nenni on 11-03-2025 at 6:00 am
Categories: AI, EDA, Synopsys

Synopsys Nvidia Agentic AI 2025

In a landmark announcement at NVIDIA’s GTC Washington, D.C. conference Synopsys unveiled deepened collaborations with NVIDIA to revolutionize semiconductor design and engineering through agentic AI, GPU-accelerated computing, and AI-driven physics simulations. This partnership, building on over three decades of joint innovation, integrates Synopsys’ expansive portfolio (now bolstered by its recent acquisition of Ansys) with NVIDIA’s cutting-edge AI and GPU technologies.

The goal: empower engineers to tackle unprecedented challenges in chip design, manufacturing, and system-level simulations with unprecedented speed, accuracy, and intuition.

At the heart of the announcement is agentic AI for next-generation semiconductor development. Synopsys is fusing its AgentEngineer™ technology with NVIDIA’s NeMo Agent Toolkit, incorporating Nemotron open models and datasets. This synergy supercharges autonomous design flows, transforming AI from a mere tool into a collaborative partner that optimizes workflows, enhances productivity, and accelerates time-to-market. For instance, Synopsys’ chip design agents, currently in development, streamline formal verification processes. These agents deepen signoff efficiency, uncover critical bugs overlooked by human reviewers, and boost overall design quality. NVIDIA is piloting this AgentEngineer tech for AI-enabled formal verification, underscoring its practical impact on advanced node processes like 2nm and beyond. By automating repetitive tasks and providing intelligent insights, agentic AI addresses the escalating complexity of AI chips, where design cycles have ballooned amid exploding transistor counts and power constraints.

Complementing this is accelerated computing, leveraging NVIDIA’s GPU prowess to turbocharge Synopsys’ software suite, the industry’s broadest, spanning nearly 20 GPU-optimized products. Synopsys is expanding integrations for compute-intensive workloads, including EDA, test, and manufacturing tools. A standout example is Ansys Fluent® computational fluid dynamics (CFD) software, which achieves a staggering 500x speedup via GPU acceleration and AI initialization for fluid simulations, vital for thermal management in high-performance AI data centers. Similarly, Synopsys QuantumATK® for atomistic simulations delivers up to 15x performance gains using NVIDIA libraries and GPUs, rendered seamlessly in NVIDIA Omniverse for immersive visualization. These enhancements extend to computational lithography, where Synopsys’ OPC software on NVIDIA’s cuLitho platform slashes runtime compared to CPU-based methods, enabling TSMC and others to push physics limits for sub-2nm nodes. The result? Faster iterations, reduced energy consumption, and scalable simulations for everything from quantum devices to hyperscale systems.

The third pillar, AI physics, merges NVIDIA’s AI physics engines with Synopsys’ simulation tools to model real-world complexities with extraordinary fidelity. Engineers can now simulate atomic-scale semiconductor behaviors or macro-scale phenomena like aircraft aerodynamics in Omniverse, blending physics-based accuracy with AI’s predictive power. “With NVIDIA AI physics technologies and agentic AI integrated within Synopsys tools, engineers are empowered to simulate the complexities of the real world with extraordinary fidelity and speed,” stated Synopsys executives. This is particularly transformative for automotive and aerospace, where Synopsys’ digital twin solutions—integrated with Omniverse—validate software-defined vehicles pre-manufacturing, slashing costs and enhancing safety.

These collaborations arrive at a pivotal moment. The semiconductor industry faces mounting pressures: AI demand surges transistor densities, geopolitical tensions strain supply chains, and sustainability mandates demand efficient designs. Synopsys’ post-Ansys portfolio spans silicon-to-systems, from EDA to multiphysics, positioning it to unlock insights across scales. NVIDIA’s Blackwell GPUs and CUDA-X libraries further amplify this, with Synopsys adopting them for TCAD and lithography to yield “unprecedented performance gains,” per Sanjay Bali, Synopsys’ SVP of strategy.

The implications ripple outward. For chipmakers like TSMC and Intel, agentic AI means fewer design respins and quicker innovation ramps. In automotive, Omniverse-enabled twins could halve validation times for Level 4 autonomy. Broader industries, from energy to healthcare, benefit as AI physics democratizes high-fidelity modeling. Yet challenges remain: ensuring AI agents’ trustworthiness in safety-critical apps and scaling GPU infrastructure amid chip shortages.

Bottom line: This NVIDIA-Synopsys alliance heralds an era where engineering is intuitive and boundary-pushing. By weaving agentic AI’s autonomy, accelerated computing’s velocity, and AI physics’ precision, it promises to fuel the next industrial revolution—one where silicon dreams become reality faster than ever.

Also Read:

Chiplets: Powering the Next Generation of AI Systems

The Rise, Fall, and Rebirth of In-Circuit Emulation: Real-World Case Studies (Part 2 of 2)

Statically Verifying RTL Connectivity with Synopsys

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IEDM 2025 and the 100th Anniversary of the FET

IEDM 2025 and the 100th Anniversary of the FET
by Daniel Nenni on 11-02-2025 at 10:00 am
Categories: Events

IEDM 2025 SemiWiki

The International Electron Devices Meeting (IEDM) is the world’s preeminent forum for unveiling breakthroughs in semiconductor and electronic device technology, manufacturing, design, physics, modeling, and circuit integration. Sponsored by the IEEE Electron Devices Society, it has been a cornerstone event since 1955, attracting thousands of researchers, engineers, and industry leaders annually to discuss innovations that drive the electronics industry forward. As we approach its 71st edition, IEDM 2025 promises to be particularly momentous, commemorating the 100th anniversary of the field-effect transistor (FET), a foundational invention patented in 1925 that revolutionized modern computing and electronics.

Scheduled for December 6-10, 2025, at the Hilton San Francisco Union Square in San Francisco, California, the conference adopts the theme “100 YEARS of FETs: SHAPING the FUTURE of DEVICE INNOVATIONS.” This milestone edition will blend retrospective insights with forward-looking advancements, emphasizing how FETs and their evolutions continue to enable emerging technologies like AI, quantum computing, and sustainable electronics. Attendees can expect a hybrid format, with in-person sessions complemented by on-demand access to recorded presentations post-event, ensuring global participation.

The program is rich and diverse, featuring over 220 presentations, including invited and contributed papers. Highlights include three plenary talks by renowned experts, offering high-level perspectives on industry trends. Six tutorials on Saturday, December 6, will provide foundational knowledge for newcomers and specialists alike, while two short courses on Sunday, December 7, delve deeper into cutting-edge topics. Evening panel discussions will foster debate on pressing challenges, and exhibits from December 8-10 showcase the latest tools and products from sponsors.

A standout feature is the five special focus sessions, curated to address timely themes:

  • Emerging Neural Interface Technologies for Human Interface, exploring bio-electronic bridges between biology and electronics.
  • AI Memory: Technology and Architecture, focusing on efficient solutions for AI workloads through innovations in memory and logic.
  • Leading Semiconductor Products and Advanced Packaging, highlighting integration strategies for next-gen chips.
  • Emerging Power Electronic Devices and Integration for a Sustainable Society, addressing energy-efficient power systems for mobility and grids.
  • IEDM’s Finest Innovations: A Retrospective Leading to the Future, reflecting on historical breakthroughs to inspire tomorrow’s devices.

These sessions underscore IEDM’s role in tackling global challenges, from AI efficiency and beyond-silicon materials to neuromorphic computing and eco-friendly power devices.

The call for papers, issued in May 2025, invites original work across nine technical areas, including Advanced Logic Technology, Emerging Device and Compute Technology, Memory Technology, and more. Emphasis is on novel results, with strict anti-plagiarism policies and requirements for in-person presentations. Student papers are encouraged, with awards and travel support available.

Bottom line: IEDM 2025’s significance lies in its timing amid rapid advancements in semiconductors, driven by demands for AI, 5G/6G, and electrification. By gathering academia, industry, and government, it accelerates technology transfer, fostering collaborations that could define the next century of device innovation. Whether you’re a researcher presenting groundbreaking work or an executive scouting trends, this conference is essential for staying at the forefront of electron devices. With its blend of history and futurism, IEDM 2025 not only celebrates the FET’s legacy but also charts paths to sustainable, intelligent electronics that will transform society.

I hope to see you there!

Registration Details

Also Read:

Breaking the Thermal Wall: TSMC Demonstrates Direct-to-Silicon Liquid Cooling on CoWoS®

How the Father of FinFETs Helped Save Moore’s Law

Revolutionizing AI Infrastructure: Alchip and Ayar Labs’ Co-Packaged Optics Breakthrough at TSMC OIP 2025