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CEO Interview with Wilfred Gomes of Mueon Corporation

CEO Interview with Wilfred Gomes of Mueon Corporation
by Daniel Nenni on 10-27-2025 at 2:00 pm

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Wilfred Gomes is the co-founder, CEO, and president of Mueon Corporation, a next-generation infrastructure startup rethinking how data centers are built for the AI era. The company’s flagship innovation, Cubelets™, modular, stackable units that unite compute, memory, power delivery and thermal management, replace the traditional rack-based model that have dominated data centers since their inception, enabling up to 10x gains in density, energy efficiency and deployment speed.

He served as a Fellow in Microprocessor Design and Technologies at Intel for nearly three decades, where he drove innovations in advanced packaging, EDA for data center, AI, and client platforms, with a focus on logic, memory and implementation efficiency. He was a co-inventor of Intel’s Foveros 3D integration platform and was instrumental in bringing 3D stacking into mainstream production. With over 250 patents across high-performance CPU and GPU design, Wilfred has played a pivotal role in charting the path toward the next era of AI-scale workloads.

Tell us about your company?

Mueon is redefining how modern data centers are built for the AI era. Founded with the belief that the core infrastructure of computing requires a fundamental change, Mueon is creating a new architectural foundation that unites compute, memory, power delivery, and thermal management into a single, modular system. Our flagship innovation, Cubelets™, replaces the traditional rack-based model that has dominated data centers since its inception, removing the current limits that constrain how silicon systems are built and scaled. Mueon is focused on making data centers more efficient, reliable, powerful, and significantly scalable, while reducing their carbon footprint.

What problems are you solving? 

The AI era has pushed data centers to their physical and architectural limits. Power, cost, and complexity are now critical bottlenecks holding AI innovation back. Traditional rack-based systems draw enormous amounts of electricity, generate heat that’s increasingly difficult to manage, and are expensive and slow to scale. Even with massive investment, operators are running into physical limits on how much performance they can extract from traditional architectures.

A major part of the problem lies in the memory hierarchy itself. Today’s compute systems treat memory as a fragmented stack, forcing data to constantly move between layers and adding latency, inefficiencies, and extra costs. Everyone wants memory that’s 10-100 times larger and faster, but no technology exists today to make that possible.

At Mueon, we’re rethinking this from the ground up. Our Cubelet architecture integrates compute, memory, power delivery, and thermal management into a single modular unit designed to bring data and compute closer together – creating high bandwidth and low latency domains. In practice, that means memory that behaves as a single, instantly accessible pool, a capability no traditional system can match. The result is a new class of data infrastructure that eliminates the tradeoffs between power, cost, and performance, and sets the foundation for computing systems with no architectural ceiling.

What application areas are your strongest?

Mueon’s strongest application areas center on three tightly linked domains: memory, power delivery, and thermal management. These are not independent domains; they have to be addressed together. At scale, each one affects the others, and true performance gains come through co-optimization. Mueon’s Cubelet architecture was built precisely for that intersection. By integrating and co-designing these three elements within a single system, Cubelets achieve breakthroughs that aren’t possible in legacy architectures, giving us a clear edge in scaling AI systems. Memory performance improves because power and cooling are managed at the chip and module level. Power efficiency increases because heat is dissipated intelligently. Thermal balance is maintained because compute, memory, and power delivery are treated as a unified whole.

This requires a fundamental change in architecture, one that brings the right technologies together in the right way. Our success comes from applying this co-optimization framework across every layer of the stack, enabling higher density, efficiency, and scalability, while remaining fully compatible with existing AI and cloud software environments.

What keeps your customers up at night?

Our customers are grappling with the realities of scaling infrastructure in the AI era, and their concerns can be summarized into three key areas: power, cost, and complexity.

Power – AI workloads are expanding so quickly that operators are running into challenges with electricity and cooling capacity. Without new approaches, operators risk hitting unscalable ceilings. Even with major investment, the physical and environmental limits of current data centers make it increasingly difficult to scale.

Cost – Building large-scale systems requires billions in capital for servers, power, cooling, networking, and real estate. Customers fear that these investments may not keep pace with AI’s rapidly changing demands, leaving them with stranded assets that are costly to operate and unable to deliver the performance they need.

Complexity – Coordinating compute, memory, power, and thermal management across tens of thousands of racks is a daunting engineering challenge. This slows development cycles, increases operational risk, and leaves customers feeling that AI innovation is outpacing their ability to adapt.

Mueon removes these limits; our Cubelet architecture integrates compute, memory, power, and thermal management into a single modular system, lowering costs, simplifying operations, and enabling AI infrastructure to scale efficiently.

What does the competitive landscape look like and how do you differentiate?

Much of the industry is still focused on extracting marginal gains from the same rack-based paradigm that has defined data centers for decades. Traditional OEMs and hyper-scalers push for incremental improvements in chip performance, cooling, or energy use, but they’re constrained by the physical and architectural limits of the rack. Some companies explore new cooling methods or form factors, but most solve for one layer of the problem rather than redefining the full system.

At Mueon, we see this as a moment to move beyond incremental improvements to redefine how entire systems are built. Moore’s Law has driven extraordinary advances at the silicon level, but it hasn’t been matched by equivalent innovation in how systems are built and scaled. We believe the next leap in computing performance will come from rethinking those abstractions – from chip to system to data center.

Our Cubelets architecture embodies that leap. By integrating compute, memory, power delivery, and thermal management into a single modular unit, we eliminate the artificial boundaries that slow innovation. This architecture delivers order-of-magnitude gains in density, deployment speed, and energy efficiency, while remaining compatible with today’s AI and cloud software stacks. Mueon is leading the next wave of abstraction, one of the first to deliver a fundamentally new model for building data centers in the AI age.

What new features/technology are you working on?

Our goal is to remove the physical limits that have constrained how silicon systems are built and scaled; there should be no limit to how large or how complex a chip can be. We’re developing technology that allows silicon to be built, stacked, and interconnected at unprecedented scale – whether that means going smaller or larger.

Scaling Down – Pushing toward the smallest possible dimensions for compute, memory, and interconnects to maximize efficiency and density.

Scaling Up – Enabling arbitrarily large chips and multi-layered stacking architectures that operate as a single coherent system.

Together, these dimensions unlock new possibilities for performance, efficiency, and system design. By breaking free from traditional limits on packaging and processing, Mueon is creating a foundation where compute can expand organically – without the bottlenecks that defined the last generation of data center architecture. We’re not just enabling faster chips, we’re creating the foundation for entirely new classes of computing.

How do customers normally engage with your company?

Right now, most of our engagements are with leading AI companies and hyperscalers that are actively building the next generation of AI chips and data infrastructure. These organizations are deeply aligned with our mission to remove the limits on how silicon can be designed, scaled, and deployed. We’re working closely with them to co-develop systems that push the boundaries of performance and efficiency.

We welcome conversations with anyone tackling similar challenges or exploring new chip models. Collaboration is core to how we operate, whether you’re building advanced AI systems, experimenting with chip architectures, or simply have ideas about where silicon design should go next.

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Pioneering Edge AI: TekStart’s Cognitum Processor Ushers in a New Era of Efficient Intelligence

Pioneering Edge AI: TekStart’s Cognitum Processor Ushers in a New Era of Efficient Intelligence
by Daniel Nenni on 10-27-2025 at 10:00 am

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One of the more in interesting companies I met at the AI Infra Summit was a company known to me for some time. The most interesting part was the chip they are in the process of taping out; It is a high-performance, ultra-low-power AI processor purpose-built for edge computing. It is claimed to deliver “the processing muscle to run advanced AI inference directly where data is generated without the energy burden that typically comes with it.”

In an era where artificial intelligence is no longer confined to data centers but embedded in the fabric of everyday devices, power efficiency and real-time performance stand as the ultimate battlegrounds. TekStart Group, a trailblazing venture studio founded in 1998, has long championed the transformation of raw technological innovation into market-dominating realities. With a track record of developing, funding, and exiting over 120 companies, TekStart’s ChipStart® division specializes in custom ASIC design and outsourced operations, bridging the gap between concept and commercialization. Headquartered in Burlington, Ontario, with global R&D hubs in Irvine, California, and Kyiv, Ukraine—plus offices across the UK, France, Japan, and the US—the company operates as a nexus for innovators, turning breakthroughs into scalable successes.

At the forefront of this mission is Cognitum, ChipStart’s groundbreaking Edge AI processor unveiled in September 2025. Designed explicitly for the exigencies of edge computing, Cognitum delivers an industry-leading 65 TOPS (tera operations per second) peak performance while consuming under 2 watts—redefining the performance-to-power ratio. In a market overview matrix, Cognitum eclipses competitors like BrainChip’s Akida, Hailo processors, and even Qualcomm’s Snapdragon in the ultra-low-power quadrant, positioning it as the “sweet spot” for high-performance edge AI without the thermal and efficiency pitfalls of legacy solutions. This isn’t incremental improvement; it’s a paradigm shift, addressing core Edge AI challenges: the demand for ultra-low-power, on-device learning; real-time inference for latency-sensitive applications; and the scaling of deep neural networks (DNNs) that once required cloud dependency.

Cognitum’s architecture is a masterclass in versatility, one unified design that scales seamlessly across edge devices and nodes, infusing remote intelligence into diverse ecosystems. For security applications, its sub-2W footprint enables always-on monitoring in surveillance cameras, efficiently streaming inferences for continuous threat detection without power drain. Lower power means cooler operation, extending device lifespan, while flexible multi-model switching allows real-time adaptation between facial recognition, object detection, or event analysis ideal for retail, public safety, and smart city platforms.

In agriculture (AgTech), Cognitum empowers solar- or battery-operated field devices, supporting energy-efficient intelligence for crop surveillance drones and livestock monitoring. Farmers can fine-tune models to local conditions like soil types and weather patterns, reducing maintenance needs and runtime servicing. A single processor sustains adaptive AI in harsh environments, slashing operational costs and boosting yields through proactive insights.

Wearables and AR/VR headsets benefit from Cognitum’s modular, embeddable silicon, optimized for vision and biometric workloads. Its all-day performance extends battery life in fitness trackers and immersive devices, while immersing users in gesture, vital signs, and motion AI—transforming wearables from passive gadgets into proactive companions.

Industrial automation sees Cognitum as a retrofit powerhouse, integrating legacy and next-gen systems for unified shop-floor management. Predictive analytics fused with vision AI enable real-time decision-making, improving uptime in Industry 4.0 setups. Durable, efficient nodes keep robotic arms and IoT sensors running longer, minimizing downtime in predictive maintenance.

Looking ahead, Cognitum is primed to power the future of agentic AI—systems that are proactive, autonomous, targeted, and collaborative via the PACT framework. As rUv, a leading AI innovator, proclaimed in August 2025:

“Building a neural network with cost-effective, ultra-low-power Edge AI inferencing nodes is a game-changer!”

With highly scalable, cost-effective connectivity and ultra-low-power nodes, Cognitum supports expansive AI clusters without the energy overhead of traditional copper interconnects.

TekStart’s ethos empowering innovators through ChipStart’s accelerated silicon success shines in Cognitum. It redefines Edge AI as accessible, efficient, and boundless, fostering new possibilities in surveillance, AgTech, wearables, and industrial realms. As Gordon Benzie, VP of Marketing, invites: Reach out at gordon@tekstart.com to explore how Cognitum can electrify your next breakthrough.

Bottom line: In a world racing toward intelligent edges, TekStart isn’t just building processors—it’s architecting the intelligent tomorrow.

For more information contact TekStart.

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CEO Interview with Howard Pakosh of TekStart

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CAST Simplifies RISC-V Embedded Processor IP Adoption with New Catalyst Program

CAST Simplifies RISC-V Embedded Processor IP Adoption with New Catalyst Program
by Daniel Nenni on 10-26-2025 at 10:00 am

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In a move poised to accelerate the integration of open-source processor architectures into resource-constrained devices, semiconductor IP provider CAST, Inc. unveiled its Catalyst™ Program at the RISC-V Summit in Santa Clara, California. This initiative addresses a persistent pain point for embedded system developers: the overwhelming configurability of RISC-V processors. By offering pre-tuned, ready-to-deploy IP cores alongside flexible licensing and expert support, CAST aims to strip away the complexity, enabling faster prototyping and deployment in low-power, cost-sensitive applications like IoT sensors, wearables, and industrial controllers.

RISC-V, the royalty-free instruction set architecture, has exploded in popularity since its inception in 2010, promising customization and vendor neutrality in a market dominated by proprietary cores from Arm and others. Yet, its flexibility with hundreds of extensions and options can paralyze small teams lacking deep expertise. CAST, a veteran IP firm founded in 1993 with a portfolio spanning processors, security modules, and interfaces, leverages its 30 years of experience to bridge this gap. Sourcing cores from partners like Beyond Semiconductor and Fraunhofer IPMS, the Catalyst Program delivers silicon-proven 32-bit RISC-V solutions optimized for embedded realities, not exhaustive versatility.

At the heart of Catalyst are five meticulously preconfigured processor cores, each tailored to distinct embedded use cases. These eliminate the “configuration overload” that Bill Finch, CAST’s senior business development vice president, describes as unnecessary for 90% of developers.

The lineup spans from ultra-minimalist to feature-rich designs:
  • BA5x-TN: A tiny MCU-class core (~17k gates) for basic control tasks, such as sensor hubs or always-on logic, serving as a seamless 8/16-bit replacement with robust performance in minimal silicon area.
  • BA5x-LP: A low-power workhorse with configurable caches, interrupts, and bus interfaces, ideal for general-purpose industrial systems demanding balanced efficiency.
  • BA5x-CM: RTOS-ready with hardware floating-point and atomic operations, targeting connected IoT and wearables where multitasking meets real-time constraints.
  • BA5x-EP: An edge powerhouse featuring dual/single-precision FPU, MMU, and optional hypervisor for secure, multi-OS environments in gateways or complex controllers.
  • EMSA5-GP: Vector-enhanced for parallel workloads like FFTs, sensor fusion, and packet processing, adding RISC-V Vector extension subsets without bloating area.

These cores promise predictable power, performance, and area metrics, verified through CAST’s rigorous validation. Developers can integrate them into ASICs or FPGAs immediately, bypassing weeks of tweaking.

What truly distinguishes Catalyst is its risk-mitigating ecosystem. Licensing flips the traditional model: no upfront fees for full-featured evaluation kits, allowing simulation, benchmarking, and design integration sans commitment. Only upon production commitment does the fee apply, with transparent terms, no royalties, and optional extended support. Direct access to CAST’s senior engineers during evaluation, guiding customization and tuning, ensures smooth onboarding. As Evan Price, CAST’s RISC-V product manager, puts it: “Catalyst reduces complications to let embedded system teams focus on innovation… without surprises.”

This program arrives at a pivotal moment. The embedded market, projected to exceed $150 billion by 2030, demands RISC-V’s cost advantages amid supply chain volatility and geopolitical tensions over proprietary IP. Yet adoption lags in ultra-low-power segments due to integration hurdles. Catalyst democratizes access, potentially slashing time-to-market by months and lowering barriers for startups and mid-tier firms. Early adopters could see 20-30% area reductions versus over-configured alternatives, per CAST benchmarks, while inheriting battle-tested reliability from hundreds of global deployments.

Bottom line:  CAST’s Catalyst Program isn’t mere IP; it’s a launchpad for RISC-V’s embedded renaissance. By fusing proven tech with developer-friendly economics, it could catalyze widespread adoption, fostering innovation in edge AI, smart cities, and beyond. As the industry pivots to open architectures, programs like this ensure no team is left configuring in the dark. For details, visit CAST’s RISC-V page or reach out to their sales team—your next embedded breakthrough awaits.

Contact CAST Here

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Podcast EP273: An Overview of the RISC-V Market and CAST’s unique Abilities to Grow the Market with Evan Price


Podcast EP313: How proteanTecs Optimizes Production Test

Podcast EP313: How proteanTecs Optimizes Production Test
by Daniel Nenni on 10-24-2025 at 10:00 am

Daniel is joined by Alex Burlak is Vice President of Test & Analytics at proteanTecs. With combined expertise in production testing and data analytics of ICs and system products, Alex joined proteanTecs in October, 2018. Before joining the company, Alex held a Senior Director of Interconnect and Silicon Photonics Product Engineering positions at Mellanox.

Dan explores the changing landscape of production testing with Alex, who explains that the current method of pass/fail testing doesn’t work well on the very large, chiplet-based designs of today. He describes a new approach from proteanTecs that utilizes detailed parametric data to increase visibility and optimize performance.

Alex explains how using proteanTecs embedded agents allows better understanding of parametric quality as well as the opportunity to optimize performance. He describes how the technology supports real-time decisions at the chip level and also allows system-wide analysis on the cloud to achieve better quality and reliability. Alex also discusses trends in this area and where he sees adoption and growth.

Contact proteanTecs

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.


CEO Interview with Alex Demkov of La Luce Cristallina

CEO Interview with Alex Demkov of La Luce Cristallina
by Daniel Nenni on 10-24-2025 at 8:00 am

Alex and Agham 8 Inch

Alex Demkov is co-founder and CEO of La Luce Cristallina. He is a distinguished figure in the field of materials physics, serving as a Professor at the University of Texas at Austin. With a prolific career marked by notable achievements, Alex boasts an impressive portfolio of 10 U.S. patents and many patent applications, showcasing his innovative contributions to the field. He has published almost three hundred research papers, several books, and is a Fellow of the American Physical Society and a Senior Member of IEEE. Alex received his Ph.D. in Physics from Arizona State University. Prior to joining the University of Texas in 2005, he worked in Motorola’s R&D organizations. His expertise extends globally, positioning him as an international authority and thought leader in the crucial domain of semiconductor manufacturing materials.

Can you tell us about your company?

La Luce Cristallina (LC) transforms over two decades of research into 200-mm (8-inch) barium titanate (BaTiO₃) wafers that overcome the performance, space, and power limitations of silicon-photonics modulators. Using RF magnetron sputtering to grow single-crystal, fully insulating films, we deliver foundry-compatible wafers from a secure U.S.-based supply chain at a scale of multiple 200-mm wafers per day. A typical stack includes 300–500 nm BaTiO₃ on top of 6–8 nm SrTiO₃ and 3 µm SiO₂ on a silicon carrier.

What problems are you solving?

Si photonics modulators reached their limits in terms of speed, size, and power consumption. Our 200 mm BaTiO₃ wafers offer many benefits over alternative materials such as lithium niobate, which is prone to contamination issues. They are also more durable than electro-optic polymers and are able to withstand high temperatures, radiation, high frequencies, and other harsh conditions. Our product remains compatible with existing Si and SiN foundry flows, and enables compact, low-drive electro-optic devices.

For example, a sub-500 µm MZI achieves VπL of 0.45 V·cm. BaTiO₃’s exceptionally high Pockels coefficient delivers a much stronger electro-optic response, enabling sub-volt, ultra-compact modulators that lithium niobate cannot match. Our work turns breakthrough research into practical solutions that meet the performance demands of numerous technology sectors.

What application areas are your strongest?

La Luce Cristallina’s solutions directly address the growing need for faster, lower-power optical interconnects in the datacom and data center markets, which currently represent the largest share of integrated silicon photonics demand. Our platform enables compact, efficient devices that support AI-driven workloads and high-density optical interconnects. Beyond data centers, our solutions extend to telecom, sensing, defense, aerospace, and advanced computing applications, including emerging quantum use cases. We empower device manufacturers and system developers to create next-generation electro-optic modulators, PICs, and integrated systems that deliver higher performance and greater reliability across these markets.

What keeps your customers up at night?

Cost is on everyone’s minds, with companies striving to reduce power, space, and OPEX without sacrificing performance. Sourcing and manufacturing through a secure supply chain is also a primary consideration, with many companies evaluating risks from restrictions on thin-film lithium niobate suppliers in China.

What does the competitive landscape look like, and how do you differentiate?

Our 200 mm wafers offer economies of scale at a reasonable price. We differentiate ourselves by offering customers more generations of device innovation (10+ years) than alternative materials. This helps companies secure a higher and quicker return on their investment while positioning them to support the rising bandwidth requirements of current and emerging use cases. BaTiO₃ is still a relative newcomer, but we’re confident its benefits will enable it to outpace indium phosphide, lithium niobate, polymers, and other materials long-term.

What new features/technology are you working on?

We recently launched our new fabrication facility in Austin, TX, and announced the availability of our new 200-mm BaTiO₃ wafers. Our flagship product brings the functionality of crystalline oxides to semiconductors. Through this solution, we’re spearheading the transition from lithium niobate to high-performance BaTiO₃ as numerous sectors work to support optical interconnects, sensing, and optical computing use cases amid rising bandwidth demands.

How do customers normally engage with your company?

Through referrals, our website, our LinkedIn account, or by discovering us in leading industry publications.

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IPLM Today and Tomorrow from Perforce

IPLM Today and Tomorrow from Perforce
by Daniel Nenni on 10-24-2025 at 6:00 am

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Today, Perforce IPLM stands at the intersection of data management, automation, and collaboration, shaping the way companies design the next generation of chips and systems. Looking ahead, its evolution will reflect the growing convergence of hardware, software, and AI-driven engineering.

WEBINAR – Future Forward: IPLM Today and Tomorrow

At its core, Perforce IPLM provides a unified framework for managing semiconductor and embedded IP throughout its lifecycle. It allows design teams to catalog every block, core, and library in a centralized database, complete with metadata, version histories, and dependency maps. This approach replaces the fragmented spreadsheets and manual versioning methods that once plagued engineering organizations. Through its hierarchical BoM capabilities, IPLM gives users visibility into which IPs are used in which projects and how changes in one component ripple through a system. The result is greater design reuse, faster project ramp-up, and reduced risk of costly mismatches or rework.

Perforce IPLM also serves as a bridge between hardware and software development workflows. It integrates with issue tracking systems such as Jira, incorporates permission controls for IP access, and provides traceability from design requirements to implementation. The recent simplification of the product’s branding—from Helix IPLM to Perforce IPLM, reflects a broader strategic vision: unifying the company’s tools under one ecosystem and highlighting the platform’s role in managing not just data, but organizational knowledge.

Perforce has also sought partnerships to expand IPLM’s role beyond traditional semiconductor design. Its collaboration with Siemens Digital Industries Software demonstrates a move toward unifying hardware and software development in an era of software-defined, silicon-enabled products. From autonomous vehicles to AI accelerators, the line between chip design and software architecture is blurring. IPLM’s ability to connect design data across domains positions it as an enabling technology for this convergence.

Looking toward the future, several forces will shape how IPLM evolves. The first is the rise of AI-assisted design. Second, global scalability will be essential. With design teams increasingly distributed across continents, IPLM must ensure secure and performant data access through caching, mirroring, and fine-grained permissions. Built-in compliance controls, such as geofencing and export management, will help companies navigate the complex regulatory landscape of semiconductor trade. A third trend is the growing emphasis on process maturity. Perforce’s collaboration with the Global Semiconductor Alliance on the IP Maturity Model provides a structured path for organizations to assess and improve their IP management practices. As design cycles shorten and product complexity rises, structured maturity frameworks will become essential for maintaining quality and repeatability across projects.

In parallel, the user experience of IPLM is evolving toward greater intuitiveness and interoperability. Engineers increasingly expect the same ease of use from enterprise tools that they enjoy from consumer software. Features such as advanced search filters, “shopping-cart” style IP selection, and visual dashboards are already modernizing how teams interact with data. Future iterations of IPLM will likely offer deeper integration with continuous integration/continuous deployment pipelines and EDA tools, creating a seamless bridge from specification to verification.

WEBINAR – Future Forward: IPLM Today and Tomorrow

Bottom line: The future of Perforce IPLM lies in its ability to act as both a knowledge repository and a collaborative engine. By harnessing AI, strengthening global scalability, and deepening its cross-domain integrations, Perforce is positioning IPLM to become a foundational layer of modern product development. As industries move toward AI-driven, software-defined, and silicon-enabled systems, the need for intelligent, traceable, and automated IP management will only grow. In that landscape, IPLM will not merely track design assets, it will help shape the future of how complex technology is imagined, built, and brought to market.

Also Read:

Chiplets: Powering the Next Generation of AI Systems

Chiplets: Powering the Next Generation of AI Systems
by Kalar Rajendiran on 10-23-2025 at 10:00 am

Arm Synopsys at Chiplet Summit

AI’s rapid expansion is reshaping semiconductor design. The compute and I/O needs of modern AI workloads have outgrown what traditional SoC scaling can deliver. As monolithic dies approach reticle limits, yields drop and costs rise, while analog and I/O circuits gain little from moving to advanced process nodes. To sustain performance growth, the industry is turning to chiplets—modular, scalable building blocks for multi-die designs that redefine how high-performance systems are built.

Why Chiplets Matter

Forecast to become a $411 billion market by 2035 (IDTechEx), multi-die designs divide large SoC functions into smaller, reusable dies (also called chiplets) that can be integrated into a single system-in-package (SiP). These chiplets may be heterogeneous or homogeneous, replicating cores for scaling. SiPs can rely on standard organic substrates or advanced interposers that enable dense interconnects and greater functionality within a compact footprint.

The vision is an open marketplace where designers can mix and match chiplets from multiple suppliers. Beyond JEDEC’s HBM memory modules, however, widespread adoption of off the shelf chiplets has been limited by fragmented standards and fragmented use cases. Progress continues with UCIe (Universal Chiplet Interconnect Express), Arm’s Chiplet System Architecture (CSA), and new industry collaborations aimed at breaking these barriers.

System Partitioning and Process Node Choices

The first step in chiplet design is deciding how to partition system functions. Compute, I/O, and memory blocks can each be implemented on the process node that offers the best balance of power, performance, and cost. For example, an AI compute die benefits from the latest node, while SRAM or analog functions may be built on less advanced—and less expensive—nodes.

Latency and bandwidth demands guide how these blocks connect. A 2.5D interposer may provide sufficient performance, but latency-sensitive systems sometimes require 3D stacking, as seen in AMD’s Ryzen 7000X3D processors, where compute and cache are vertically integrated for faster data access.

Designing Die-to-Die Connectivity

Interconnect performance defines chiplet success. UCIe has become the industry’s preferred die-to-die standard, offering configurations for both cost-efficient organic substrates and high-density silicon interposers. Designers must weigh data rates, lane counts, and bump pitch to achieve the right mix of bandwidth, area, and power.

AI I/O chiplets, for instance, may require UCIe links supporting 16G–64G data rates to maintain low-latency communication with compute dies. Physical layout choices for interface IPs—single-row or double-stacked PHYs—may affect the beachfront area available for die-to-die interfaces and affect both area efficiency and design complexity.

Bridging UCIe’s streaming interface with on-chip protocols such as AXI, Arm CXS, or PXS is also key to maximizing throughput and minimizing wasted bandwidth.

Advanced Packaging and Integration

Packaging now sits at the heart of semiconductor innovation. Designers must choose between lower-cost organic substrates and denser 2.5D or 3D approaches. Silicon interposers deliver unmatched interconnect density but come with size and cost constraints. Emerging RDL (Redistribution Layer) interposers provide a balanced alternative—supporting larger system integration at reduced cost. Typical bump pitches range from 110–150 microns for substrates to 25–55 microns for interposers, shrinking further for 3D stacks.

Thermal, mechanical, and power-integrity challenges grow as multiple chiplets share one package. Early co-design across silicon and packaging domains is essential. Testability must also be planned in advance, using the IEEE 1838 protocol and multi-chiplet test strategies to ensure known-good-die (KGD) quality before assembly.

Securing and Verifying Multi-Die Designs

With multiple chiplets, the attack surface widens. Each chiplet must be authenticated and protected through attestation and secure boot mechanisms. Depending on the application, designers may integrate a root of trust to manage encryption keys or isolate sensitive workloads.

Data in transit must be secured using standards such as PCIe and CXL Integrity and Data Encryption (IDE), DDR inline memory encryption (IME), or Ethernet MACsec. Verification is equally critical: full-system simulation, emulation, and prototyping are required to validate die interactions before fabrication. Virtual development environments enable parallel software bring-up, shortening time-to-market.

Synopsys and Arm: Simplifying AI Chip Design

AI accelerators bring these challenges into sharp focus. They demand enormous compute density, massive bandwidth, and efficient integration across heterogeneous dies. To address this complexity, Synopsys and Arm—long-time collaborators—are combining their expertise to streamline AI and multi-die development.

At Chiplet Summit 2025, Synopsys VP of Engineering Abhijeet Chakraborty and Arm VP of Marketing Eddie Ramirez discussed how their companies are reducing design risk and speeding delivery. Under  Arm Total Design, Arm’s Neoverse Compute Subsystems (CSS) are now pre-validated with Synopsys IP, while Synopsys has expanded its Virtualizer prototyping solution and Fusion Compiler quick-start flows for the Arm ecosystem. These integrations let customers implement Arm compute cores more efficiently, validate designs earlier, and begin software development long before silicon arrives.

“We feel we are barely scratching the surface,” Chakraborty noted. “There’s a lot more work we can do in this space.” Both leaders emphasized that interoperability, reliability, and security will remain top priorities as chiplet ecosystems evolve.

The Road Ahead

The semiconductor industry is shifting from monolithic to modular design. Continued progress will depend on collaboration, standardization, and shared innovation across companies and ecosystems. With Synopsys advancing chiplet standards, design flows, and verified IP subsystems, the path from concept to production is becoming faster and more predictable. Customers can focus on their core competencies, while offloading other aspects of the design to respective experts in those areas for fast and reliable time-to-market.

The next generation of AI systems won’t rely on bigger chips—they’ll be built from smarter, interconnected chiplets, delivering scalable performance, efficiency, and flexibility for the most demanding compute workloads of the future.

Also Read:

The Rise, Fall, and Rebirth of In-Circuit Emulation: Real-World Case Studies (Part 2 of 2)

Statically Verifying RTL Connectivity with Synopsys

Why Choose PCIe 5.0 for Power, Performance and Bandwidth at the Edge?


Better Automatic Generation of Documentation from RTL Code

Better Automatic Generation of Documentation from RTL Code
by Tom Anderson on 10-23-2025 at 6:00 am

Specador Doc

One technical topic I always find intriguing is the availability of links between documentation and chip design. It used to be simple: there weren’t any. Architects wrote a specification (spec) in text, in Word if they had PCs, or using “troff” or a similar format if they were limited to Unix platforms. Then the hardware designers started drawing schematics or writing RTL code, and the programmers did their thing. Verification and validation were all about making sure everything worked together.

Whenever the specification changed, manual updates to the hardware and software were required. When implementation issues caused the design to differ from the original intent, the impact was rarely reflected back in the spec. Thus, when it came time to produce documentation for the end user, it was a lot of manual work to combine bits of the spec, update to reflect the actual design, and add explanatory material for the target audience.

These days, we have links galore. There are many ways to generate hardware and software code from various specification and documentation formats, plus methods to generate documentation from source code. The former is not a new idea. I remember working on a new processor design around 1988-1989 in which the details of the instruction set changed numerous times. I wrote an “awk” script to automatically generate the Verilog RTL design for the instruction decoder based on a tabular representation of the opcodes and their meanings.

These days, there are lot of pieces in a typical chip that can be generated from various specification formats, such as registers from IP-XACT or SystemRDL and state machines from transition tables. We’re starting to see generative AI spit out even larger chunks of the design, essentially based on natural language specifications in the form of chats. Being able to regenerate RTL code whenever a specification changes saves a great deal of time of effort over the course of a chip project.

Generating documentation from code is also not a new idea. Solutions in this space started on the software side, with tools such as Doxygen. The idea is that certain aspects of the documentation can be generated automatically from the code, with pragmas or some other in-line mechanism available for programmers to control the generation and add content. Numerous options for document generation are now available, with AI-based techniques quickly gaining acceptance. Being able to regenerate documentation every time the source code changes also saves a lot of time and eliminates a lot of manual effort.

From what I can gather, documentation generation from code is very common in the software world. However, I’ve been surprised by how few hardware projects embrace this approach in a big way.  I often hear designers and verification engineers complain that languages such as SystemVerilog are not as well supported by shareware documentation tools. They also say that they don’t have the level of control needed to get the quality of results their end users demand.

AMIQ EDA has a commercial product, Specador Documentation Generator, focused on hardware design and verification code. I figured that there must be some good reasons why their users chose this solution over free utilities, so I chatted with CEO Cristian Amitroaie. The first thing he said was that Specador was created with hardware engineers in mind. It supports source code written in SystemVerilog, Verilog, VHDL, the e language, and more. It covers the RTL design plus the verification testbench, components, models, and tests. It generates both PDF and HTML output.

To me, the most impressive aspect of Specador is that it leverages all the language knowledge available in the AMIQ EDA Design and Verification Tools (DVT) suite. Their front end compiles all the design and verification code and builds a flexible internal model. Users of the integrated development environment DVT IDE can easily browse, edit, and understand the code, and even query the model with AI Assistant.

Understanding the design means, for example, that users can generate design hierarchies, schematics, and state machine diagrams. Since the DVT tools also understand the Universal Verification Methodology (UVM), users can generate class or component diagrams including TLM connections, cross-linked class inheritance trees, and other useful forms of documentation for the testbench. My choice of the word “documentation” here is deliberate, because many of the design and verification diagrams that users might generate within the IDE are also useful as part of user manuals and other chip documentation.

Cristian stressed that Specador (like all their products) uses accurate language parsers to compile the code so that it understands the project structure. Users can employ it to document design or verification environments, even when comments are not present to provide additional context. Of course, Specador also supports the ability to use comments to format documentation and to add content that can’t be inferred from the source code.

I asked Cristian what’s new in Specador, and he mentioned that AMIQ EDA keeps implementing new features and enhancements based on customer feedback. For example, they recently added the ability to quickly preview the documentation directly in the IDE, the ability to apply custom filters when generating schematic or FSM diagrams, the ability to work with Markdown and reStructuredText markup languages, and last but not least the ability to generate documentation using their AI Assistant.

Specador makes it possible for design and verification engineers to easily create and maintain proper and well-organized documentation. Users can control what documentation they create by filtering or selecting elements in the design and testbench. They can quickly embed or link to external documentation. Specador integrates easily into existing development flows, allowing design and verification groups to automate the documentation process.

Above all, Specador keeps the generated documentation in sync with the source code, saving a great deal of maintenance time and effort as the code evolves. I thank Cristian for his time, and recommend looking at the product information, exploring the documentation generated for the Ibex embedded 32-bit RISC-V CPU core, and reading a post on real-world user experience to learn more.

Also Read:

2025 Outlook with Cristian Amitroaie, Founder and CEO of AMIQ EDA

Adding an AI Assistant to a Hardware Language IDE

Writing Better Code More Quickly with an IDE and Linting


FD-SOI: A Cyber-Resilient Substrate for Secure Automotive Electronics

FD-SOI: A Cyber-Resilient Substrate for Secure Automotive Electronics
by Daniel Nenni on 10-22-2025 at 10:00 am

Soitec white paper image

The paper highlights how Fully Depleted Silicon-On-Insulator (FD-SOI) technology provides a robust defense against Laser Fault Injection (LFI), a precise, laboratory-grade attack method that can compromise cryptographic and safety-critical hardware. As vehicles become increasingly digital and connected, with dozens of microcontrollers and over-the-air updates, hardware-level security has become central to automotive cybersecurity standards such as ISO/SAE 21434.

The Rising Threat of Physical Fault Attacks

Physical fault injection attacks (FIA) can bypass secure boot, unlock protected debug ports, and disrupt program flow. Among these, LFI stands out for its precision, using tightly focused near-infrared laser pulses to flip bits or alter circuit timing. While voltage and electromagnetic glitches can occur in the field, LFI remains the gold standard for systematically probing silicon vulnerabilities in controlled laboratory conditions.

As front-side access becomes harder due to thicker metal layers and shielding, back-side laser access through the substrate is increasingly used. This shift makes substrate engineering—the physical foundation of a chip—a critical security factor.

Why FD-SOI Disrupts Laser Attack Mechanisms

FD-SOI differs from bulk CMOS in that its transistors are built on an ultra-thin silicon layer electrically isolated from the main wafer by a buried oxide (BOX). This structural difference eliminates the main LFI fault mechanisms found in bulk silicon.

Four dominant bulk mechanisms are neutralized by FD-SOI:

  1. Drain/body charge collection – FD-SOI’s thin silicon layer and BOX barrier dramatically reduce the photocurrent that lasers generate at PN junctions.

  2. Laser-induced IR-drop – In bulk CMOS, current loops between wells and substrate can cause transient voltage drops. FD-SOI, using isolated body-bias networks, removes this conduction path.

  3. Substrate diffusion and funneling – Charge carriers cannot spread vertically through the BOX, preventing multi-cell upsets and latch-up.

  4. Parasitic bipolar amplification – Only a weak, lateral bipolar effect remains in FD-SOI, which can be further mitigated using reverse body-bias (RBB) to raise the laser energy threshold.

By blocking substrate conduction and confining active regions, FD-SOI significantly reduces the area and energy range vulnerable to laser faults.

Experimental Validation

Experiments comparing 22FDX FD-SOI and 28 nm bulk CMOS devices including D-flip-flops, SRAMs, and AES/ECC crypto cores confirmed the theoretical advantages. In tests, FD-SOI required up to 150× more laser shots to produce the same fault observed in bulk devices. The time-to-first-fault rose from roughly ten minutes to ten hours, while the minimum fault energy threshold increased from 0.3 W to over 0.5 W.

Spatial and depth-sensitivity mapping showed that bulk silicon has wide fault-prone zones, while FD-SOI faults are confined to sub-micron “hotspots” with a narrow focal depth of only about ±1 µm. Attackers must therefore perform ultra-fine spatial scans, drastically increasing effort and cost.

Furthermore, excessive laser power in FD-SOI caused permanent damage or stuck bits effectively creating a natural deterrent since aggressive attempts could destroy the target device.

Implications for Automotive Security Compliance

In the ISO/SAE 21434 framework, reducing attack likelihood directly lowers cybersecurity risk. FD-SOI’s physical resilience therefore simplifies compliance and can help products achieve Common Criteria or SESIP assurance levels (EAL4+ or higher) without extensive additional countermeasures. Because attack duration, equipment complexity, and expertise all increase, FD-SOI provides a quantifiable uplift in assurance for automotive OEMs and tier-one suppliers.

Toward a Next-Generation Secure Substrate

The authors envision extending FD-SOI’s benefits through substrate-level innovation, transforming it from a passive platform into an active cyber-resilient layer. Two emerging techniques are highlighted:

  1. Buried optical barriers—highly doped layers under the BOX that absorb or scatter infrared light, reducing LFI energy transmission while enabling anti-counterfeit watermarking.

  2. Integrated sensors and PUFs (Physically Unclonable Functions) substrate-embedded monitors that detect tampering or derive unique cryptographic identities from manufacturing variations.

Together, these innovations could allow the substrate to detect attacks, react in real time, and cryptographically bind the silicon identity to the vehicle platform.

Bottom line: FD-SOI represents a material-level breakthrough in hardware security. By eliminating substrate pathways exploited in bulk CMOS, it narrows the laser fault window, increases attack complexity, and provides tunable resilience through body-bias control. These benefits align directly with evolving automotive cybersecurity regulations, offering faster certification and lower system costs.

As substrate engineering continues toward integrated optical barriers and anti-tamper features, FD-SOI is poised to become the reference platform for secure automotive electronics, anchoring trust at the silicon level.

Read the full white paper here.

Also Read:

Soitec’s “Engineering the Future” Event at Semicon West 2025

How FD-SOI Powers the Future of AI in Automobiles

Powering the Future: How Engineered Substrates and Material Innovation Drive the Semiconductor Revolution


Podcast EP312: Approaches to Advance the Use of Non-Volatile Embedded Memory with Dave Eggleston

Podcast EP312: Approaches to Advance the Use of Non-Volatile Embedded Memory with Dave Eggleston
by Daniel Nenni on 10-22-2025 at 8:00 am

Daniel is joined by Dave Eggleston is senior business development manager at Microchip with a focus on licensing SST SuperFlash technology. Dave’s extensive background in Flash, MRAM, RRAM, and storage is built on 30+ years of industry experience. This includes serving as VP of Embedded Memory at GLOBALFOUNDRIES, CEO of RRAM pioneer start-up Unity Semiconductor (acquired by Rambus), Director of Flash Systems Engineering at Micron, NVM Product Engineering manager at Sandisk, and NVM Engineer at AMD. Dave is frequently invited as a speaker at international conferences as an expert on emerging NVM technologies and their applications and has 25+ NVM-related patents granted.

Dan explores the requirements of embedded non-volatile memory (NVM) for application in 32-bit microcontrollers with Dave, who provides a broad overview of the many markets served by these technologies. He describes the challenges of integrating NVM as process nodes advanced. Dave explains the benefits of Microchip’s SST SuperFlash technology and also discusses the cost and time-to-market benefits of using a chiplet approach to add VVM.

Dave also touches on the recently announced strategic collaboration between Microchip/SST and Deca Technologies to innovate a comprehensive NVM chiplet package to facilitate customer adoption of modular, multi-die systems.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.