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2010 Semiconductor Foundry Update: Consolidation!

2010 Semiconductor Foundry Update: Consolidation!
by Daniel Nenni on 05-16-2010 at 6:46 pm
Categories: Foundries, GlobalFoundries, TSMC

It has been an interesting month in the semiconductor business. Record revenues, profits, aggressive expansion plans, something we have not seen before and may not see again. Let’s start in Taiwan then move to Silicon Valley, Upstate New York, China, and Korea, with a look at: financials, capacity, and consolidation.

TSMC and UMC both posted record sales and profits exceeding even the optimistic. The top semiconductor companies followed suit which prompted the often quoted market researcher iSuppli to predict the chip industry is set for its highest annual growth in a decade: Semiconductor sales will climb to an all-time high of $300 billion in 2010, up from $230 billion last year. The previous sales record was $274 billion in 2007. According to iSupply, the last time semiconductor sales increased at such a rate was in 2000 when sales grew at 36.7%.

Though the semiconductor industry is estimated to grow 30%+ in 2010, TSMC and the foundry business is heading for much higher growth. Both fabless and fabbed semiconductor companies are reserving capacity with TSMC to ensure their SoCs hit the market window, compounding the wafer allocation problem that started earlier this year.

Capacity of course is key to semiconductor riches and will play the most significant role in who will deliver silicon to future generations. During my last visit to Taiwan, friends from TSMC briefed me on the Gigafab concept to which TSMC has publicly committed billions of dollars in capital expenses. A third $3B+ Gigafab will be constructed in the central Taiwanese city of Taichung and is slated to go online by the end of 2011. Nobody brings a new fab online faster and cheaper than TSMC, believe it.

While capitol spending is the key indicator of organic capacity growth, inorganic growth is also high on the foundry agenda: GlobalFoundry’s acquisition of Chartered Semiconductor, UMC’s investment in China’s He Jian, and TSMC’s equity stake in SMIC. GlobalFoundries clearly understands that capacity is everything in the foundry business, also understanding that they are no match for TSMC in a Fab building contest. Look for more inorganic growth for GlobalFoundries.

One of the leading semiconductor crystal ball sites predicted that there will only be three semiconductor manufacturers producing wafers below 20nm. It has been repeated so many times I don’t remember where it came from but now some view it as a truth. Today there are six foundries pushing Gordon Moore’s Empirical Observation: TSMC, UMC, GlobalFoundries, SMIC, Samsung, and IBM. That could certainly consolidate down to three: TSMC, Samsung, and GlobalFoundries.

While capitol spending is the key indicator of organic capacity growth, inorganic growth is also high on the foundry agenda: GlobalFoundry’s acquisition of Chartered Semiconductor, UMC’s investment in China’s He Jian, and TSMC’s equity stake in SMIC. GlobalFoundries clearly understands that capacity is everything in the foundry business, also understanding that they are no match for TSMC in a Fab building contest. Look for more inorganic growth for GlobalFoundries.

One of the leading semiconductor crystal ball sites predicted that there will only be three semiconductor manufacturers producing wafers below 20nm. It has been repeated so many times I don’t remember where it came from but now some view it as a truth. Today there are six foundries pushing Gordon Moore’s Empirical Observation: TSMC, UMC, GlobalFoundries, SMIC, Samsung, and IBM. That could certainly consolidate down to three: TSMC, Samsung, and GlobalFoundries.

lang: en_US

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Cadence EDA360 Redux!

Cadence EDA360 Redux!
by Daniel Nenni on 05-09-2010 at 9:02 pm
Categories: Cadence, EDA

“Cadence Design Systems, Inc. (NASDAQ: CDNS), the global leader in EDA360………”

Of course, why wouldn’t Cadence be the global leader in something they just made up? As a follow-up to my yawningly successful blog Cadence EDA360 Manifesto:

One of the problems I have with EDA360 is the fear, uncertainty, and doubt (FUD) it attempts in the paragraph “from creators to integrators”. It argues that maintaining Moore’s law depends on “a continuing migration to lower process nodes to gain performance, power, and cost advantages”. It further claims that Moore’s law hit a wall due to rising development costs?

Figure 1 shows development costs for advanced process nodes. Look at 32nm: the cost is $100M, looks daunting, but actually 50-60% is software – which is completely not related to a new semiconductor process. The next ingredient: Architecture, design and verification account for another 25-30%. This is again not related to process technology or Moore’s law.

The only part that is influenced by a new process is the implementation and manufacturing which accounts to only about 10-15% of the cost. So given the total cost, it is clear that the process technology’s contribution to the cost increase is minor. So this graph and explanation fail to explain the issue and how it is related to a semiconductor process technology. It is FUD against the foundries and the advantages of moving to new process nodes.

A few large semiconductor companies will continue to followMoore’s Law and design the fastest, most complex, and smallest ICs. These innovators are design creators. While they will provide a crucial role in the industry, only a handful of such companies can exist.

Clearly there must be a way to be successful at lower volumes or with less advanced silicon. Consumer demand is setting the stage for new kinds of connected devices we haven’t even imagined yet. If electronic design is only available to a handful of creators who can only make money by shipping 80 million units, few of these devices will be built and the diversity that consumers want will not materialize.

I absolutely agree with the concept of the increased role of integration, but my conclusion is that there is no reason not to use the latest semiconductor process technology, on the contrary, it can be used to integrate previously separate parts into one chip using the same higher level software, architecture, etc. thereby accomplishing lower cost, lower system footprint, lower power, etc.

This way, fabless semiconductor companies can take advantage of the latest process technology at a relatively low incremental cost, as they don’t need to invest again in developing new architecture, new software etc., and they get to reduce the risk and time to market for this new integrated product.

The role of the EDA industry is semiconductor design enablement through design reuse, automated tools and flows, which includes process migration. If I’m wrong on this please let me know, but my conclusion on this point: Cadence EDA360 not only insults the other EDA companies that lead the market segments mentioned (design, implement, verify), it also alienates the foundries and the push for advanced technologies, in addition to the fabless companies that are today successfully designing to those advanced process nodes.

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Cadence EDA360 Manifesto

Cadence EDA360 Manifesto
by Daniel Nenni on 05-02-2010 at 8:54 pm
Categories: Cadence, EDA

EDA360 is said to be a blueprint or high-level vision for the EDA industry and not a Cadence specific document, based on the challenges that customers are experiencing. What EDA36o really is, is a manifesto, a public declaration of intentions, opinions, objectives, or motives, issued by a specific organization. The question is: EDA360, will it be an industry transformation catalyst or a failed public relations campaign?

Unfortunately the word manifesto will forever be negated by the Unabomber’s (Theodore John Kaczynski) rambling 35,000 word manifesto against modern society “Industrial Society and Its Future”, which brought to conclusion one of the FBI’s most costly investigations. Mr Kaczynski’s brother recognized the writing style and arguments and informed the FBI of Ted’s wilderness whereabouts. It is my hope that John Bruggeman and EDA360 can change the perception of a manifesto and not reinforce it.
To understand a manifesto, first you must research the author. I’m a bit surprised that John Bruggeman has not one but two LinkedIn profiles and neither is even close to being complete, so my research ended there. John Blogs and Twitters but does not do LinkedIn? It is concerning if a Chief Marketing Officer does not really get Social Media. John’s Twitter and Blog started after he joined Cadence so maybe he is still ramping up, I hope he is a quick study. Theodore John Kaczynski doesn’t have a completed LinkedIn profile either but he does have a very detailed Wiki page.

The manifesto itself is 32 pages long and can be found here along with an overview, John Bruggeman intro video, and an EDA360 news aggregator. A Richard Goering EDA360 Q&A is here and the Cadence official EDA360 press release can be found here. The formal Cadence description:
The Cadence EDA360 Vision Paper is a comprehensive call-to-action for the electronics industry to address a disruptive transformation—a shift in focus from design creation to integration. Drawing upon a collaborative ecosystem, EDA360 enables the development of complete hardware/software platforms that are application-ready. While traditional EDA concentrates on silicon design creation, EDA360 responds to the needs of both design creators and integrators. It helps creators close the “productivity gap” through improved approaches to design, verification, and implementation. EDA360 also helps integrators close the “profitability gap” by providing new capabilities for IP creation, selection, and integration, and for system optimization.

The main goal of any manifesto is to elicit discussion and from what I have seen so far there will be plenty of it on EDA360. A Cadence PR person contacted me a couple weeks ago and has scheduled a 30 minute discussion between John Bruggeman and myself for May 10th. Hopefully I can make some sense out of all this and come up with some relevant questions for John by then as to not embarrass myself. Normally I require lunch or some sort of meal to blog, as a qualifier as to how serious they are (I blog for food). On this occasion however, I will give Cadence the benefit of the doubt.

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Moore’s (Empirical Observation) Law!

Moore’s (Empirical Observation) Law!
by Daniel Nenni on 04-18-2010 at 10:49 pm
Categories: EDA, General, Siemens EDA

“What would you like your legacy to the world to be? Anything but Moore’s Law!”

 

Gordon Moore, May 2008.

Moore slightly altered the formulation of the law over time, bolstering the perceived accuracy of Moore’s law in retrospect. Most notably, in 1975, Moore altered his projection to a doubling every two years. Despite popular misconception, he is adamant that he did not predict a doubling “every 18 months”.

So clearly Moore’s law is more of an observation. Wally Rhines, Mentor Graphics CEO and my favorite presenter certainly thinks so. In his presentation to the U2U conference (that I mentioned in my previous blog), Wally feels that Moore’s empirical observation has been a useful approximation for the past 40 years due to a basic law of nature called “The learning curve”.

By definition, a learning curve is a graphical representation of the changing rate of learning for a given activity or process. Typically, the increase in retention of information is sharpest after the initial attempts and then gradually evens out, meaning that less and less new information is retained after each repetition. The learning curve can also represent at a glance the initial difficulty of learning something and, to an extent, how much there is to learn after initial familiarity.

An amazing thing, the presentation is seventy pages long and filled with an incredible amount of data, but you will never see a better data delivery system than Wally Rhines. It would be impossible to do a Wally presentation justice in a 500 word blog but here is what I learned that day:
For perspective there are:

  • 100+ billion galaxies in the night sky
  • 100+ billion stars in the milky way galaxy
  • 100+ billion transistors on a chip by 2025

Delivering 10X and beyond design improvements will require:

  • System Level Design
  • Functional Verification
  • Embedded Software
  • Physical Design and Verification


A new level of abstraction will be required for billions of transistors, 100 millions of gates, millions of lines of RTL, and hundreds of lines of TLM or C-based code. I remember the transition from schematic based design to language based (synthesis), it was a bloody battle for sure. The poor ESL guys never had a chance! Expect nothing less for System Level Design.

Verification is falling further behind and will need exponential growth in speed and capabilities to keep pace. Redundant verification must be eliminated. Emulation with transactional testbenches and mixing dynamic and formal verification will be required. Verification is one of the big challenges I see with the foundries, absolutely.

Physical Design and Verification will continue to see new routing architecture every 2-3 nodes, parallel optimization, and full parallelization of routing. Place and route will be merged with verification to reduce/eliminate ECO routing iterations. This will be a big win for Mentor obviously since they own the verification market and are trying to move up the physical design chain.

Embedded Software is a hot topic for Wally and of course where Mentor has made significant investments. According to Wally most of the escalating SoC design costs can be attributed to software development, which will by far outpace hardware development.

Wally is my favorite EDA CEO. He is humble, brilliant, personable, and a great speaker. No coincidence Mentor Graphics is also my favorite EDA company as it mirrors Wally. Why Dr. Walden C. Rhines does not have his own wiki page I do not know (too humble?). Rumor has it I may get a lunch with Wally sometime soon, which will certainly reinforce the notion that I blog for food.

lang: en_US

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TSMC Earthquake Damage Redo

TSMC Earthquake Damage Redo
by Daniel Nenni on 04-14-2010 at 10:54 pm
Categories: Foundries, TSMC

As you may know I enjoy poking fun at the current state of semiconductor design and manufacture media; sloppy reporting, editors with little or no actual semiconductor experience taking corporate marketing spins on news/events and passing it along as fact.

Last week it was the EETimes parroting the Samsung foundry business press. A nice thing about being a blogger and owning your own domain is that you get to see (Google Analytics) where the views come from and which links they click on etc…. It’s like spying on your siblings, not that I ever did that. Lets just say that last week South Korea discovered my blog.

This time it is the ElectronicsWeakly top viewed article TSMC Loses 40K Wafers In Quake by one of my fellow bloggers David Manners. There was a lot of press on this topic last week but David is the only one to put a number (40,000 wafers, which is significant) on the loss, and he led with it in an article versus his blog (insert sinister music here). The question is: Where did David get a 40,000 wafer loss number? Certainly not from the official TSMC press brief:

TSMC Reports Impact From March 4 Earthquake Initial Estimate of 1.5 Days Wafer Movement Loss
Issued by: TSMC Issued on: 2010/03/04 Hsinchu, Taiwan, R.O.C. – March 4, 2010 – TSMC (TWSE: 2330, NYSE: TSM) today announced that an earthquake of magnitude 6.4 on the Richter scale occurred in south Taiwan at 8:18 am Taiwan local time on March 4. The earthquake registered on instruments at TSMC’sTainansite at magnitude 5, and was measured at TSMC’s Hsinchu site at magnitude 2.

Current assessments reports show that the earthquake had minimal impact on Hsinchu fabs. WhileTainan fabs suffered greater impact, they have gradually begun to resume production. Our initial estimate is that the earthquake caused the equivalent of 1.5 days loss of wafer movement for the company in total.

Luckily one of my siblings, that I absolutely did not spy on when I was a kid, spent his career with semiconductor equipment manufacturers and knows of such things. He says that determining actual wafer or die loss in this context is next to impossibleand here is why:

There are 300+ steps in wafer production so the impact is spread over a long wafer movement process.Average wafer movement loss is calculated as: Each Fab’s Equipment Production Time Loss (including equipment check and recalibration) + Each Fab’s Wafer Scrap (wafers removed from the movement process and not returned) / by over all wafer movement for the company (TSMC). Average wafer movement loss is expressed in “days loss of wafer movement”, which is an averaged manufacturing index, not an actual wafer scrap or revenue loss number. Bottom line, you can’t determine actual “lost wafers” from “loss of wafer movement”.

It looks like David took TSMC’s 2009 capacity of 9,995,000 8-in wafers (the 8-in. equivalent number is used to normalize 6,8, and 12-in. wafer production) and divided it out using 1.5 days of “wafer movement loss” as “lost wafer production”. My emails to David on the subject were not returned. Even funnier, I was in Taiwan that week. Funny because my Taiwan friends accuse me of bringing earthquakes with me from California. As I blogged last year, I was in Taiwan for both the July 2009 and the September 1999 earthquakes, also typhoons and an airplane crash. Pure coincidence I assure you.

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Redefining the Semiconductor Foundry Model: Abu Dhabi versus Taiwan

Redefining the Semiconductor Foundry Model: Abu Dhabi versus Taiwan
by Daniel Nenni on 04-11-2010 at 2:53 pm
Categories: EDA, Foundries, GlobalFoundries, Siemens EDA, TSMC

It was a pleasure to see the GlobalFoundries (GFI) corporate pitch at the Mentor Graphics U2U Conference last week. Wally Rhines is a tough act to follow but Mojy Chian, Senior Vice President of Design Enablement at GlobalFoundries, presented a compelling argument for a refined foundry business model. The GFI people were also nice enough to send the presentation, offer a private briefing, and honor my request for a picture of an actual 28nm test chip wafer.

I first met Mojy Chian at Conexant and again at Altera where he was Vice President of Technology managing development, infrastructure, and manufacturing (down to TSMC 40nm). I last met Mojy at lunch on St Patrick’s day. When I heard Mojy joined GlobalFoundries I knew they were absolutely serious about the business side of semiconductor design and manufacturing.

Clearly the fabless model continues to thrive at 40nm and below. Due to the cost, only a handful of semiconductor manufacturers will develop 28nm process technology. Due to the cost, only the top fabless companies will design at 28nm, so the competition for their business will be fierce. The challenge for GlobalFoundries is to differentiate from Taiwan and that was the underlying message in this presentation: “GlobalFoundries is everything TSMC is not”.

Point #1 is the basis for their name, being global and not putting your semiconductor manufacturing eggs in one regional (Taiwan) basket. TSMC’s Morris Chang responded directly to this “Global Semiconductor Company” challenge by saying that TSMC will stay in Taiwan. The major reason being the economies of scale. According to Chang, TSMC only needs to run its Taiwan wafer fabrication plants at 40% capacity to break even, compared with 80% for “global” rivals.

The Chartered Semiconductor Common Platform marketing initiative will continue under GFI. In theory, the process development is collaborative and the cost is shared amongst the members. Common Platform clearly did not work for the now defunct Chartered Semiconductor which in my opinion was an implementation problem. If GFI drives this alliance hard it will work, believe it.

Point #2 is technology and the differing versions of HKMG technology. David Lammers did an excellent write-up: Gate First or Gate Last: Technologists Debate High-k . The bottom line is that Intel and TSMC will do Gate-Last. GFI, IBM, and other Common Platform Alliance members will do Gate-First. From what I have learned, Gate-Last will favor high performance and high yield designs but will require restricted design rules (RDRs). Gate-First will favor low power and smaller die sizes but may not scale past 22nm. I see this as a major battle ground for the foundry business. My opinion, whoever wins the 28nm node will lead the foundry business for the next decade.

Point #3 is semiconductor design enablement or the EDA, IP, and Design Services ecosystem. GlobalFoundries has Common Platform, TSMC has the Open Innovation Platform. One thing that has changed with Common Platform is that GFI is providing generous financial incentives for partners and we are talking about millions of dollars in life lines to companies that have struggled for profitability. GFI also pledged not to compete with partners, which is a direct shot at TSMC who has spent 100’s of millions of dollars developing proprietary design enablement technology.

Speaking of TSMC design enablement, the annual TSMC 2010 Technology Symposiums start next week in San Jose with Morris Chang as keynote speaker. TSMC has scheduled an in-person briefing for me with Shang Yi Chiang, senior vice president of R&D, to discuss 28nm technology so next week’s blog will be a follow-up to this.

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Redefining the Foundry Model: TSMC versus GlobalFoundries

Redefining the Foundry Model: TSMC versus GlobalFoundries
by Daniel Nenni on 04-10-2010 at 2:08 am
Categories: Foundries, GlobalFoundries, TSMC

The 17[SUP]th[/SUP] annual TSMC Technical Symposium finished its North American tour in Boston, a day before the Boston Marathon. I would like to be clever and say the foundry business is also a marathon but it clearly is not. If you watch TSMC, the foundry business is both a sprint AND a marathon!

In contrast to the previous blog on Global Foundries, the three key points to TSMC’s success are Leadership, Technology, and Experience. Rick Cassidy, President of TSMC North America, opened the symposiums with 30 slides of analogies and perspective featuring the US Olympic Bobsledding team.

Point #1 Leadership: Clearly TSMC is the leading foundry in all aspects of the business. The question is can TSMC continue in that role for another decade? I think the answer rests squarely on point #2.

Point #2 Technology: My 30 minute meeting with Dr. Shang-Yi Chiang, Vice President of TSMC R&D, should be a blog in itself but let me say here that he is one of the smartest, humble, and most believable men I have met. The big announcement Dr Chiang made was that TSMC would skip 22nm in favor of 20nm. My first question was why? Well, for two reasons (1) TSMC continues to see a 70% shrink as the optimum scaling factor: 40nm->28nm, 28nm->20nm, 20nm->14nm, 14nm-> 10nm. (2) Is my reason: Because TSMC can, and it gives them a competitive advantage. The predominate foundry business challenge is price cutting (2[SUP]nd[/SUP] and even 3[SUP]rd[/SUP] sourcing) so making your process as sticky as possible is the ultimate business goal. High volume designs will absolutely take advantage of the performance/power/area savings of a 20nm process versus 22nm. Look for the other foundries to follow suit as they did with 45 to 40nm in order to be competitive.

My second question for Dr Chiang was why Gate-Last versus Gate-First for 28nm? TSMC actually had parallel 28nm projects: Gate-First, Gate-Last, and Poly Gate. The winner was the Gate-Last 28nm implementation coupled with Restricted Design Rules due to scalability, performance, and yield. Dr Chang also stated that there is not an area penalty using RDRs which defies my personal experience with Recommend Design Rules.

My third question was about 40nm, what really happened with yield? Dr Chiang viewed it positively as a “learning” experience which resulted in technologies and practices that will enable 28nm and below (restricted design rules). TSMC saw 40nm designs with 4 billion + single VIAs, so VIA failure was an issue. Process variation was also a major issue, which I have blogged about before:

Moore’s Law and 28nm Yield
Moore’s Law and 40nm Yield


Dr Chaing did say that 40nm is “comfortably in production” at Fab 12 and 14. Expansion projects will double TSMC 40nm capacity by the end of the year. Giga Fabs like 12 and 14 can produce 100,000+ 12 inch wafers per month! Compared to Mini Fabs (10k+) and Mega Fabs (30k+). Capacity and the ability to satisfy the high volume needs of the top fabless semiconductor companies is key, believe it. He also said 28nm is on track with risk production in Q2 2010, which puts TSMC 6 months ahead of GlobalFoundries.

Point#3 Experience:TSMC also owns this one. IDM experience and Foundry experience are two very different things. One example is semiconductor IP and how it integrates into your design. Characterized, Modeled, Silicon proven IP from TSMC itself and TSMC early access partners like Virage Logic will ease integration issues and speed wafer sales. IP such as SRAM is used as pipe cleaners for new processes, which is why Virage was the first to announce products on TSMC 28nm. Other experience examples include silicon proven PDKs, Reference Design Kits and Flows.

This is my favorite Rick Cassidy slide, tight integration indeed:

My second favorite slide: mega fab costs are comparable to a Nimitz Class Aircraft carrier, minus the aircraft ($5B+). The question is, how many companies will be able to afford a fleet of aircraft carriers in the coming years, TSMC and?

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TSMC 2011 Forecast and 28nm Update!

TSMC 2011 Forecast and 28nm Update!
by Daniel Nenni on 03-31-2010 at 10:05 pm
Categories: Foundries, TSMC

My visit to Taiwan last week was very encouraging. No earthquake, no typhoon, and both TSMC and UMC again posted record financial results, giving a peek into what 2011 has in store for us semiconductor professionals around the world.

A transcript from the TSMC earnings call can be foundhere, the UMC transcript is here. The TSMC transcript is 19 pages long so let me save you some time with the key financial points:

  • TSMC’s net sales reached NT $412.3 billion ($13.4730 billion USD), up 6.9% from Q2 and up 24.8% from the same period a year ago.
  • Wafer shipments were 3.19 million 8 inch equivalent wafers, up 9% from the prior quarter and up 30.5% from the year ago quarter.
  • Operating margin was 38.4%, down 2% points sequentially, but up 2.8% points compared with year ago quarter.
  • EPS for Q3 reached NT$1.81, ROE was 36.5%.
  • Q3 gross margin was 50%, up by 0.5% points from 49.5 in Q2, mainly due to continued cost improvements.
  • Operating expense increased NT$1.6 billion from Q2, primarily due to a higher level of development activities for our 28 nanometer and 20 nanometer technologies, and also a higher opening expense for our Fab 12.
  • Ended Q3 with $5B+ USD in cash and short term investments


“Our mission is simply to be the technology and capacity provider of the global logic IP industry for years to come. We want to be the technology and capacity provider of the largest IP industry for years to come.”
Morris Chang was again on the conference call. Morris resumed as TSMC CEO June 2009 after passing the CEO baton to Rick Tsai in July 2005. I really am glad Morris is back at TSMC! According to Morris:

  • Q3 was a historical record in revenue dollars, in gross margin and in net income dollars.
  • If Q4 were at the same exchange rate at Q3, then Q4 guidance would be revenue NT$111.6 billion to NT$113.7. billion which is higher than Q3 actual.
  • Gross margin percentage would be 49.5% to 51.5%, which is also higher than the Q3 actual.
  • CAPEX will be $5.5 billion this year, CAPEX will be greater in 2011.
  • 71 customer 28 nm tape outs already scheduled.
  • We are forecasting total foundry revenue growth will be 14% in 2011.


One thing that Morris said that needs clarification is on 28nm portability:

I also wanted to point out that as the 28 nanometer generation, customer designs are very difficult to port between foundries. They’re very difficult to move from one foundry to another. This is a new phenomena that did not exist even in the 45-40 generation.

It is true that TSMC 28nm designs cannot be manufactured at other foundries with little or no modifications like 40nm. TSMC 28nm designs can however be migrated to other foundries using process migration tools from Sagantec. Magma and Cadence also have migration tools (Titan ALX and Virtuoso Layout Migrate) but they both have complexity and capacity issues. Process migration is only a $10M market so I doubt Magma or Cadence will put much more effort into it. I’m currently working on 28nm migration projects with Sagantec so I know this by experience.

Communications (mobile internet) will continue to drive semiconductors in 2011 and the rest of this decade. Smartphones give people access to information and information is power. In India and China even the poorest of poor people have mobile phones. No indoor plumbing, but everyone has a mobile phone. Access to information raises the aspirations of the poor which will in turn force governments to acknowledge poverty and do something about it. The semiconductor industry is changing the world, believe it.

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Semiconductor Industry 2025

Semiconductor Industry 2025
by Daniel Nenni on 03-21-2010 at 8:56 pm
Categories: Events, Semiconductor Services

The 2010 ISSCC theme was all about “Sensing the Future” and was one of the most inspiring semiconductor conferences I have experienced. The halls were filled with the top names in semiconductor design and manufacture from around the world. The sessions highlighted not only technology breakthroughs (first 4G silicon), but new semiconductor applications for humanity.

“The International Solid-State Circuits Conference is the foremost forum for presentation of advances in solid-state circuits and systems-on-a-chip. The Conference offers a unique opportunity for engineers working at the cutting edge of IC design and use to maintain technical currency, and to network with leading experts.”
Per my previous blogs, mobile internet devices are a leading driver of semiconductor growth. Next-generation semiconductors will enable new mobile applications that take advantage of high-speed data connections, high-performance applications, added processing capabilities, and long battery lifetime. The result being exploding data usage and a 3G wireless bottleneck.

The first functional 4G chip for high-speed communication was highlighted, a collaboration between researchers from ETH Zurich and Advanced Circuit Pursuit. In addition, researchers from CEA-LETI described a reconfigurable chip that can implement multiple wireless standards including 4G, WIMAX, 802.11n, and Cognitive Radio. Their solution provides the necessary flexibility required to interconnect to a variety of networks using many different standards. Very cool stuff.

Also unveiled were several low-power embedded processors that break through the 1 GHz barrier, enabling the next generation of smart phones and netbooks that are fast approaching PC operating speeds. Intel and ARM presented new circuits for dynamic detection and correction of timing errors to squeeze voltage margins for reliable low- power operation over 1.5GHz, while Qualcomm describes low-power-design techniques used in their upcoming 1.4GHz Snapdragon processor core.

These innovations in both cellular/wireless standard support and low-power, high-performance embedded processors will be the building blocks for the next-generation mobile devices, bringing as-yet-unseen levels of functionality and performance to the masses. Extremely cool stuff!

A late Tuesday night panel “ Semiconductor Industry in 2025 “ looked at the challenges ahead:

The historic predictability of Moore’s Law has spurred innovation and redefined how we build integrated circuits. We have developed an eco-system of specialized entities to resolve specific challenges such as Equipment Development, Foundry Services, Design, EDA, Software, and Consumer Services. While more specialization has been an undisputed trend of the past, we are beginning to see hardware companies becoming less specialized – manufacturing companies entering design, design companies entering services, to name a few. What approach will be the predominant model in 2025? More vertically-integrated companies that enable recurring revenue? Or more horizontally- integrated companies that focus on specialized innovation?

Executives from Intel, IBM, NXP, TSMC, and Mentor Graphics presented. My favorite, of course, is Wally Rhines who made an interesting point. While other industries consolidate, the semiconductor industry de-consolidates with basically the same players in different positions depending on what technology drives the semiconductor market. In the 1970’s it was memory, microprocessors in the 1980’s, fabless semiconductor companies joined the ranks of the top 25 in the 1990’s, and mobile internet enablers experienced record growth in the last 10 years.
From 2010-2025 Wally predicts a yearly:

  • Decline in cost per function (transistor) of 35%
  • 49%+ transistor increase
  • 13%+ unit increase

The 2011 ISSCC continues on the futuristic path of semiconductors: Electronics for Healthy Living – call for papers is now available. I hope to see you there.

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TSMC versus SAMSUNG

TSMC versus SAMSUNG
by Daniel Nenni on 03-07-2010 at 8:49 pm
Categories: Foundries, TSMC

According to the EETimes – “The leading-edge foundry market is up for grabs, as several vendors have stumbled or been victims of the shakeout “. According to people who actually work with the foundries, like myself, the leading edge foundry market will continue to be dominated by TSMC and GlobalFoundries is the “dark horse”. Samsung is now and will always be an IDM, with the foundry business being a diversion at best.

The EETimes also claims that TSMC “stumbled and had yield issues at the 40-nm node.”Again not true. TSMC has more than 80% of the 40nm market with 60+ products in production. TSMC forecasts 40nm accounting for 20% of overall revenues at the end of 2010, compared to 9% in the fourth quarter of 2009. Other foundries would be lucky to stumble into numbers like that!
TSMC Fab 12 is currently capable of producing 80,000 12-inch equivalent wafers on 40nm every quarter and will double that by the end of 2010. TSMC’s other 300-mm GigaFab, Fab 14, can also be used to meet future 40nm demand.
The widely reported TSMC 40nm yield problems were focused on GPUs. GPU products are bleeding edge technologies that drive process development, including half nodes. There are (5) GPU players withmarket share: Intel, Nvidia, AMD/ATI, S3, and SiS. Intel is an IDM, the rest manufacture at TSMC. Why TSMC you ask? Because GPUs are the single most difficult product to yield and TSMC is the only foundry that can accommodate the insanely competitive GPU market.

According to Ana Hunter, Samsung Semiconductor Vice President of Foundry Services, after 4+ years of trying “Samsung’s share of the foundry business is not as big as we want, but it takes time to put the pieces in place and ramp designs.”Prior to Samsung, Hunter spent 9+ years at Chartered Semiconductor, which was bought by GlobalFoundries last year for pennies on the invested dollar. Hunter stated that “The foundry business is part of our core strategy” and highlighted 6 reasons why Samsung believes it will succeed:

[LIST=1]

  • Capacity – Samsung plans to double its production of chips for outside customers every year until it rivals market leader TSMC. ( Wow, good luck with that!)
  • Resources – Samsung is one of the few companies that has the resources to compete at the high-end of the foundry market. (Intel, IBM, TSMC, GFI….)
  • Leading Edge Technology – Samsung is ramping 45-nm technology at a time when TSMC and others are struggling in the arena. (Oh no she di’int!)
  • Leading Edge Technology part II – Samsung will be one of the first foundries to roll out a high-k/metal-gate solution. The technology will be offered at the 32- and 28-nm nodes, which will be rolled out this year. (TSMC and GFI will go straight to 28nm HKT this year)
  • Leading Edge Technology part III – Unlike rival TSMC, Samsung is using a gate-first, high-k technology, TSMC is going with gate-last. We think that gate-first is best suited for today’s needs. (I defer to TSMC on this one, they have forgotten more about the foundry business than most will ever know.)
  • Ecosystem – Samsung has put the EDA pieces in place for the design-for-manufacturing puzzle. (A puzzle analogy, really?)
    Now let me highlight 6 reasons why I believe Samsung will not succeed:

    [LIST=1]

  • Business Model – The Foundry business is services centric, the IDM business is not. This is a serious paradigm shift for Samsung.
  • Customer Diversity – Supporting a handful of customers/products is a far cry from supporting the 100’s of customers and 1,000′s of products TSMC does.
  • Ecosystem – An open ecosystem is required which includes supporting commercial EDA, Semiconductor IP, and Design Services companies of all shapes and sizes.
  • Conflict of Interest – Pure-play foundries will not compete with customers, Not-pure-play foundries (Samsung) will. Would you share sensitive design, yield, and cost data with your competitor?
  • China – The Chinese market represents the single largest growth opportunity for the foundry business. TSMC has a fab in Shanghai and 10% control of SMIC (#4), UMC (#2) has control of China’s He Jian (#11), and Samsung does not even speak Mandarin.
  • Competition – The foundry business is ultra competitive, very sticky, and product dumping will not get you from #9 to #1.Just my opinion of course.