Wiki Tag: Intel
Craig R. Barrett Wiki
Backside Power Delivery (BSPD) Wiki
Backside Power Delivery (BSPD), also called Backside Power Delivery Network (BSPDN) or backside power via (BPV) technology, is a semiconductor manufacturing innovation in which the chip’s primary power distribution network is relocated from the front side (transistor and signal interconnect layers) to the backside of the… Read More
Paul Otellini Wiki
Born: October 12, 1950 – San Francisco, California, U.S.
Died: October 2, 2017 – Sonoma County, California, U.S.
Education:
-
B.A. in Economics, University of San Francisco (1972)
-
M.B.A., University of California, Berkeley (1974)
Occupation: Business executive
Known For: 5th CEO of Intel Corporation (2005–2013), leading … Read More
Semiconductor Gigafab (Giga Fabrication Plant) Wiki
Gigafab is a term used in the semiconductor industry to describe an ultra-large semiconductor fabrication plant (fab) capable of producing wafers at a scale exceeding 100,000 wafer starts per month (WSPM). These facilities represent the pinnacle of scale, automation, and capital intensity in advanced chip manufacturing.… Read More
Intel EMIB (Embedded Multi-die Interconnect Bridge)
EMIB (Embedded Multi-die Interconnect Bridge) is an advanced 2.5D packaging technology developed by Intel that enables high-density, high-bandwidth, low-latency interconnects between chiplets (dies) within a single package—without requiring a full silicon interposer. EMIB offers a modular and scalable approach to … Read More
UCIe (Universal Chiplet Interconnect Express) Wiki
UCIe (Universal Chiplet Interconnect Express) is an open industry standard for die-to-die interconnects that enables high-bandwidth, low-latency, power-efficient communication between chiplets in advanced package architectures. The UCIe specification was launched in March 2022 by the UCIe Consortium, with founding… Read More
Intel 3 vs. Intel 18A Wiki
Overview
| Feature | Intel 3 | Intel 18A |
|---|---|---|
| Node Class | Enhanced 7nm (refinement of Intel 4) | 1.8nm-class full-node leap |
| Transistor Type | FinFET | RibbonFET (GAAFET) |
| Power Delivery | Front-side power only | Backside Power Delivery (PowerVia) |
| EUV Use | Partial (select layers) | Extensive EUV, reduced multi-patterning |
| PPA Target | Modest vs. Intel |
Network-on-Chip (NoC) Wiki
Term: Network-on-Chip (NoC)
Also Known As: On-chip Interconnect Network, SoC Interconnect Fabric
Domain: Semiconductor Architecture, System-on-Chip (SoC), Multiprocessor Design
Primary Use: Communication backbone for multi-core processors, SoCs, and chiplets
First Introduced: Early 2000s (concept); widespread… Read More
High-NA EUV Lithography Wiki
Full Name: High Numerical Aperture Extreme Ultraviolet Lithography
Abbreviation: High-NA EUV
Technology Type: Advanced semiconductor photolithography
Developed By: ASML, Zeiss, in collaboration with Intel, TSMC, imec, and others
First Deployment Target: Intel (expected ~2025–2026)
Main Use: Sub-2nm logic node patterning… Read More
Intel Foundry Services Wiki
Name: Intel Foundry Services (IFS)
Parent Company: Intel Corporation
Business Type: Internal business unit
Founded: March 2021
Headquarters: Santa Clara, California, USA
Global Presence: U.S., Germany, Israel, Ireland, India, Malaysia
Industry: Semiconductor Manufacturing Services
Website: https://www.intel.com/foundry… Read More









Semidynamics Unveils 3nm AI Inference Silicon and Full-Stack Systems