Hierarchy Applied to Semiconductor IP Reuse

Hierarchy Applied to Semiconductor IP Reuse
by Daniel Payne on 11-30-2017 at 12:00 pm

When I first started doing IC design back in 1978 we had hierarchical designs, and that was doing a relatively simple 16Kb DRAM chip with only 32,000 transistors using 6um (aka 6,000 nm) design rules. SoC designs today make massive use of hierarchy at all levels of IC design: IC Layout, transistor netlist, gate level netlist, RTL … Read More


Time is Money, Especially when Testing ICs

Time is Money, Especially when Testing ICs
by Daniel Payne on 05-24-2017 at 12:00 pm

Semiconductor companies are looking for ways to keep their business profitable by managing expenses on both the design and test side of electronic products, which is quite the challenge as the trends show increases in test pattern count and therefore test costs. Scan compression is a well-known technique first created over 15… Read More


Dassault Systemes Hosts New Microsite Focused on IP Reuse Challenges

Dassault Systemes Hosts New Microsite Focused on IP Reuse Challenges
by Mitch Heins on 01-04-2017 at 12:00 pm

I recently wrote an article about networks-on-chip (NoC) and how Systems-On-Chip integrated circuits (SoCs) are becoming increasingly more complex and heterogeneous in nature. While researching for that article I came upon a new micro-site by Dassault Systemes that goes into great detail about the operational challenges… Read More


Requirements Management and IP Management Working Together

Requirements Management and IP Management Working Together
by Daniel Payne on 09-12-2016 at 12:00 pm

I first heard about requirements management back in 1995 while marketing a graphic HDL entry tool for an EDA vendor, and it sounded like a very useful automation approach, however our team quickly discovered that there were too many different vendors for requirements management, so there could be no simple way to integrate with… Read More


More Test Points are Better

More Test Points are Better
by Daniel Payne on 02-14-2015 at 7:00 am

I got really involved in testability back at CrossCheck in the 1990’s when they designed a way for Gate Arrays to have 100% observability without any Design For Test (DFT) requirements on designers. The Japanese Gate Array companies loved this approach and their customers enjoyed the highest test coverage without being… Read More


Managing Semiconductor IP

Managing Semiconductor IP
by Daniel Payne on 01-21-2015 at 5:00 pm

SemiWiki blogger Eric Esteve does an excellent job writing about all of the semiconductor IP available, and the popularity of IP is only growing more each year. Here’s a projection from IBS about semiconductor IP showing revenues of $4.7B by 2020:

Analyst Gary Smith divides IP into three broad categories: Functional, Foundation… Read More


A Functional Verification Framework Spanning Simulation to Emulation

A Functional Verification Framework Spanning Simulation to Emulation
by Daniel Payne on 12-11-2014 at 2:00 am

Software engineers and firmware designers can find bugs, update their code and re-distribute to the users. In the consumer electronics world this means that my smart phone apps get updated, and my Android OS gets updated on a somewhat regular basis, however on the hardware side the design and verification of an SoC must be close … Read More


Simulation and Analysis of Power and Thermal Management Policies

Simulation and Analysis of Power and Thermal Management Policies
by Daniel Payne on 11-18-2014 at 10:00 pm

Earlier this month I blogged about Power Management Policies for Android Devices, so this blog is part two in the series and delves into the details of using ESL-level tools for simulation and analysis. The motivation behind all of this is to optimize a power management system during the early design phase, instead of waiting until… Read More


Power-Aware Verification in Mixed-Signal Simulation

Power-Aware Verification in Mixed-Signal Simulation
by Daniel Payne on 11-10-2014 at 7:00 am

My Samsung Galaxy Note 2 phone lasts about 1.5 days on a single battery charge, thanks in part to the clever power conservation approaches like when the screen is automatically dimmed then turned off after no activity. Mobile phones and many other battery-powered devices used today all need power-saving designs, which then means… Read More


Full-Chip Electromigration Analysis

Full-Chip Electromigration Analysis
by Daniel Payne on 10-10-2014 at 7:00 am

I’ll never forget debugging my first DRAM chip at Intel, peering into a microscope and watching the aluminum interconnect actually bubble and dissolve as the voltage was increased, revealing the destructive effects of Electromigration (EM) failure. That was back in 1980 using 6 um, single level metal technology, so imagine… Read More