Is FD-SOI Smarter than Moore?

Is FD-SOI Smarter than Moore?
by Eric Esteve on 11-01-2013 at 12:03 pm

If you have read the excellent article from Paul McLellan, you know about FDSOI as a technology, so I will not come back to FDSOI device, and the comparison with FinFET in term of device topology, doping level and so on. If you missed it, I would recommend you to read this article, as well as the many comments (all of them being relevant).… Read More


The Alternative to FinFET: FD-SOI

The Alternative to FinFET: FD-SOI
by Paul McLellan on 10-30-2013 at 11:00 am

Everywhere you turn these days you find FinFETs. Intel has had them since 22nm (they use the word Tri-gate but it is the same as what the world calls FinFET) and TSMC will have them at 16nm. So why FinFET? And is there an alternative?

The reason that regular bulk planar transistors have run out of steam is that the channel area underneath… Read More


Subsystem IP, myth or reality?

Subsystem IP, myth or reality?
by Eric Esteve on 12-07-2012 at 5:00 am

I have participated to a panel during IP-SoC, I must say that “Subsystem IP, myth or Reality” was a great moment. The panel was a mix of mid-size IP vendor (CAST, Sonics), one large EDA (Martin Lund from Cadence), Semiwiki blogger and one large IDM (Peter Hirt from STM) who has very well represented the customer side. And, to make the… Read More


ST Microelectronics: Strategic Options

ST Microelectronics: Strategic Options
by Paul McLellan on 12-01-2012 at 5:11 pm

ST Microelectronics announced yesterday that it would have a conference call on December 10th to announce its strategy going forward. ST has been struggling the last couple of years, with revenues down year to year. From 2010-2012 (the last an estimate of course) it did $10.3B, $9.6B and $8.4B so it has shrunk nearly 20% in 3 years.… Read More