Cryogenic Semiconductor Designs for Quantum Computing

Cryogenic Semiconductor Designs for Quantum Computing
by Kalar Rajendiran on 01-16-2024 at 6:00 am

siemens eda quantum crygogenics newsroom 1280x720

Over the last few years, there has been an increase in news about quantum computing. Much of this news coverage has been around computing supremacy, potential threats to information security and quantum cryptography. While the field of quantum computing is still in its early stages, there are several companies who have already… Read More


Analysis and Verification of Single Event Upset Mitigation

Analysis and Verification of Single Event Upset Mitigation
by Jacob Wiltgen on 12-07-2023 at 10:00 am

Figure 1 Driving trends

The evolution of space-based applications continues to drive innovation across government and private entities. The new demands for advanced capabilities and feature sets have a direct impact on the underlying hardware, driving companies to migrate to smaller geometries to deliver the required performance, area, and power… Read More


A Complete Guidebook for PCB Design Automation

A Complete Guidebook for PCB Design Automation
by Kalar Rajendiran on 11-29-2023 at 8:00 am

Constraint Management

Printed Circuit Boards (PCBs) are the foundation of modern electronics, and designing them efficiently is complex. Design automation and advanced PCB routing have transformed the process, making it faster and more reliable. Design automation streamlines tasks, reduces errors, and ensures consistency. Advanced PCB routing… Read More


Uniquely Understanding Challenges of Chip Design and Verification

Uniquely Understanding Challenges of Chip Design and Verification
by Daniel Nenni on 11-14-2023 at 6:00 am

Jean Marie Brunet (1)

Jean-Marie Brunet is Vice President and General Manager of Siemens Hardware-Assisted Verification. He and I spoke recently about how different his hardware group is from the rest of the software-centric EDA product space and why a hardware-oriented EDA vendor like Siemens fully understands the challenges of the chip design… Read More


Successful 3DIC design requires an integrated approach

Successful 3DIC design requires an integrated approach
by Kalar Rajendiran on 11-13-2023 at 6:00 am

Siemens EDA 3DIC Graphics

While the leap from traditional SoC/IC designs to Three-Dimensional Integrated Circuits (3DICs) designs brings new benefits and opportunities, it also introduces new challenges. The benefits include performance, power efficiency, footprint reduction and cost savings. The challenges span design, verification, thermal… Read More


Ensuring 3D IC Semiconductor Reliability: Challenges and Solutions for Successful Integration

Ensuring 3D IC Semiconductor Reliability: Challenges and Solutions for Successful Integration
by Kalar Rajendiran on 10-25-2023 at 10:00 am

3D IC Cross Section Illustration

One of the most promising advancements in the semiconductor field is the development of 3D Integrated Circuits (3D ICs). 3D ICs enable companies to partition semiconductor designs and seamlessly integrate silicon Intellectual Property (IP) at the most suitable process nodes and processes. This strategic partitioning yields… Read More


The Path to Chiplet Architecture

The Path to Chiplet Architecture
by Paul McLellan on 10-19-2023 at 10:00 am

The Path to Chiplet Architecture

If you have anything to do with the semiconductor industry, you already know that one of the hottest areas for both manufacturing and EDA are systems designed with advanced packaging, basically putting more than one die (aka chiplets) in the same package.

When 3D packaging was first introduced, there were not really any effective… Read More


Placement and Clocks for HPC

Placement and Clocks for HPC
by Paul McLellan on 10-11-2023 at 10:00 am

cts

You are probably familiar with the acronym PPA, which stands for Power/Performance/Area. Sometimes it is PPAC, where C is for cost, since there is more to cost than just area. For example, did you know that adding an additional metal layer to a chip dramatically increases the cost, sometimes by millions of dollars? It requires a … Read More


Optimizing Shift-Left Physical Verification Flows with Calibre

Optimizing Shift-Left Physical Verification Flows with Calibre
by Peter Bennet on 09-26-2023 at 6:00 am

Shift-left with Calibre

Advanced process nodes create challenges for EDA both in handling ever larger designs and increasing design process complexity.

Shift-left design methodologies for design cycle time compression are one response to this. And this has also forced some rethinking about how to build and optimize design tools and flows.

SemiWiki… Read More


Podcast EP179: An Expert Panel Discussion on the Move to Chiplets

Podcast EP179: An Expert Panel Discussion on the Move to Chiplets
by Daniel Nenni on 09-01-2023 at 10:00 am

Dan is joined by a panel of experts to discuss chiplets and 2.5/3D design. The panelists are: Saif Alam – Vice President of Engineering at Movellus Inc., Tony Mastroianni Siemens EDA- Advanced Packaging Solutions Director and Craig Bishop – CTO Deca Technologies.

In this spirited and informative discussion the … Read More