Have you seen the latest design rule manuals? At 28nm and 20nm design sign-off is no longer just DRC and LVS. These basic components of physical verification are being augmented by an expansive set of yield analysis and critical feature identification capabilities, as well as layout enhancements, printability, and performance… Read More
Tag: semiconductor
3D Thermal Analysis
Matt Elmore of ANSYS/Apache has an interesting blog posting about thermal analysis in 3D integrated circuits. With both technical and economic challenges at process nodes as we push below 28nm, increasingly product groups are looking towards through-silicon-via (TSV) based approaches as a way of keeping Moore’s law… Read More
Laker Analog Prototyping
Over the years many attempts have been made to increase the level of automation in analog design. Most of these have not been especially successful. Probably part of the reason was inadequate technology but also there is an attitude that “real” analog designers design polygons on the bare silicon. I think two things… Read More
Extreme Ultra Violet (EUV)
EUV is the great hope for avoiding having to go to triple (and more) patterning if we have to stick with 193nm light. There were several presentations at Semicon about the status of EUV. Here I’ll discuss the issues with EUV lithography and in a separate post discuss the issues about making masks for EUV.
It is probably worth … Read More
Silicon on Insulator (SOI)
I attended a panel session followed by a party during Semicon to celebrate Soitec’s 20th birthday. Officially it was titled An Insider’s Look at the Future of Mobile Technologies. But in reality it was a look at the future possibilities for SOI.
Silicon on Insulator (SOI) has been a sort of bastard child of semiconductor.… Read More
Direct Write E-beam
One of the presenters at the standing-room only litho session at Semicon this week was Serge Tedesco, the litho program manager at CEA-Leti in Grenoble France. He is running a program called IMAGINE for maskless lithography. Chips today are built using a reticle (containing the pattern for that layer of the chip) which is exposed… Read More
Using Accurate Models to Debug Cellphones
There is an interesting Gizmodo review of an HTC Android-based smartphone. The basically positive review (as good as the iPhone, best Android phone at the time) ends up with an update:UPDATE: After more extensive testing there’s something a little weird going on. You’ll probably only see this while gaming, but there’s… Read More
Nokia: the Epic Version
Whenever I write about the handset industry, lots of people seem to be interested. As I’ve said before, my go to person for the industry but especially for Nokia, is Tomi Ahonen. He has written a long (and I mean long, it is nearly 30,000 words) indictment of Elop’s tenure at Nokia and how he has destroyed one of the most … Read More
Semicon West
I have been spending some time at Semicon West at the Moscone center the last couple of days. Since it was only a month ago that I was there for DAC, the first contrast is the size of the show. DAC didn’t fill Moscone South. Semicon fills Moscone South, and North, and the corridor between. And Moscone West on the other side of 4th … Read More
Atrenta Technology Forum, Japan
The 1st Atrenta Technology Forum in Japan (well, it used to be the user group meeting, so it’s only the first in a very technical sense) is next week on July 19th from 1pm until 5.15pm. It will be held in the Shin-Yokohama Kokusai Hotel (how to access it here).
In the unlikely event that non-Japanese are reading this blog, here’s… Read More