In 1985 Morris Chang was recruited by the Taiwanese government to help develop the emerging semiconductor industry. In 1986 Morris joined the Hsinchu based non profit research institute ITRI as Chairman and President and launched what would be TSMC’s first semiconductor wafer fabrication plant on the ITRI campus. Taiwan… Read More
Cadence has a series of webinars about their digital flow, focused on 28nm design. It is easy for all of us in the EDA ecosystem to assume that everyone is already doing 20/22nm design, if not 14nm already. But in fact most designs are still being done at 45nm and 65nm; 28nm is still a big challenging step.
One of the tools in the Cadence… Read More
Josefina Hobbs, a solutions architect at Synopsys, shows the integration of Synopsys Protocol Analyzer with SpringSoft’s Verdi using the Verdi Interoperability Apps (VIA) which gives open access to the Verdi KDB and FSDB databases. She also demonstrates protocol debug made easy using the Protocol Analyzer. This gives… Read More
The Wi-Fi Alliance is an industry consortium dedicated to driving adoption of the various Wi-Fi standards which also go under the rather less catchy name of IEEE 802.11x (where the x varies depending on the generation of the standard, right now a, b, g or n). They also certify devices for interoperability.
Wi-Fi Alliance says that… Read More
About 4 years ago some of my semiconductor cohorts urged me to blog. “Hey Dan, you’re a funny guy, write about EDA and IP, make us laugh!” Of course what I think is funny most people think is snarky, which is a nice word for being a smart ass. The traditional semiconductor press was crumbling, the non traditional EDA websites were outdated,… Read More
Optimizing logical, physical, electrical, and manufacturing effects, Cadence digital implementation technology eliminates iteration without sacrificing design quality by addressing timing sensitivity, yield variation, and leakage power from the start. … Read More
Josefina Hobbs, a solutions architect at Synopsys, demonstrates protocol debug made easy using the Synopsys Protocol Analyzer. This gives users a graphical view of the transfers, transaction, packets and handshaking of a protocol. The video also shows the integration of Synopsys Protocol Analyzer with SpringSoft’s… Read More
I learn a lot these days through webinars and videos because IC design tools like schematic capture and custom layout are visually oriented. Today I watched a video presentation from Steve Lewis and Stacy Whiteman of Cadence that showed how Virtuoso 6.1.5 is used in a custom IC design flow:… Read More
Selectively automating non-critical aspects of custom IC design allows engineers to focus on precision-crafting their designs. Cadence circuit design solutions enable fast and accurate entry of design concepts, which includes managing design intent in a way that flows naturally in the schematic. Using this advanced, parasitic-aware… Read More
Back before Denali was acquired by Cadence they used to run an annual conference called MemCon. Since Denali was the Switzerland of EDA, friend of everyone and enemy of none, there would be presentations from other memory IP companies and from major EDA companies. For example, in 2010, Bruggeman, then CMO of Cadence, gave the opening… Read More
